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EDA365电子工程师网»技术社区 › 电子技术社区 › SI仿真资料与模型 › PCB Designer’s si guide
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PCB Designer’s si guide

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发表于 2008-5-26 11:07 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式

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PCB Designer's SI GUIDETable of Content ) a5 x* e+ N0 x- @1 |, p0 n
Basics of SI___________________________________________________________________5
2 @, z$ W- `" @/ j4 n1.1 When Speed is important? _____________________________________________5
& P# }+ j2 J6 c- h; w- {+ t) H8 J1.1.1 Acceptable Voltage and timing values ________________________________5 ' O* t+ q% [  A2 H9 i+ Q2 i! W
1.2 Signal Integrity ______________________________________________________5
5 h' e0 X; v+ F  d- @, g& p! ?1.2.1 Waveform Voltage Accuracy _______________________________________5 / ]$ X* d* |6 @6 o1 E* G
1.2.2 Timing_________________________________________________________5
# l& S1 Z/ q$ ]1 N/ {1.3 Speed of currently used logic families ____________________________________5 5 i) g5 x. b$ Z5 p( Q
1.3.1 Transition Electrical Length (TEL) __________________________________6
: e# E# W; a+ t5 Z% k1.3.2 Critical length ___________________________________________________6 0 w; D$ g4 k0 a/ n* ]+ q; ?  W5 d
1.3.3 What is Transmission Line? ________________________________________6
! W( R: ~( r5 G9 B5 Q3 q1.3.4 What is moving in a Transmission line?_______________________________6
1 ~5 a3 g$ H0 R& D8 N# C1.3.5 Power Plane Definition____________________________________________6 $ H7 M1 A# V+ Q) g( n2 N
1.3.6 The concept of Ground ____________________________________________7
2 B; `" m7 j3 \" y: {* b8 q1.4 STRIPLINE circuit with Electromagnetic field _____________________________7
3 W7 r5 @, [; c8 o1.5 RLC Transmission Line Model _________________________________________8
4 S& i: Y8 {4 M7 m1.5.1 What is Impedance? ______________________________________________8
8 k8 P9 n. n* E' V" e) ^* L3 k1.5.2 A Practical impedance equation for microstrip _________________________8
' X4 L, H! Y1 {5 |) l9 J, ~$ H1.5.3 What is relative dielectric constant Er? _______________________________9 - e+ V$ D! o4 z" S
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2 Interconnections for High Speed Digital Circuits _______________________________10

8 a& R- D& i! y1 W2.1.1 Summary______________________________________________________10
7 W, o9 t" K" T8 Y2.2 Examples of dynamic interfacing problems _______________________________10
' F1 K: v* p8 e# L2.3 IC Technology and Signal Integrity _____________________________________12
* ?9 C1 t; t+ ?. i  {9 L3 o2.4 Speed and distance __________________________________________________14
- n. a# K8 Q9 m) T& i# P+ I- k2.5 Digital signals: Static interfacing _______________________________________15
& G" G0 z! G5 i. ~2.6 Digital signals: Dynamic interfacing ____________________________________16 : b) B) z+ U, y- C- [- y
2.7 Review questions ___________________________________________________18 ) S$ m) y+ ^2 Q1 |1 C- W- V

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3 Interconnection Models____________________________________________________20
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3.1 Summary__________________________________________________________20
' y/ j9 }( y5 R5 f( ~* @# F3.2 Reference model for interconnection analysis _____________________________20
0 g1 ~' B; D- x3 s( w  B/ q; I3.3 Receiver model_____________________________________________________21
6 Q: g0 [  s# Z3.4 RC interconnection model ____________________________________________23
  h! N8 N/ N4 s7 ?# Z3.5 Parameters of the interconnection ______________________________________25 ) Y9 i2 f! I8 r
3.6 Refined models _____________________________________________________26
* k' X, `: r# U% g7 ~- p/ x3.7 Review question ____________________________________________________28
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4 Transmission Line Models _________________________________________________31

, R4 W1 x) D$ T+ F  z2 b4.1 Summary__________________________________________________________31 / Y- s. x$ z* e
4.2 Transmission line models _____________________________________________31
* }/ Q7 `+ g6 a4.3 Loss-less transmission lines ___________________________________________32
* M$ P) S1 q  R4.4 Critical Length _____________________________________________________34 , m! M! H5 a' w0 `8 L) T. K
4.5 Reference transmission line model______________________________________35 5 ]: }  ~, o) |- |  r6 S. u
4.6 Line driving _______________________________________________________36
. V2 s; S6 ~3 u( X1 U& c0 H4.7 Propagation and reflected waves _______________________________________37
. u8 J( S) l( S0 d2 X4.8 A sample system____________________________________________________39
( _  Q' G) Y  |" z* Z* r7 x4.9 Review questions ___________________________________________________42
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PCB Designer’s SI Guide Page 2 Venkata
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5 Analysis techniques _______________________________________________________45
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5.1 Summary__________________________________________________________45 ' m5 C5 d! l7 n4 x# e
5.2 Transmission time and skew___________________________________________45
" O8 F+ V) @# {5 ]5.3 Effects of termination resistance _______________________________________46 ' q5 _: B0 q2 X- Q( O7 w
5.4 Lattice diagram _____________________________________________________48
+ Y2 a5 l; o8 t" A+ \  [5.5 Examples of Real Lines ______________________________________________49 / R+ u! M& k, g1 I5 y) ]& @2 Z
5.6 Simulation code ____________________________________________________51 0 e, }/ R/ Q: Y/ g' p
5.7 Examples of results__________________________________________________54
. l8 }8 k" t8 F# R  j- ^5.8 Review questions ___________________________________________________55
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6 Design guide for interconnection ____________________________________________57
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6.1 Summary__________________________________________________________57 " F# e- c) i+ }* Q; `
6.2 Incident wave switching ______________________________________________57 & r- I  t. F' [4 ]$ r- D$ c
6.3 Effects of capacitive loading __________________________________________58
' c. y( C' y3 P8 t6.4 Termination circuits _________________________________________________59
* d( n& J# [1 Y6.4.1 Passive termination______________________________________________60
; n" ~. `8 ?$ B6.4.2 Low power termination___________________________________________61 ; p7 _% ~2 X( j9 F, z/ G
6.4.3 Active low power termination circuit. _______________________________61 8 ?+ h+ \  n4 \+ Y& [% y
6.5 Driving point-to-point lines ___________________________________________62 " W) I4 r$ g9 r5 |: p. p$ `$ ~
6.6 Driving bused lines __________________________________________________64 : K: [# m4 C0 d& }% R' ?
6.7 Design guidelines ___________________________________________________67
9 k* W+ d( ]2 f3 i& w/ l+ h6.8 Review questions ___________________________________________________67

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 楼主| 发表于 2008-5-26 11:09 | 只看该作者
Signal Integrity in Digital Circuits ___________________________________________70 , j- d0 r+ Q+ M# F- L: n
7.1 Crosstalk __________________________________________________________70
+ K- I& k+ E5 [: _# ]7.1.1 Summary______________________________________________________70   l! R( c5 f9 U& l& e
7.2 Examples of signal integrity problems ___________________________________70
  Y( H' f1 s4 U8 O" D) w9 l% a/ @0 R7.3 Simplified Model for Crosstalk Analysis _________________________________71
: h7 N. [) w2 R3 T" E( e; p7.4 Forward and backward crosstalk _______________________________________74 ' R, r/ z3 @4 T2 t! V5 `( a6 {
7.5 Examples__________________________________________________________76 * k) k: R' |: o; T; z) d
7.6 Near-end and Far-end crosstalk ________________________________________80 + z1 D( j( ]) }4 Z3 `9 C3 B
7.7 Review questions ___________________________________________________81
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8 Design Guide to Handle Crosstalk ___________________________________________85
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8.1 Summary__________________________________________________________85
+ C' [+ n* O& ?8.2 Effects of Crosstalk __________________________________________________85
0 I# u0 l5 M6 U  R% o8.3 Passive countermeasures _____________________________________________86
4 P) x9 G% o. V$ T, ]# F# [8.4 Active Control of Crosstalk ___________________________________________92
; \2 F+ N3 i  R6 ^9 o3 L8.5 Review questions ___________________________________________________94   W% v4 j  u( c8 j4 @% C9 Y
9 Ground Bounce and Switching Noise_________________________________________97

$ S6 w! e) s8 g# Q9 J; P5 D4 T9.1 Summary__________________________________________________________97 9 Z6 G! c% b3 V8 f, J
9.2 The totem pole Current Spike__________________________________________97
6 T2 M0 I& B0 k: x9.3 Current flow in the output capacitance __________________________________100
/ `9 W! t* j& g9.4 Total Ground Bounce _______________________________________________100
/ H4 ~- k, L3 \# c; M4 c9.5 Review questions __________________________________________________105
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10 Design Guide for Ground & Power Distribution _____________________________107

% _1 u) I$ T' Z0 l( l10.1 Summary_________________________________________________________107
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PCB Designer’s SI Guide Page 3 Venkata
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10.2 Decoupling Capacitors ______________________________________________107
, B: ]/ g- ^& A# S( t6 n* S. L10.3 Placement of bypass Capacitors _______________________________________113
- E  Q6 w1 g1 M4 R) E$ K, b9 Y10.4 Ground and power distribution________________________________________114 3 u: r: D1 @3 t
10.5 Clock distribution __________________________________________________115
6 ~' q. g+ K* `5 M10.6 Review Questions __________________________________________________118 4 W) ^4 u- }9 ?6 [4 W
11 Laboratory Experience _________________________________________________120 : i: \' N1 ^/ F0 {& |1 P
11.1 Summary_________________________________________________________120 & D' P& p* J$ t) l7 Q
11.2 Aim of the experience_______________________________________________120
0 L/ x: i' q! ^4 z  q11.3 Generator Parameters _______________________________________________122 * z5 R: q3 U) {0 v  R5 d! `
11.4 Cable Parameters __________________________________________________123 7 f2 a- J* [' P5 E& `- J1 w
11.5 Mismatch at driver and at termination __________________________________124 % G9 Z/ ?+ d+ y3 c) D
11.6 Capacitive Load ___________________________________________________125 1 ]( j2 W. D" H, j+ d' _
11.7 7. Time-domain reflectometer ________________________________________127 # @$ H: c; i# s; Z2 n
11.8 Driving the line with logic devices _____________________________________128
; \$ y; v. C: N; e4 i12 SI Analysis Strategy____________________________________________________133
$ O7 f7 `4 m  v8 y12.1.1 A modern high-speed design methodology must involve the at least the following: ____________________________________________________________133
) ]: E! [$ K: i; V12.2 POSSIBLE HIGH-SPEED DESIGN APPROACHES ______________________133
1 _" j& S8 n- U) u6 c12.2.1 There are two fundamental types of conditions that need to be considered for solution space analysis:__________________________________________________134 9 X' ?# x) u4 X& Q
12.3 SOLUTION SPACE ANALYSIS _____________________________________135 ! |5 S: Z/ x" ]3 q* C
12.3.10 v- ^1 B7 ~3 n8 F0 H4 z% F/ ]
STEP 1 — DEFINING THE INITIAL TOPOLOGY __________________135
0 d+ x4 e% I. i& |6 \+ T$ ~3 N7 q* U+ s12.3.2 STEP 2 — DEFINE MANUFACTURING TOLERANCES AND THEIR MIN/MAX VALUES ___________________________________________________135
4 i2 M6 ]2 R# x* J/ C9 g9 F! L12.3.3( \# Q& b) Z, e( x3 y& F
STEP 3 — DEFINE THE STARTING POINT FOR DESIGN VARIANCES 136
- b8 g1 i  d2 e6 N12.3.4
# K2 x0 K3 S4 u: X6 O2 z/ [STEP 4 — SET UP AND RUN A NUMBER OF SIMULATION CASES _136 9 [3 z, s9 k. v& A: i$ w
12.3.5 STEP 5 — EXAMINE THE SIMULATION RESULTS, IDENTIFY WHICH CASES FAILED AND WHY ____________________________________________136
! {, E: M1 s8 ]* E2 s12.3.6 STEP 6 — ADAPT THE TOPOLOGY AND DESIGN RULES AS APPROPRIATE _______________________________________________________137 ' K+ B2 D6 _5 O' O
12.3.7 STEP 7 — REPEAT STEPS 4-6 UNTIL THE TOPOLOGY CONVERGES ON A SET OF VALUES THAT PASS FOR ALL CASES ANALYZED __________137 5 A1 o; y# w8 }6 q$ c- ~  ^3 H& r+ a
12.3.8: ~( j* k& s# f7 c& V% D
STEP 8 — DERIVE DESIGN RULES FOR THE TARGET CAD SYSTEM 137
+ s: W- I. @. h  l  [- C$ L+ N12.3.9 STEP 9 — DRIVE THE CAD RULES INTO THE CAD DATABASE, AND USE THEM TO DRIVE THE PLACEMENT/ROUTING PROCESSES ___________138 1 ~8 Y4 N) l* a- o: W
12.3.10 STEP 10 — POST LAYOUT SI ANALYSIS ______________________139
% Q: w+ u) Q  [5 R0 A12.4 CONCLUSION____________________________________________________139
) |+ R' L2 s0 G1 h13 Glossary _____________________________________________________________141
9 U5 l5 |, k/ M3 m; B
PCB Designer’s SI Guide Page 4Venkata
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