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EDA365电子工程师网»技术社区 › 电子技术社区 › SI仿真资料与模型 › PCB Designer’s si guide
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PCB Designer’s si guide

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snowwolfe

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发表于 2008-5-26 11:07 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式

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PCB Designer's SI GUIDETable of Content
; O! a$ l$ o5 |" H: jBasics of SI___________________________________________________________________5
$ e+ l# Z  A' `4 B1.1 When Speed is important? _____________________________________________5
( ?' ^% @# H& B* m7 |" ?# h  W+ x1.1.1 Acceptable Voltage and timing values ________________________________5
) y  `6 J. t  b. I$ T/ n+ s& D* f* A1.2 Signal Integrity ______________________________________________________5
# M0 L6 i' Y" h( p2 h8 i% M1.2.1 Waveform Voltage Accuracy _______________________________________5
& [9 {+ b. L1 c% I9 S  w1.2.2 Timing_________________________________________________________5 7 i: E3 t& {  S6 m. C; X
1.3 Speed of currently used logic families ____________________________________5 # Z5 a, P7 F% z: B, W/ k
1.3.1 Transition Electrical Length (TEL) __________________________________6 1 [1 g9 E& P- y5 _8 g) R
1.3.2 Critical length ___________________________________________________6 * \1 y7 d- n& z4 ]; v# F$ F* m
1.3.3 What is Transmission Line? ________________________________________6
" i# s* ~: h" o" f; w1.3.4 What is moving in a Transmission line?_______________________________6
, Y) I1 Y0 ?$ k6 M& ^6 q1.3.5 Power Plane Definition____________________________________________6 1 j0 Y+ l) t. }- i/ o$ U) h& e
1.3.6 The concept of Ground ____________________________________________7
" \, C& g3 h& J; s! r+ n  H1.4 STRIPLINE circuit with Electromagnetic field _____________________________7 9 `' E) e8 S5 ]. I$ @( g, W2 y
1.5 RLC Transmission Line Model _________________________________________8 , }2 `: R' h; a+ T0 L0 p7 I
1.5.1 What is Impedance? ______________________________________________8
5 B; M7 }' I+ e0 s, `1.5.2 A Practical impedance equation for microstrip _________________________8 $ B" e  `( U2 N. N
1.5.3 What is relative dielectric constant Er? _______________________________9
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2 Interconnections for High Speed Digital Circuits _______________________________10
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2.1.1 Summary______________________________________________________10
; J8 F, I0 Y' q% r2.2 Examples of dynamic interfacing problems _______________________________10 / z- n0 \, ~9 t" ~, N
2.3 IC Technology and Signal Integrity _____________________________________12 ! ]3 F- T+ Y0 _4 ^! f# D
2.4 Speed and distance __________________________________________________14
' @1 w9 `- \: J/ t6 u6 u2.5 Digital signals: Static interfacing _______________________________________15 * K# K' B  v1 ]. f, B
2.6 Digital signals: Dynamic interfacing ____________________________________16 ' o: u$ J( v' Y  |* r0 v! p% \( i. V
2.7 Review questions ___________________________________________________18 - L$ i+ |* u! Q! h. C) V
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3 Interconnection Models____________________________________________________20

6 n, j8 u5 v$ G! s0 c3.1 Summary__________________________________________________________20 ) l+ \; r- r/ b  u) J/ u
3.2 Reference model for interconnection analysis _____________________________20
7 z& ?* M/ U; a! C. B7 z5 F2 ~4 X4 E( l3.3 Receiver model_____________________________________________________21
& L; p, N8 a: Q( ]3.4 RC interconnection model ____________________________________________23 ' w3 V. g4 Y% S: l. x
3.5 Parameters of the interconnection ______________________________________25
6 |9 E$ p. u( J6 d6 ~6 r3.6 Refined models _____________________________________________________26
+ U5 i. k+ @3 p8 N7 _3.7 Review question ____________________________________________________28 0 k. S; }" N9 O/ n

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4 Transmission Line Models _________________________________________________31
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4.1 Summary__________________________________________________________31
1 `; n' q7 J7 W6 K: Q4.2 Transmission line models _____________________________________________31 ! k' b7 N8 \0 A& m, k
4.3 Loss-less transmission lines ___________________________________________32
( `2 \6 H9 o: E$ ]4 H% P$ P$ C4.4 Critical Length _____________________________________________________34
  Y  f0 @  h4 w$ z  g2 e2 X* }4 w4.5 Reference transmission line model______________________________________35
/ ]: }. p( \+ L$ f7 c! p4.6 Line driving _______________________________________________________36
4 v- [' m8 T  d) A4.7 Propagation and reflected waves _______________________________________37
7 y* E  F$ Y5 K1 K; d7 o4.8 A sample system____________________________________________________39
5 m8 d, k+ c* u6 C  |, t! A4.9 Review questions ___________________________________________________42
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PCB Designer’s SI Guide Page 2 Venkata

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5 Analysis techniques _______________________________________________________45

+ X8 e  y) r" Y1 ]6 v( g5.1 Summary__________________________________________________________45 + c0 ?# v. h9 W. n
5.2 Transmission time and skew___________________________________________45
; P9 a0 ^1 F4 B/ f5.3 Effects of termination resistance _______________________________________46 ' D" m0 d1 T% a1 {& y! d
5.4 Lattice diagram _____________________________________________________48 ! {1 s, r4 {4 p! X7 c1 ^! i
5.5 Examples of Real Lines ______________________________________________49
9 h! E& x" w, A5 M8 E5.6 Simulation code ____________________________________________________51 3 n5 E' b$ l6 G# {$ c
5.7 Examples of results__________________________________________________54
  R8 K0 k2 Z5 M0 N9 L/ S5.8 Review questions ___________________________________________________55 , o' D6 ~' ~$ J7 h' y' t5 n2 W
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6 Design guide for interconnection ____________________________________________57

3 N- m/ |/ t( R% Y. r& l9 Y$ ~6.1 Summary__________________________________________________________57
! X; x9 @/ g& h) J9 k, R. G; ?# d6.2 Incident wave switching ______________________________________________57
2 \% I, b/ N/ P6.3 Effects of capacitive loading __________________________________________58
2 h  L3 l5 G9 }( j$ \6.4 Termination circuits _________________________________________________59
$ S6 v/ Q& f* j+ j$ H6.4.1 Passive termination______________________________________________60 3 D2 d$ _6 P; l4 @7 f5 b
6.4.2 Low power termination___________________________________________61 : M4 E! o+ J# T) z
6.4.3 Active low power termination circuit. _______________________________61
/ u5 @- T. S$ o6.5 Driving point-to-point lines ___________________________________________62 - @  a" N) d/ o& \7 H: M
6.6 Driving bused lines __________________________________________________64 " D- n; _. {/ n5 T
6.7 Design guidelines ___________________________________________________67 0 a9 ], E% n) p0 z- K) ?
6.8 Review questions ___________________________________________________67

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 楼主| 发表于 2008-5-26 11:09 | 只看该作者
Signal Integrity in Digital Circuits ___________________________________________70
6 _: F' L5 R' V& M5 a  q6 [7.1 Crosstalk __________________________________________________________70 ( h7 T& B) r! v- T* D0 Y0 K
7.1.1 Summary______________________________________________________70
9 S) i+ u" f, q, P/ }8 S7.2 Examples of signal integrity problems ___________________________________70 7 ?# V( l' b& B/ ?
7.3 Simplified Model for Crosstalk Analysis _________________________________71 2 G/ I+ d/ s+ A) ^1 P- t. i6 M0 I9 f+ n
7.4 Forward and backward crosstalk _______________________________________74
1 ?) |& Z9 u! M) V" r+ _7.5 Examples__________________________________________________________76 * ]9 N5 \! k# T: }! [: G6 r
7.6 Near-end and Far-end crosstalk ________________________________________80 # a. x1 K- b# Y  I
7.7 Review questions ___________________________________________________81 # _$ x$ h/ X9 w7 W3 E+ u! Z
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8 Design Guide to Handle Crosstalk ___________________________________________85
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8.1 Summary__________________________________________________________85
6 m" `1 n2 t% x5 j- A* z8.2 Effects of Crosstalk __________________________________________________85
; c: b9 t- @  k" S$ Y8.3 Passive countermeasures _____________________________________________86
6 z, B  E' E+ f9 S8.4 Active Control of Crosstalk ___________________________________________92 ; j. k& c! ], k
8.5 Review questions ___________________________________________________94
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9 Ground Bounce and Switching Noise_________________________________________97
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9.1 Summary__________________________________________________________97 1 w' s9 E* x) Q, F+ G$ f" ]7 E
9.2 The totem pole Current Spike__________________________________________97 - J: \. i2 Y( l& r: s2 X- _( v7 O
9.3 Current flow in the output capacitance __________________________________100 ' e! m2 W$ m4 {* p+ f1 ]
9.4 Total Ground Bounce _______________________________________________100 8 D3 ?! L. T. |8 r
9.5 Review questions __________________________________________________105
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10 Design Guide for Ground & Power Distribution _____________________________107

1 F; Z& V& f5 \9 [10.1 Summary_________________________________________________________107
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PCB Designer’s SI Guide Page 3 Venkata
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10.2 Decoupling Capacitors ______________________________________________107
2 k5 X  \( \4 S8 G10.3 Placement of bypass Capacitors _______________________________________113 , _- P; e% x# T
10.4 Ground and power distribution________________________________________114
( u2 P  [2 F, ~6 m; Y5 h10.5 Clock distribution __________________________________________________115
. ?; N4 F; F0 q* t& o! N# E10.6 Review Questions __________________________________________________118
; y* m$ ]7 Z2 q4 L0 N4 t) r4 R11 Laboratory Experience _________________________________________________120
& ~. j+ I/ d9 h# j- N11.1 Summary_________________________________________________________120 . e( u7 y6 U0 D" c8 u( u
11.2 Aim of the experience_______________________________________________120 9 a" C5 E( m  _1 j/ C) f- j
11.3 Generator Parameters _______________________________________________122 * V7 S0 N( a" N
11.4 Cable Parameters __________________________________________________123 & Z1 {  c: T% A0 m! _9 w/ p. ]
11.5 Mismatch at driver and at termination __________________________________124 ) d1 V0 V7 J/ a4 R$ q
11.6 Capacitive Load ___________________________________________________125 - h6 y7 Y2 N: z5 d9 Z
11.7 7. Time-domain reflectometer ________________________________________127 : k7 b+ a3 B4 }' U0 i
11.8 Driving the line with logic devices _____________________________________128
3 J9 M3 h7 C& f; P* f7 L: Y& [6 B12 SI Analysis Strategy____________________________________________________133
) {. V" f; u  K0 k* |+ q. m12.1.1 A modern high-speed design methodology must involve the at least the following: ____________________________________________________________133
2 x& v! Y, x2 L4 M* I. s8 d# h" ?4 {12.2 POSSIBLE HIGH-SPEED DESIGN APPROACHES ______________________133 5 g9 `* |$ R) X- C* s' g
12.2.1 There are two fundamental types of conditions that need to be considered for solution space analysis:__________________________________________________134
) B( H  R4 i+ j3 E  c; S  W12.3 SOLUTION SPACE ANALYSIS _____________________________________135
$ R& A$ H7 y4 Z! z, f12.3.1, m7 x8 W& l, i3 n: h
STEP 1 — DEFINING THE INITIAL TOPOLOGY __________________135 5 [" }& Z- H* Y8 N& P$ D7 T  l6 }
12.3.2 STEP 2 — DEFINE MANUFACTURING TOLERANCES AND THEIR MIN/MAX VALUES ___________________________________________________135
. m1 g) x: Q, J" Y) G( N12.3.3
) P/ y5 ]$ _- FSTEP 3 — DEFINE THE STARTING POINT FOR DESIGN VARIANCES 136 3 w$ v4 r- K4 I' f  Q
12.3.4
+ T. J7 W9 ~' ?% M$ ZSTEP 4 — SET UP AND RUN A NUMBER OF SIMULATION CASES _136
) r% w' W" o  K0 H: I5 {2 k. k! Q12.3.5 STEP 5 — EXAMINE THE SIMULATION RESULTS, IDENTIFY WHICH CASES FAILED AND WHY ____________________________________________136
9 R+ t' A$ A0 l* g6 T1 l& j2 d12.3.6 STEP 6 — ADAPT THE TOPOLOGY AND DESIGN RULES AS APPROPRIATE _______________________________________________________137
; N# e! ^! C7 N! s12.3.7 STEP 7 — REPEAT STEPS 4-6 UNTIL THE TOPOLOGY CONVERGES ON A SET OF VALUES THAT PASS FOR ALL CASES ANALYZED __________137
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STEP 8 — DERIVE DESIGN RULES FOR THE TARGET CAD SYSTEM 137
+ [% H( E, S4 m( m9 ^12.3.9 STEP 9 — DRIVE THE CAD RULES INTO THE CAD DATABASE, AND USE THEM TO DRIVE THE PLACEMENT/ROUTING PROCESSES ___________138 9 Q3 p$ \- p$ z5 F% F2 u- q
12.3.10 STEP 10 — POST LAYOUT SI ANALYSIS ______________________139 ( \2 \  ~6 G" T
12.4 CONCLUSION____________________________________________________139 0 m6 {7 n1 o" Z6 x( e! e/ J7 B8 _: k
13 Glossary _____________________________________________________________141 % H, U2 g" d0 {' V6 @5 f
PCB Designer’s SI Guide Page 4Venkata
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