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哪位大神过来看看啊，这Altium真让人受不鸟了。
- X3 L( D# H5 h' T" s最近自己画个图，用层次原理图进行的设计，其中还使用了 harness，结果一编译就出警告“has multiple names”，也不知道哪里出了问题，改了好多地方，包括工程设置，也都不行，上网上查找的方法也不管用。) k: ?3 r5 Z$ G" R8 k; ~4 w
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Class Document Source Message Time Date No.
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[Warning] TOP.SchDoc Compiler Nets Bus Slice CONF_FLASH_A[24..0] has multiple names (Net Label CONF_FLASH_A[24..0],Net Label CONF_FLASH_A[24..0],Port FPGA_CONFIG.CONF_ADDR[24..0],Port FPGA_CONFIG.CONF_ADDR[24..0]) 17:49:14 2016/3/9 29
8 g( D) P& Z; U" i: ~[Warning] FPGA_CONFIG.SchDoc Compiler Nets Bus Slice CONF_FLASH_A[24..0] has multiple names (Net Label CONF_FLASH_A[24..0],Port FPGA_CONFIG.CONF_ADDR[24..0]) 17:49:14 2016/3/9 305 j0 b* g2 U2 a7 X0 V& L
[Warning] TOP.SchDoc Compiler Nets Bus Slice CONF_FLASH_D[15..0] has multiple names (Net Label CONF_FLASH_D[15..0],Net Label CONF_FLASH_D[15..0],Net Label CONF_FLASH_D[15..0],Port FPGA_CONFIG.CONF_DATA[15..0],Port FPGA_CONFIG.CONF_DATA[15..0]) 17:49:14 2016/3/9 31
9 |) j& E& b F[Warning] FPGA_CONFIG.SchDoc Compiler Nets Bus Slice CONF_FLASH_D[15..0] has multiple names (Net Label CONF_FLASH_D[15..0],Port FPGA_CONFIG.CONF_DATA[15..0]) 17:49:14 2016/3/9 323 I# [( d7 X7 x0 A7 y( u
[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[0]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A0 (Inferred),Net Label CONF_FLASH_A0,Port FPGA_CONFIG.CONF_ADDR0 (Inferred)) 17:49:14 2016/3/9 338 F# `' t. b, z
[Warning] TOP.SchDoc Compiler Nets Element[0]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A0,Net Label CONF_FLASH_A0 (Inferred),Net Label CONF_FLASH_A0,Net Label CONF_FLASH_A0 (Inferred),Port FPGA_CONFIG.CONF_ADDR0 (Inferred),Port FPGA_CONFIG.CONF_ADDR0 (Inferred)) 17:49:14 2016/3/9 34
$ Y7 m* ? m! S[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[0]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A0,Net Label CONF_FLASH_A0 (Inferred),Port FPGA_CONFIG.CONF_ADDR0 (Inferred)) 17:49:14 2016/3/9 35
4 L1 Z/ k6 ~& C0 K( [[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[0]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D0 (Inferred),Net Label CONF_FLASH_D0,Port FPGA_CONFIG.CONF_DATA0 (Inferred)) 17:49:14 2016/3/9 36
2 ~8 b7 m) ~8 ?6 @( e[Warning] TOP.SchDoc Compiler Nets Element[0]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D0,Net Label CONF_FLASH_D0 (Inferred),Net Label CONF_FLASH_D0,Net Label CONF_FLASH_D0 (Inferred),Net Label CONF_FLASH_D0 (Inferred),Port FPGA_CONFIG.CONF_DATA0 (Inferred),Port FPGA_CONFIG.CONF_DATA0 (Inferred)) 17:49:14 2016/3/9 37
; f5 g$ p7 ^. @2 F! A5 O8 f[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[0]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D0,Net Label CONF_FLASH_D0 (Inferred),Port FPGA_CONFIG.CONF_DATA0 (Inferred)) 17:49:14 2016/3/9 38
c k. U8 A6 s8 G1 J[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[1]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A1 (Inferred),Net Label CONF_FLASH_A1,Port FPGA_CONFIG.CONF_ADDR1 (Inferred)) 17:49:14 2016/3/9 394 U& y& \# x5 m, A6 X
[Warning] TOP.SchDoc Compiler Nets Element[1]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A1,Net Label CONF_FLASH_A1 (Inferred),Net Label CONF_FLASH_A1,Net Label CONF_FLASH_A1 (Inferred),Port FPGA_CONFIG.CONF_ADDR1 (Inferred),Port FPGA_CONFIG.CONF_ADDR1 (Inferred)) 17:49:14 2016/3/9 40
* _) [$ {" |5 u z; Z' p/ g ^[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[1]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A1,Net Label CONF_FLASH_A1 (Inferred),Port FPGA_CONFIG.CONF_ADDR1 (Inferred)) 17:49:14 2016/3/9 411 y: w) n1 M' b, n
[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[1]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D1 (Inferred),Net Label CONF_FLASH_D1,Port FPGA_CONFIG.CONF_DATA1 (Inferred)) 17:49:14 2016/3/9 425 M! w9 @1 n% ], v, @" F8 d
[Warning] TOP.SchDoc Compiler Nets Element[1]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D1,Net Label CONF_FLASH_D1 (Inferred),Net Label CONF_FLASH_D1,Net Label CONF_FLASH_D1 (Inferred),Net Label CONF_FLASH_D1 (Inferred),Port FPGA_CONFIG.CONF_DATA1 (Inferred),Port FPGA_CONFIG.CONF_DATA1 (Inferred)) 17:49:14 2016/3/9 43. W4 L( q% V+ _& `- Z
[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[1]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D1,Net Label CONF_FLASH_D1 (Inferred),Port FPGA_CONFIG.CONF_DATA1 (Inferred)) 17:49:14 2016/3/9 44 R0 Z0 d" O. u! P
[Warning] TOP.SchDoc Compiler Nets Element[1]: EN has multiple names (Net Label EN1,Net Label EN1,Net Label EN1 (Inferred),Net Label EN1 (Inferred),Port EN_A1) 17:49:14 2016/3/9 45) x3 X. Q/ v* V4 O# J7 Z) H
[Warning] TOP.SchDoc Compiler Nets Element[1]: L_IN has multiple names (Net Label L_IN1,Net Label L_IN1,Net Label L_IN1 (Inferred),Port L_IN_A1) 17:49:14 2016/3/9 46
^: X n. F2 j$ t[Warning] TOP.SchDoc Compiler Nets Element[1]: POWER_OUT has multiple names (Net Label POWER_OUT1,Net Label POWER_OUT1,Net Label POWER_OUT1,Net Label POWER_OUT1 (Inferred),Port POWER_OUT_A1) 17:49:14 2016/3/9 47 U8 B2 u) [* j' L! I+ h7 {
[Warning] TOP.SchDoc Compiler Nets Element[1]: R1C has multiple names (Net Label R1C1,Net Label R1C1,Net Label R1C1 (Inferred),Port R1C_A1) 17:49:14 2016/3/9 48$ H ~. W/ B$ ]
[Warning] TOP.SchDoc Compiler Nets Element[1]: R2C has multiple names (Net Label R2C1,Net Label R2C1,Net Label R2C1 (Inferred),Port R2C_A1) 17:49:14 2016/3/9 49# _7 e: Q5 ^0 y" d1 h& T
[Warning] TOP.SchDoc Compiler Nets Element[1]: RFB has multiple names (Net Label RFB1,Net Label RFB1,Net Label RFB1 (Inferred),Port RFB_A1) 17:49:14 2016/3/9 50
$ |# t- h8 s% E% P8 n[Warning] TOP.SchDoc Compiler Nets Element[1]: SS has multiple names (Net Label SS1,Net Label SS1,Net Label SS1 (Inferred),Net Label SS1 (Inferred),Port SS_A1) 17:49:14 2016/3/9 51& N0 ]7 t# ?3 _/ S0 s
[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[2]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A2 (Inferred),Net Label CONF_FLASH_A2,Port FPGA_CONFIG.CONF_ADDR2 (Inferred)) 17:49:14 2016/3/9 52
9 m" n$ [6 R1 {$ T5 }[Warning] TOP.SchDoc Compiler Nets Element[2]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A2,Net Label CONF_FLASH_A2 (Inferred),Net Label CONF_FLASH_A2,Net Label CONF_FLASH_A2 (Inferred),Port FPGA_CONFIG.CONF_ADDR2 (Inferred),Port FPGA_CONFIG.CONF_ADDR2 (Inferred)) 17:49:14 2016/3/9 53
; e @7 D3 \7 G- I+ a- q1 T5 O5 A6 K[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[2]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A2,Net Label CONF_FLASH_A2 (Inferred),Port FPGA_CONFIG.CONF_ADDR2 (Inferred)) 17:49:14 2016/3/9 548 H. s/ Q. V( j* G
[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[2]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D2 (Inferred),Net Label CONF_FLASH_D2,Port FPGA_CONFIG.CONF_DATA2 (Inferred)) 17:49:14 2016/3/9 55/ W3 w' i" f2 T: p8 t8 [
[Warning] TOP.SchDoc Compiler Nets Element[2]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D2,Net Label CONF_FLASH_D2 (Inferred),Net Label CONF_FLASH_D2,Net Label CONF_FLASH_D2 (Inferred),Net Label CONF_FLASH_D2 (Inferred),Port FPGA_CONFIG.CONF_DATA2 (Inferred),Port FPGA_CONFIG.CONF_DATA2 (Inferred)) 17:49:14 2016/3/9 56& i1 W2 R( I, ]) [ ^5 s6 V
[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[2]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D2,Net Label CONF_FLASH_D2 (Inferred),Port FPGA_CONFIG.CONF_DATA2 (Inferred)) 17:49:14 2016/3/9 579 R: j @' ]) F$ s. I/ Z
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发表于 2016-3-9 17:54
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支持！
反对！
发表于 2016-3-13 15:47
楼主
晕死，好像是因为HARNESS 必须得成对应用。我刚开始画原理图的时候，只在sheet_adc中使用了一个，与它配对的那个没放，结果就出错了，后来都给匹配了就好了。altium 还是有一些不太好用的地方
。再比如说没有差分总线功能，不能单独修改花焊盘，多通道设计序号不能从0开始等等。希望能越来越完善。
