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哪位大神过来看看啊，这Altium真让人受不鸟了。% |' Q! r! s% |2 W
最近自己画个图，用层次原理图进行的设计，其中还使用了 harness，结果一编译就出警告“has multiple names”，也不知道哪里出了问题，改了好多地方，包括工程设置，也都不行，上网上查找的方法也不管用。
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[Warning] TOP.SchDoc Compiler Nets Bus Slice CONF_FLASH_A[24..0] has multiple names (Net Label CONF_FLASH_A[24..0],Net Label CONF_FLASH_A[24..0],Port FPGA_CONFIG.CONF_ADDR[24..0],Port FPGA_CONFIG.CONF_ADDR[24..0]) 17:49:14 2016/3/9 291 u$ w6 B4 D: q4 q4 l! {% m g2 |
[Warning] FPGA_CONFIG.SchDoc Compiler Nets Bus Slice CONF_FLASH_A[24..0] has multiple names (Net Label CONF_FLASH_A[24..0],Port FPGA_CONFIG.CONF_ADDR[24..0]) 17:49:14 2016/3/9 30
! p6 E3 w) @: q$ [, B[Warning] TOP.SchDoc Compiler Nets Bus Slice CONF_FLASH_D[15..0] has multiple names (Net Label CONF_FLASH_D[15..0],Net Label CONF_FLASH_D[15..0],Net Label CONF_FLASH_D[15..0],Port FPGA_CONFIG.CONF_DATA[15..0],Port FPGA_CONFIG.CONF_DATA[15..0]) 17:49:14 2016/3/9 312 Z% R1 Q: D& o) A- Q2 G
[Warning] FPGA_CONFIG.SchDoc Compiler Nets Bus Slice CONF_FLASH_D[15..0] has multiple names (Net Label CONF_FLASH_D[15..0],Port FPGA_CONFIG.CONF_DATA[15..0]) 17:49:14 2016/3/9 32
K# k2 r2 ^8 k2 J* u+ o# x: L[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[0]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A0 (Inferred),Net Label CONF_FLASH_A0,Port FPGA_CONFIG.CONF_ADDR0 (Inferred)) 17:49:14 2016/3/9 33
8 ^9 P) ~* |: m% m[Warning] TOP.SchDoc Compiler Nets Element[0]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A0,Net Label CONF_FLASH_A0 (Inferred),Net Label CONF_FLASH_A0,Net Label CONF_FLASH_A0 (Inferred),Port FPGA_CONFIG.CONF_ADDR0 (Inferred),Port FPGA_CONFIG.CONF_ADDR0 (Inferred)) 17:49:14 2016/3/9 34
) A/ w# Z* X0 m) k0 ][Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[0]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A0,Net Label CONF_FLASH_A0 (Inferred),Port FPGA_CONFIG.CONF_ADDR0 (Inferred)) 17:49:14 2016/3/9 35. a9 y) u+ {; b% q8 L
[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[0]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D0 (Inferred),Net Label CONF_FLASH_D0,Port FPGA_CONFIG.CONF_DATA0 (Inferred)) 17:49:14 2016/3/9 36
" E, t& p. F: V2 C' ~[Warning] TOP.SchDoc Compiler Nets Element[0]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D0,Net Label CONF_FLASH_D0 (Inferred),Net Label CONF_FLASH_D0,Net Label CONF_FLASH_D0 (Inferred),Net Label CONF_FLASH_D0 (Inferred),Port FPGA_CONFIG.CONF_DATA0 (Inferred),Port FPGA_CONFIG.CONF_DATA0 (Inferred)) 17:49:14 2016/3/9 37/ B' _/ _0 c/ S- ?: {
[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[0]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D0,Net Label CONF_FLASH_D0 (Inferred),Port FPGA_CONFIG.CONF_DATA0 (Inferred)) 17:49:14 2016/3/9 38
# J* J$ _( t) ]: t, ?: o+ i/ p[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[1]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A1 (Inferred),Net Label CONF_FLASH_A1,Port FPGA_CONFIG.CONF_ADDR1 (Inferred)) 17:49:14 2016/3/9 39
g, j+ d( e e" i5 B$ S[Warning] TOP.SchDoc Compiler Nets Element[1]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A1,Net Label CONF_FLASH_A1 (Inferred),Net Label CONF_FLASH_A1,Net Label CONF_FLASH_A1 (Inferred),Port FPGA_CONFIG.CONF_ADDR1 (Inferred),Port FPGA_CONFIG.CONF_ADDR1 (Inferred)) 17:49:14 2016/3/9 40( Y1 L/ d1 Z9 t1 s: R' r3 t$ O( Z
[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[1]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A1,Net Label CONF_FLASH_A1 (Inferred),Port FPGA_CONFIG.CONF_ADDR1 (Inferred)) 17:49:14 2016/3/9 41
0 \' d! A; T% C[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[1]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D1 (Inferred),Net Label CONF_FLASH_D1,Port FPGA_CONFIG.CONF_DATA1 (Inferred)) 17:49:14 2016/3/9 420 d1 _; v6 s8 n. V: [: q: T
[Warning] TOP.SchDoc Compiler Nets Element[1]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D1,Net Label CONF_FLASH_D1 (Inferred),Net Label CONF_FLASH_D1,Net Label CONF_FLASH_D1 (Inferred),Net Label CONF_FLASH_D1 (Inferred),Port FPGA_CONFIG.CONF_DATA1 (Inferred),Port FPGA_CONFIG.CONF_DATA1 (Inferred)) 17:49:14 2016/3/9 43% ]5 d* w: t; _9 w7 n1 F% P3 r; S
[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[1]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D1,Net Label CONF_FLASH_D1 (Inferred),Port FPGA_CONFIG.CONF_DATA1 (Inferred)) 17:49:14 2016/3/9 44! i4 S A, o! b5 Q+ S1 ^
[Warning] TOP.SchDoc Compiler Nets Element[1]: EN has multiple names (Net Label EN1,Net Label EN1,Net Label EN1 (Inferred),Net Label EN1 (Inferred),Port EN_A1) 17:49:14 2016/3/9 45
9 E: N- _9 Z K/ Q t/ M) d[Warning] TOP.SchDoc Compiler Nets Element[1]: L_IN has multiple names (Net Label L_IN1,Net Label L_IN1,Net Label L_IN1 (Inferred),Port L_IN_A1) 17:49:14 2016/3/9 46! l( l# ^, I, N& T% g# M: F+ ^+ Z
[Warning] TOP.SchDoc Compiler Nets Element[1]: POWER_OUT has multiple names (Net Label POWER_OUT1,Net Label POWER_OUT1,Net Label POWER_OUT1,Net Label POWER_OUT1 (Inferred),Port POWER_OUT_A1) 17:49:14 2016/3/9 47
$ y5 B( c6 I: E6 D# D[Warning] TOP.SchDoc Compiler Nets Element[1]: R1C has multiple names (Net Label R1C1,Net Label R1C1,Net Label R1C1 (Inferred),Port R1C_A1) 17:49:14 2016/3/9 48- n: h+ i1 G) c9 `
[Warning] TOP.SchDoc Compiler Nets Element[1]: R2C has multiple names (Net Label R2C1,Net Label R2C1,Net Label R2C1 (Inferred),Port R2C_A1) 17:49:14 2016/3/9 49
* E+ M. O. W. p9 j4 x0 ?- a1 V! H[Warning] TOP.SchDoc Compiler Nets Element[1]: RFB has multiple names (Net Label RFB1,Net Label RFB1,Net Label RFB1 (Inferred),Port RFB_A1) 17:49:14 2016/3/9 50+ _! n& K7 O$ ]' T- F1 k
[Warning] TOP.SchDoc Compiler Nets Element[1]: SS has multiple names (Net Label SS1,Net Label SS1,Net Label SS1 (Inferred),Net Label SS1 (Inferred),Port SS_A1) 17:49:14 2016/3/9 51
& t- c( t* @* \/ T7 J' L7 o[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[2]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A2 (Inferred),Net Label CONF_FLASH_A2,Port FPGA_CONFIG.CONF_ADDR2 (Inferred)) 17:49:14 2016/3/9 52
5 e7 h0 ~" [5 s9 s, D7 ~[Warning] TOP.SchDoc Compiler Nets Element[2]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A2,Net Label CONF_FLASH_A2 (Inferred),Net Label CONF_FLASH_A2,Net Label CONF_FLASH_A2 (Inferred),Port FPGA_CONFIG.CONF_ADDR2 (Inferred),Port FPGA_CONFIG.CONF_ADDR2 (Inferred)) 17:49:14 2016/3/9 538 d: _( S5 e. X g% S
[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[2]: CONF_FLASH_A has multiple names (Net Label CONF_FLASH_A2,Net Label CONF_FLASH_A2 (Inferred),Port FPGA_CONFIG.CONF_ADDR2 (Inferred)) 17:49:14 2016/3/9 54( c* M% i+ t( O! X8 b0 P0 N
[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[2]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D2 (Inferred),Net Label CONF_FLASH_D2,Port FPGA_CONFIG.CONF_DATA2 (Inferred)) 17:49:14 2016/3/9 55) H: {, a5 U5 k5 W% w- }+ s) e
[Warning] TOP.SchDoc Compiler Nets Element[2]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D2,Net Label CONF_FLASH_D2 (Inferred),Net Label CONF_FLASH_D2,Net Label CONF_FLASH_D2 (Inferred),Net Label CONF_FLASH_D2 (Inferred),Port FPGA_CONFIG.CONF_DATA2 (Inferred),Port FPGA_CONFIG.CONF_DATA2 (Inferred)) 17:49:14 2016/3/9 56
, X- n4 n1 J5 Q% t0 T9 S[Warning] FPGA_CONFIG.SchDoc Compiler Nets Element[2]: CONF_FLASH_D has multiple names (Net Label CONF_FLASH_D2,Net Label CONF_FLASH_D2 (Inferred),Port FPGA_CONFIG.CONF_DATA2 (Inferred)) 17:49:14 2016/3/9 57
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发表于 2016-3-9 17:54
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支持！
反对！
发表于 2016-3-13 15:47
楼主
晕死，好像是因为HARNESS 必须得成对应用。我刚开始画原理图的时候，只在sheet_adc中使用了一个，与它配对的那个没放，结果就出错了，后来都给匹配了就好了。altium 还是有一些不太好用的地方
。再比如说没有差分总线功能，不能单独修改花焊盘，多通道设计序号不能从0开始等等。希望能越来越完善。
