PCB Designer’s si guide

snowwolfe

PCB Designer's SI GUIDETable of Content
/ A9 _; P9 t$ Y( dBasics of SI___________________________________________________________________5
1.1 When Speed is important? _____________________________________________5
1.1.1 Acceptable Voltage and timing values ________________________________5
1.2 Signal Integrity ______________________________________________________5
% F9 W- V# ]+ x" r1.2.1 Waveform Voltage Accuracy _______________________________________5
1.2.2 Timing_________________________________________________________5
( K# D( ]7 v4 [( I3 E4 R+ q4 a, ]1.3 Speed of currently used logic families ____________________________________5
( d6 l- e, r) f; z( T7 X1.3.1 Transition Electrical Length (TEL) __________________________________6
+ [  x! a8 p$ r$ {# \! K& f! E1.3.2 Critical length ___________________________________________________6
+ F. G4 Q: \: I1.3.3 What is Transmission Line? ________________________________________6
1.3.4 What is moving in a Transmission line?_______________________________6
1.3.5 Power Plane Definition____________________________________________6
1.3.6 The concept of Ground ____________________________________________7
# ~& S* n$ |* @) n/ T+ X1.4 STRIPLINE circuit with Electromagnetic field _____________________________7
1.5 RLC Transmission Line Model _________________________________________8
( Q" O7 m6 N) q, q0 P1.5.1 What is Impedance? ______________________________________________8
1.5.2 A Practical impedance equation for microstrip _________________________8
1.5.3 What is relative dielectric constant Er? _______________________________9
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2 Interconnections for High Speed Digital Circuits _______________________________10

. o7 [# _8 N: d2 ?2.1.1 Summary______________________________________________________10
2.2 Examples of dynamic interfacing problems _______________________________10
2.3 IC Technology and Signal Integrity _____________________________________12
2.4 Speed and distance __________________________________________________14
& `: f1 v! ^% P, _2 ^; Y! `2.5 Digital signals: Static interfacing _______________________________________15
2.6 Digital signals: Dynamic interfacing ____________________________________16
1 I4 f1 S3 F; s9 |3 X+ `2.7 Review questions ___________________________________________________18
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3 Interconnection Models____________________________________________________20

. Z, K/ U( ~' t6 F  R: q3.1 Summary__________________________________________________________20
3.2 Reference model for interconnection analysis _____________________________20
3.3 Receiver model_____________________________________________________21
6 Q, ]) _0 j+ o2 p4 M% d3.4 RC interconnection model ____________________________________________23
, Z9 y0 E2 H( w  }3.5 Parameters of the interconnection ______________________________________25
6 v) L4 O$ N  V7 S# V# Y3.6 Refined models _____________________________________________________26
3.7 Review question ____________________________________________________28
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4 Transmission Line Models _________________________________________________31

, ?" B6 T8 {9 q2 O" r4.1 Summary__________________________________________________________31
4.2 Transmission line models _____________________________________________31
4.3 Loss-less transmission lines ___________________________________________32
4.4 Critical Length _____________________________________________________34
* a5 k9 n7 ~' A1 }2 W3 m) B4.5 Reference transmission line model______________________________________35
4.6 Line driving _______________________________________________________36
4.7 Propagation and reflected waves _______________________________________37
4.8 A sample system____________________________________________________39
4.9 Review questions ___________________________________________________42
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PCB Designer’s SI Guide Page 2 Venkata

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5 Analysis techniques _______________________________________________________45

5.1 Summary__________________________________________________________45
5.2 Transmission time and skew___________________________________________45
5.3 Effects of termination resistance _______________________________________46
5.4 Lattice diagram _____________________________________________________48
4 z$ [; c$ r: j5 S2 R+ A5.5 Examples of Real Lines ______________________________________________49
! g/ g, k( q3 K5.6 Simulation code ____________________________________________________51
5.7 Examples of results__________________________________________________54
5 P5 V& ~2 C7 v0 P' K5.8 Review questions ___________________________________________________55
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6 Design guide for interconnection ____________________________________________57

) l$ p; r* A; v, h9 d5 m6.1 Summary__________________________________________________________57
6.2 Incident wave switching ______________________________________________57
6.3 Effects of capacitive loading __________________________________________58
2 B6 `# J/ T; [6.4 Termination circuits _________________________________________________59
2 D& K7 `( z8 O5 x( b6.4.1 Passive termination______________________________________________60
6.4.2 Low power termination___________________________________________61
2 M; `- y9 p9 f( i1 w0 r6.4.3 Active low power termination circuit. _______________________________61
6.5 Driving point-to-point lines ___________________________________________62
# q+ h: s4 L/ w6 ^; j1 P6.6 Driving bused lines __________________________________________________64
6.7 Design guidelines ___________________________________________________67
6.8 Review questions ___________________________________________________67

snowwolfe

Signal Integrity in Digital Circuits ___________________________________________70
7 H; o) f) u2 o6 c* f6 o( X7.1 Crosstalk __________________________________________________________70
1 u/ C4 ?; \: r' F7.1.1 Summary______________________________________________________70
7.2 Examples of signal integrity problems ___________________________________70
7.3 Simplified Model for Crosstalk Analysis _________________________________71
7.4 Forward and backward crosstalk _______________________________________74
: s( l: a7 G. ~7.5 Examples__________________________________________________________76
8 s6 L0 R1 `; {& d6 ~7.6 Near-end and Far-end crosstalk ________________________________________80
7.7 Review questions ___________________________________________________81

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8 Design Guide to Handle Crosstalk ___________________________________________85

8.1 Summary__________________________________________________________85
( A4 l" J6 o) _0 |$ _/ i8.2 Effects of Crosstalk __________________________________________________85
+ T8 M4 A; I9 s, d! f4 K) q8 Y8.3 Passive countermeasures _____________________________________________86
8.4 Active Control of Crosstalk ___________________________________________92
8.5 Review questions ___________________________________________________94
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9 Ground Bounce and Switching Noise_________________________________________97

9.1 Summary__________________________________________________________97
9.2 The totem pole Current Spike__________________________________________97
9.3 Current flow in the output capacitance __________________________________100
9.4 Total Ground Bounce _______________________________________________100
9.5 Review questions __________________________________________________105
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10 Design Guide for Ground & Power Distribution _____________________________107

2 u3 e$ B( j) ^: E7 V10.1 Summary_________________________________________________________107
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PCB Designer’s SI Guide Page 3 Venkata

7 f8 e" E) u8 M; E' B  @10.2 Decoupling Capacitors ______________________________________________107
+ a& g6 v# ^9 C( C$ _# f10.3 Placement of bypass Capacitors _______________________________________113
* Y, A: ]' F% H, d! ?10.4 Ground and power distribution________________________________________114
2 ]6 S% H' u; [% Z. k4 P; P" I" v10.5 Clock distribution __________________________________________________115
: Z9 r- i/ j5 e10.6 Review Questions __________________________________________________118
2 W1 E7 K* o0 d3 \7 N' S" d11 Laboratory Experience _________________________________________________120
7 i1 n# Q% N7 i! ~11.1 Summary_________________________________________________________120
$ P* O7 }7 ]& M& H11.2 Aim of the experience_______________________________________________120
/ n4 P- Y4 k1 k: S7 l1 r* R- S6 u2 B11.3 Generator Parameters _______________________________________________122
. d) P6 l1 x# z3 ?11.4 Cable Parameters __________________________________________________123
. S5 V( }7 c+ {. r$ @11.5 Mismatch at driver and at termination __________________________________124
) C: M; i1 v+ N5 b: K# O; {11.6 Capacitive Load ___________________________________________________125
11.7 7. Time-domain reflectometer ________________________________________127
11.8 Driving the line with logic devices _____________________________________128
12 SI Analysis Strategy____________________________________________________133
0 E( ~  ~' }- ~6 @' x12.1.1 A modern high-speed design methodology must involve the at least the following: ____________________________________________________________133
12.2 POSSIBLE HIGH-SPEED DESIGN APPROACHES ______________________133
! ^2 F+ y8 _" a1 M12.2.1 There are two fundamental types of conditions that need to be considered for solution space analysis:__________________________________________________134
12.3 SOLUTION SPACE ANALYSIS _____________________________________135
  K- j! n( N  Q, u+ G2 M7 U12.3.1
STEP 1 — DEFINING THE INITIAL TOPOLOGY __________________135
5 Q) P; A! L. X) F! o" k12.3.2 STEP 2 — DEFINE MANUFACTURING TOLERANCES AND THEIR MIN/MAX VALUES ___________________________________________________135
12.3.3
$ I2 [5 T* w& `/ k. T  dSTEP 3 — DEFINE THE STARTING POINT FOR DESIGN VARIANCES 136
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STEP 4 — SET UP AND RUN A NUMBER OF SIMULATION CASES _136
: [7 d/ l& q8 n12.3.5 STEP 5 — EXAMINE THE SIMULATION RESULTS, IDENTIFY WHICH CASES FAILED AND WHY ____________________________________________136
  V3 ]/ M0 j0 p  y% x12.3.6 STEP 6 — ADAPT THE TOPOLOGY AND DESIGN RULES AS APPROPRIATE _______________________________________________________137
  l- O. O$ Y* T$ G  Y3 g5 T! {12.3.7 STEP 7 — REPEAT STEPS 4-6 UNTIL THE TOPOLOGY CONVERGES ON A SET OF VALUES THAT PASS FOR ALL CASES ANALYZED __________137
12.3.8
STEP 8 — DERIVE DESIGN RULES FOR THE TARGET CAD SYSTEM 137
1 T8 P9 H8 M3 j) ^12.3.9 STEP 9 — DRIVE THE CAD RULES INTO THE CAD DATABASE, AND USE THEM TO DRIVE THE PLACEMENT/ROUTING PROCESSES ___________138
8 q. F' f7 @/ L5 e% M8 ?! N8 U12.3.10 STEP 10 — POST LAYOUT SI ANALYSIS ______________________139
12.4 CONCLUSION____________________________________________________139
3 w- i& L7 I3 w& G" f7 P2 S$ W4 Q13 Glossary _____________________________________________________________141

PCB Designer’s SI Guide Page 4Venkata

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