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偶也跟一贴！
4 M" M% `! W2 k C) a4 f ~ \4 \以下内容来自《high speed digital system design》。: D) U4 _2 m e }& ^6 p9 O
2 j+ V$ L: G& I) tA via is a small hole drilled through a PCB that is used to make connections between various
9 c2 l3 V. u; dlayers of the PCB or to connect components to traces. It consists of the barrel, the pad, and
- N' K/ E7 X4 j9 A: athe antipad. The barrel is a conductive material that fills the hole to allow an electrical3 p! m `8 Z* ?5 @7 @
connection between layers, the pad is used to connect the barrel to the component or trace,1 p- o! K: e7 d5 ~
and the antipad is a clearance hole between the pad and the metal on a layer to which no! v* o, l. G) s/ q$ Z3 G; Y
connection is required. The most common type of via is called a through-hole via because it: T9 {- F) t8 n$ O$ I# U4 @
is made by drilling a hole through the board, filling it with solder, and making connections on1 s7 g& w/ [: y! Q2 W
appropriate layers via the pad. Other, less common types of vias, used primarily in multichip0 l! X9 N( t/ X0 h$ b& t8 M
modules (MCMs) and advanced PCBs, are blind, buried, and micro-vias. Figure 5.1 depicts2 @9 J1 I1 X- g$ X/ U w
a typical through-hole via and its equivalent circuit. Notice that the pads used to connect the
: {4 c, {5 T1 etraces on layers 1 and 2 make contact with the barrel and that there is no connection on
9 Q2 }2 y, n9 P8 Qlayer 3. Blind and buried vias have a slightly different construction. Since through-hole vias
1 E1 V& ?$ M) B- Oare by far the most common used in industry, they are the focus of this discussion.2 g R& F8 u- a7 p
3 b# I/ x% ?2 Q; u' W
Notice that the via model is simply a pi network. The capacitors represent the via pad
0 q! t. B# T6 y5 E; }: T- Kcapacitance on layers 1 and 2. The series inductance represents the barrel. Since the via
/ r H' _9 b, D2 Y1 E: Mstructures are so small, they can be modeled as lumped elements. This assumption, of7 Y/ L1 n3 I4 Z' U/ U: M
course, will break down when the delay of the via is larger than one-tenth of the edge rate.
$ W1 ?- {8 T4 l; v5 O4 mThe main effect that via capacitance has on a signal is that it will slow down the signal edge
8 B+ l8 c9 |) c& j% X7 [& _ [- Vrate, especially after several transitions. The amount that the signal edge rate will be slowed
- M% `! p% D* h# {can be estimated by examining the degradation of a signal transmitted through a capacitive" y3 l! I$ d& M$ y% c: d
load, as shown later in this chapter in equation (5.21). Furthermore, if several consecutive/ T/ H d2 v3 E
vias are placed in close proximity to one another, it will lower the effective characteristic
- l$ g* D( Z2 h4 b+ } i9 M$ F# Bimpedance, as explained in Section 5.3.3. The approximate value of the pad capacitance is) z3 [- W$ X4 d/ g y A7 a
[Johnson and Graham, 1993]
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[ 本帖最后由 killerljj 于 2007-11-21 20:51 编辑 ] |
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发表于 2007-9-11 14:20
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x6 a' b* ]1 L4 _
发表于 2007-9-15 15:34
俺也顶一下,因为焊盘描述的太形象啦!
发表于 2007-12-19 08:39