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偶也跟一贴！
p5 f1 B+ n6 N! \ k% Z以下内容来自《high speed digital system design》。
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A via is a small hole drilled through a PCB that is used to make connections between various
, l8 x4 f2 C! S# w: l' a& vlayers of the PCB or to connect components to traces. It consists of the barrel, the pad, and7 L, w2 f1 {6 ?( N( Y/ M: M! q% b
the antipad. The barrel is a conductive material that fills the hole to allow an electrical8 ?: C1 D+ X3 `/ V
connection between layers, the pad is used to connect the barrel to the component or trace,
$ c- H# A! r8 ^6 ]* wand the antipad is a clearance hole between the pad and the metal on a layer to which no" \2 Q S5 \& b1 Q6 f/ c$ J$ N
connection is required. The most common type of via is called a through-hole via because it6 I+ L. Z/ s8 }' c8 M8 [ h; Z
is made by drilling a hole through the board, filling it with solder, and making connections on: y( h# Q1 f4 b( ^, V& @, g
appropriate layers via the pad. Other, less common types of vias, used primarily in multichip
0 Z1 i7 B8 u" B" |1 Qmodules (MCMs) and advanced PCBs, are blind, buried, and micro-vias. Figure 5.1 depicts0 L+ v' k# ?: h) \$ D
a typical through-hole via and its equivalent circuit. Notice that the pads used to connect the
8 B9 ]' W- W% G7 x1 \- Otraces on layers 1 and 2 make contact with the barrel and that there is no connection on
- E* j7 Y! P( b- z* zlayer 3. Blind and buried vias have a slightly different construction. Since through-hole vias
, n% [4 t! ^& B7 z/ R0 g( j9 l' w. sare by far the most common used in industry, they are the focus of this discussion.
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; P, U5 L$ T5 M% {& d: u, ZNotice that the via model is simply a pi network. The capacitors represent the via pad% w( t1 F3 T) c6 y2 v
capacitance on layers 1 and 2. The series inductance represents the barrel. Since the via0 V) e6 z4 U. F+ k
structures are so small, they can be modeled as lumped elements. This assumption, of: @- c& l' X) e2 ?2 O& Z
course, will break down when the delay of the via is larger than one-tenth of the edge rate.$ c6 O6 x. ]& A% O- t) x
The main effect that via capacitance has on a signal is that it will slow down the signal edge
- t+ X7 W/ C8 v) b8 mrate, especially after several transitions. The amount that the signal edge rate will be slowed
) U) T7 h2 V; z2 bcan be estimated by examining the degradation of a signal transmitted through a capacitive/ ]* B; W) s5 H L
load, as shown later in this chapter in equation (5.21). Furthermore, if several consecutive2 t8 c- `: M; E7 C5 u* ?; o
vias are placed in close proximity to one another, it will lower the effective characteristic
6 V7 [1 l4 O" d& H2 c) wimpedance, as explained in Section 5.3.3. The approximate value of the pad capacitance is" k' P7 d( X; O# @6 c$ O
[Johnson and Graham, 1993]
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[ 本帖最后由 killerljj 于 2007-11-21 20:51 编辑 ] |
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发表于 2007-9-11 14:20
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8 L, D m8 |) K) I# P5 X6 w$ e
发表于 2007-9-15 15:34
俺也顶一下,因为焊盘描述的太形象啦!
发表于 2007-12-19 08:39