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补丁包更新列表！
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DATE: 11-20-2015 HOTFIX VERSION: 061) ?, s/ N6 P1 w$ v. O6 D
===================================================================================================================================
$ |! \5 |1 `' K6 J9 |CCRID PRODUCT PRODUCTLEVEL2 TITLE
% U$ }9 y9 `3 t! C% @, F7 k===================================================================================================================================
. Y5 F- ?& S* D. C1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value
' X, t, b9 t8 d# K8 F" c1342644 ADW COMPONENT_BROWSE Need directive or method for Component Browser to load a search criteria file upon init5 A+ G( r7 ?# O, Z
1413248 CONCEPT_HDL CORE Import from another TDO project makes the block read-only, G& g C c$ E8 g! T% H
1417429 ALLEGRO_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle4 V7 H( ~9 C% a$ h; t5 e4 _
1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins0 N) h1 g" e- J
1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set
/ i* |0 F2 ?: R3 [4 B: t/ G# a1453527 ALLEGRO_EDITOR EDIT_ETCH Contour route hugs the outer edge of the route keepin
( b* _( b' ] H4 T- H1 A1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools' I# H; G! R+ e, F7 k% S8 Q2 V
1467826 CONCEPT_HDL PDF PublishPDF from Console Window creates a long PDF filename" E& K" q5 G$ \
1478639 CAPTURE OTHER Capture Browse Nets window does not display all nets' D2 m2 z* Z8 ]3 M; L, ~
1479177 SIP_LAYOUT OTHER Pin pair constraints do not appear to be supported in Sip Layout XL
5 j+ W% i! y5 Z4 m: |: }1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy2 P2 ^/ @5 Q6 a8 q* m
1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable
$ j' E; h( @+ @- H0 q) r1480293 CAPTURE PROJECT_MANAGER Capture hangs when searching for all nets
. L3 L7 y ^! X3 Y- m1483894 CONCEPT_HDL CORE Import Design hangs when pull-down arrow is clicked twice/ T8 ?" B: D! [0 g: O; e& ?) }' q
1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues6 s; X7 F# e" t
1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only
* J; D5 q, S' ]. x1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project# P% m2 U6 T* f7 u0 E: G6 q
1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork.: E. ~) s) e1 s7 o- t; ?3 G
1486834 CONSTRAINT_MGR OTHER Restore the Status column in cmDiffUtility8 O+ i4 d, N! k
1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems
: o0 f* E% C J Q! m ]1487197 ALLEGRO_EDITOR DRC_CONSTR Drill to Via DRCs are not being reported
3 N0 v& F7 l( `9 N+ E. j1 B0 C$ e1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior
) n: E/ b7 `) K* s* }5 _ L1487733 CONSTRAINT_MGR OTHER Running Export Physical - It takes over two hours to update the PCB Editor board3 Q0 s- u* g4 m7 s9 ]
1488758 CONCEPT_HDL CONSTRAINT_MGR CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager
7 `/ q3 J$ l- A6 @# e c2 U1490299 SCM OTHER ASA does not update revision properly/ m6 ]" } n1 u" M8 g, G
1490744 ALLEGRO_EDITOR SKILL axlChangeLine2Cline changes line to cline and places it on the TOP layer
6 ?( R4 F N! a0 g( u8 k$ x ~1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints: }, M* y7 D5 l/ K- h( ?6 C
1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working
9 X0 H N+ L5 S% |, F1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong' f+ G* W$ }' c8 g
1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO import of customer mcm results in crash
2 K2 R+ R8 X. s" [1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL* C0 k% n- d0 ~ D+ J
1495621 ALLEGRO_EDITOR INTERFACES Oval pins are placed with wrong orientation in IPC2581* r- L/ f8 b Z1 z% w
1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size
) J) ^& |' c& `; J1 J9 @1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root
% b9 r5 X" _6 o$ Q% ]' O1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file3 l3 C- x& @# v, Y$ f
1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60. w7 J) Y; z. ~& Q; w6 ]
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最新破解包列表！
- r+ B# B8 d! n- o9 M6 m& g1 O+ T------------------------------------------------------------------------------
9 l# y3 J$ Z; l6 I5 tSPB 16.6 UPDATED KITS RELEASE: ISR 16.60.061 EST.DATE: 11-20-2015
/ ?, b2 G7 m6 {- o' ?: y6 w------------------------------------------------------------------------------
9 x8 {& E8 F: p4 \, ^& W0 NCompBrowser16.60-s037wint
1 \$ p/ t6 x: H, v, ^DSCoreUtils16.60-s077wint8 R1 z Y; D& z3 c" b& c- S
DSCore16.60-s055wint6 ^1 Q% k7 G6 F+ D1 |1 W
DSSchgen16.60-s030wint/ r; O& u) _* b9 l* a
DSSetup16.60-s010wint
2 M9 z2 H, G) D: M1 nDSTableEditor16.60-s018wint
- t2 M9 M2 @! X/ ]6 t( ODSTextEditor16.60-s015wint1 h; {% ?) }. ?% z( _
DSUICommonIndep16.60-s019) `9 ~2 V0 E" ^" h# N
DSUICommon16.60-s026wint k" a8 j5 ^1 G: M) }
DSUIUtils16.60-s037wint
# e! G7 q8 t: E1 ISPBIX06116.60-p002wint4 s# l8 M+ m5 n0 ?
adpPDFLibs16.60-s033wint+ h$ b- a' P: x9 `
advanPakgDsnr16.60-s129wint8 G' D$ _0 ?$ G& F9 V) ]
adwLRM16.60-s033wint% [. c' b0 Y% h2 ?! h: ?
adwSDM16.60-s044wint
) n1 j* J0 B0 j6 m) Z; ^9 D" YalgroAcad16.60-s122wint! [2 R# _2 ~& B4 } M8 R
algroArtwork16.60-s122wint$ L) R4 W" R2 H k! b: ?% Z
algroAxl16.60-s0485 D6 X4 u& @" n
algroBase16.60-s129wint
+ I3 o" L% P+ ?+ {; L" X5 p# jalgroCxt16.60-s077' v: M7 `: w# [, @( P
algroDBTools16.60-s124wint% e4 s* J6 T% k0 D0 u
algroDsign16.60-s122wint L _: R2 w& _
algroF2B16.60-s122wint$ s% P2 m3 \5 r8 w
algroIDF16.60-s122wint/ u- c) L5 M4 u* j& E. C6 M+ v
algroIgin16.60-s122wint( h) o- r# L7 P- [4 h5 Z$ p
algroIgout16.60-s122wint
6 T! D# s+ V. [7 V" H* malgroIpc16.60-s122wint
4 h8 T- _" K0 F: }$ }algroMfg16.60-s122wint
1 P- E/ @/ B0 c% _3 \5 BalgroNetin16.60-s122wint2 S0 x: L, d4 P! A
algroPlace16.60-s122wint
1 _( ]. {$ Y% f) O& ^3 palgroSgnse16.60-s122wint7 n9 C6 Y0 v F3 \8 g# l
algroSpif16.60-s122wint
B4 A* v2 n0 K5 L) aalgroStrm16.60-s122wint
; u$ E/ p$ z0 D( balgroTextIndep16.60-s0897 [% y2 Z9 K; N# O
algroTransltr16.60-s121wint$ z# O5 V& U' _5 H+ K5 Z
algroUtlty16.60-s122wint
- f7 D+ N/ g# ybom16.60-s030wint
$ w1 Z e6 \$ F( X+ ocapPSpLibMAB16.60-s018wint
8 c2 x/ g- P9 b( G, E5 gcapProg16.60-s044wint
* m' Q) e7 M, F! l4 \8 G$ I9 G* Ocheckplus_exp16.60-s023wint+ Q% L8 F1 O' X4 x
conceptNT16.60-s106wint* X/ D. L6 R0 k' Q* E
concptSetup16.60-s015wint
% D/ |5 y7 s$ l( e5 g; j: c5 QconsMgr16.60-s104wint' n/ H: K' w! d" A; ^& w; |1 i" o
desSync16.60-s019wint) l* \6 X5 j8 n; q
eCWCore16.60-s009wint$ @4 K( T4 M0 [( W; j' H( [. W
fetBase16.60-s034wint+ g$ e+ l' w* q" e- W6 C" |" }
icpCommon16.60-s122wint5 v3 x' g# o( f4 K4 j7 W
iff2hdl16.60-s010wint: d6 X, h! L0 G1 E/ r1 ?: J; V. ]
lmancore16.60-s036wint( m/ R! }. C, ]4 e2 x0 I
lmanext16.60-s012wint: Q# a3 N; L- c5 ?. ~6 d
lman16.60-s023wint% E3 g! P% T! u; A3 a4 B
productServer16.60-s084wint
0 U$ [( q9 @, wprojMgr16.60-s015wint
" A1 A# e5 `1 |2 c0 }- ~pspProg16.60-s043wint
( O" t) @% k% D1 p u6 Jrfpcbfe16.60-s026wint4 l: _ I& P* D! }( F
rfsipPcellIndep16.60-s005
) e4 a9 Z2 [$ M, K ^. ^sipDsnr16.60-s128wint N. X7 C, s0 F1 k) l! k
spbFpgaPlanner16.60-s065wint4 N& i6 I! e6 s+ m9 v0 ?! ?/ S
specctraQuest16.60-s122wint
: _; u- |2 c% Z. UspgSignal16.60-s123wint
' ?0 ^* m' \& K/ t% H3 Y7 p' Avedit16.60-s043wint6 i) C2 j, z! y$ @8 F! K0 v
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补丁包种子！
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cadence.spb.orcad.16.60.061.hotfix.rar
(17.88 KB, 下载次数: 1047)
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发表于 2015-12-3 09:33
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