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Cadence SPB OrCAD 16 最新的升级补丁，版本号16.50.46，修正内容如下：
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CCRID PRODUCT PRODUCTLEVEL2 TITLE9 t; c) r$ p6 c/ S% O
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8 ^( Q# H3 R, n; }# X: U `' W: i2 }9 X1079538 F2B PACKAGERXL Ability to block all їsingle noded netsї to the board while packaging.
- o( }' f$ e# o( v$ F1123150 CONCEPT_HDL CORE property on y axis in symbol view was moved by visibility change to None.
- J6 t+ v5 v4 r6 y9 l. U4 `1144990 PCB_LIBRARIAN CORE PDV expand & collapse vector pins resizes symbol outline to maximum height
6 }0 O4 g3 W0 |/ l& {% z; a1149987 PCB_LIBRARIAN PTF_EDITOR Save As pushing the part name suffix into vendor_part_number value- [% F2 ~) |4 g* k
1152755 CONCEPT_HDL COPY_PROJECT Copy project hangs if library or design name has an underscore
! ?5 v; K& |' p O8 ]1153857 CONCEPT_HDL CORE Changing different power symbol should maintain the schematic level properties.5 v, } O6 Y7 @. _& h' G
1155569 APD MODULES P1_U1 and P1_U3 Die pins are missing after Place Module.
* T3 z) a- }. W! d7 a8 K- o1155728 CONCEPT_HDL CORE Unable to uprev packaged 16.3 design in 16.5 due to memory
1 W; w3 q+ _) W, k1156547 ALLEGRO_EDITOR DRC_CONSTR Etch Turn under SMD pin rule check through pin Etch makes confused.
( l% }" E1 q- Q/ X* O6 E/ ]1158042 ALLEGRO_EDITOR DFA DFA_DLG writes the dra file name in uppercase.2 E6 h# N( Z- n4 E
1158528 CONCEPT_HDL OTHER Dual Monitor issue: Retain Hard Packaging option is missing and attribute test distorted
- ^* K) W) o: p @' k! q- v$ y1158718 CONCEPT_HDL CHECKPLUS Customer could not get $PN property values on logical rule of CheckPlus16.6.. |" K% i: p& G4 p8 F$ S+ v3 J
1159516 ALLEGRO_EDITOR EDIT_ETCH Unable to slide cline segment with new slide.
4 X/ F! h; }& ^1 a' m. A: {8 U( E8 N1160004 SCM UI The RMB->Paste does not insert signal names.
. K7 \4 R) P! ^2 p) Y1161538 CONCEPT_HDL CORE Espice model value edited in DE HDL & then netlisting done, but it doesnt changes the earlier assigned model in Allegro
; r! g0 G7 F. t/ F% Z8 l1162383 CONCEPT_HDL CHECKPLUS Checkplus not using $CDS_SITE/custom_help and $CDS_SITE/custom_rules_include directories.
+ D( Z. X- t# w( A1162686 CONCEPT_HDL CORE Changing NET_SPACING_TYPE to display both shows up with $NET_SPACING_TYPE _5 ~7 ~/ N; a8 t) U9 c+ \" l
1165469 CONCEPT_HDL CORE Import Design loses design library name
' n/ J( Q6 P6 V1165801 CONCEPT_HDL PDF Pin texts of spun symbol overlap in publish PDF.
1 }$ k- `8 C4 S5 v, w; E1165836 SIG_INTEGRITY GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.(update)
) q" k8 A; c. O$ J1166819 CONCEPT_HDL CORE Cadence DEHDL Text Size Issue
" Y* \) S9 v: r1167519 ALLEGRO_EDITOR DATABASE Uprev dbdoctor does not log warnings about renaming properties.( y2 }1 ?3 |& l8 K
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Cadence SPB OrCAD 16.50.46 Hotfix/ E$ J: h p$ ]2 w* h% r6 d$ {
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Download uploaded, d8 S( D0 _& Z0 g2 i* p) T: y
http://uploaded.net/file/9yjz448a/cpborc165046ho.rar
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Download 城通网盘
& Q7 S1 T- A' ~/ V7 O9 ^1 qhttp://www.400gb.com/file/28712279
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发表于 2013-8-28 21:42
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