我用cadence16.5 ConceptHDL设计原理图,完成后道pCB,我使用的Top-down式原理图设计方式1 u0 g$ ], n4 ?' L# J, ]
导PCB时提示“Connectitivity server is unable to load design. The .xcon file might be missing or incorrect. Your design needs to be netlisted in 16.4 or later version of Design Entry HDL"% A& u0 e7 B5 i, [3 ~
! m+ O! f. N8 p# m# j* L* q这个是由什么问题导致的?3 u% D" `# q+ |1 A1 a6 D8 k