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EE TO PADS 转换问题

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发表于 2013-1-8 14:01 | 只看该作者 |只看大图 回帖奖励 |倒序浏览 |阅读模式

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我先是 AD的PCB  转换成 PADS 再转换成EE文件,在EE中将线画好。
# G' r2 F, G2 S0 C( t5 I. o然后用PADS,再导入EE画好的PCB,转换是成功,有提示转换问题,只有元件不见了,其它的还有。怎么解决!!!
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* k! s1 `6 U& }2 `( k转换提示内容如下! B# \6 m# m- q3 I+ b" F4 \
Expedition to PADS Layout Design and Libraries Translator (Version 9.5) 01/08/13 13:54:535 b& i6 H; n, N5 E7 C" N5 @
Copyright (c) 2012 Mentor Graphics Corp. - All rights reserved2 |1 b2 U( ]$ w
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------------------------------------------------------------: i8 z1 ~( @$ H2 U/ U
Input folder: D:\1\EE\PCB\EE.pcb
% c/ }  ^( J2 s! t6 ]" V8 a6 jOutput folder: EE_pads_5.pcb . D8 S$ q5 j/ y6 K! O8 s3 g

% k( ^: u0 o' G; j/ y% s[I] Preparing data...( Z, l9 U+ i) J3 {
Output file: EE_pads_5.pcb 8 x; q, K2 m- T, A4 d9 k+ r7 v
[I] Loading...
" i0 U9 }( s7 g4 k  p  p[I] Translating Expedition design files from 'C:\Users\ADMINI~1\AppData\Local\Temp\' to PADS Layout design file  J6 j* Z: S2 n  s! h  R! k# y
[I] Reading Pad Stacks...
: C( ~2 \1 ]( r* Z6 i. ~[I] Reading Cells...3 r0 p2 u: X, r5 T: B: N
[I] Reading Part Numbers...+ a0 q  w% @& V
[I] Reading Job Prefernces...# E3 \; S* \. }6 i8 p
[I] Reading Net Classes...
9 l$ i+ `: H8 ?/ f8 ~% w[I] Reading Net Properties...
. x6 l1 x2 B. u2 k; y* ~) a[I] Reading Layout...
" {1 E. I/ h- W5 a$ y- j$ W. _[I] Translating data...* J& R: m9 M0 Q! ^. F6 a/ H
[W] All coincident Pad Entry rules are translated to Default Rules level
4 P" t7 o" q" a1 ?1 P* B[W] Discriminate Pad Entry rules found, and the rules were not translated.
/ H' U% \+ G6 V& G6 D$ j, \[W] Route grid is not set. Primary part grid is used for setting design grid.
  v7 ?: z* K# h0 f6 O1 z0 L4 Q; h/ U[W] Part type 'RES' is not found, and the component 'R6' was not translated.
: `! j% @5 D) ^( y[W] Part type 'RES' is not found, and the component 'R9' was not translated.0 `$ \) L$ M; c
[W] Part type 'RES' is not found, and the component 'R10' was not translated.& k9 b: R2 \& a1 y9 y- y
[W] Part type 'RES' is not found, and the component 'R5' was not translated.& P! Z" O" d2 d4 z! ]
[W] Part type 'RES' is not found, and the component 'R8' was not translated.
$ E8 F' [1 T" E; w. g9 x[W] Part type 'RES' is not found, and the component 'R7' was not translated.
. T  g( a1 {8 o) m! S[W] Part type 'RES' is not found, and the component 'R4' was not translated.
; ^+ N  w) M- D2 s4 }% g0 e[W] Part type 'RES' is not found, and the component 'R3' was not translated.
  K  F, Q& M* @9 n4 P2 q: D4 T, z3 n[W] Part type 'RES' is not found, and the component 'R2' was not translated.
6 G& c* s! Y# [( y2 p3 b[W] Part type 'RES' is not found, and the component 'R1' was not translated.
4 n4 a5 Y) `) p  j! a1 `' Z6 S[W] Route outlines are not supported, and was not translated.
+ x; G. {9 g# ^3 I[W] Pin name 'R7-1' has wrong format. The pin was not included into the net 'GND'.
% z: i, N0 i6 X" ?[W] Pin name 'R6-1' has wrong format. The pin was not included into the net 'GND'.* Z0 a' c( `$ p* b, t( o- S
[W] Pin name 'R8-1' has wrong format. The pin was not included into the net 'GND'.) H1 T- _* O) _
[W] Pin name 'R9-1' has wrong format. The pin was not included into the net 'GND'.8 d+ e1 E0 S+ i- B" L% w2 M  E
[W] Pin name 'R10-1' has wrong format. The pin was not included into the net 'GND'.. P' i2 Y4 o9 J0 T) _
[W] Net 'GND' don't have properly pin pair. Vias of the net were not translated and traces were translated to open coppers.
  Y9 G) c& _, `0 K$ C; {# a[W] Pin name 'R1-1' has wrong format. The pin was not included into the net 'NETR1_1'.
# }" g0 N2 \6 p- T/ g- l[W] Pin name 'R6-2' has wrong format. The pin was not included into the net 'NETR1_1'.
- ~5 {( g" Z- u/ f; E+ ~, k$ g[W] Net 'NETR1_1' don't have properly pin pair. Vias of the net were not translated and traces were translated to open coppers.! S/ g6 P8 W( o/ \  O
[W] Pin name 'R2-1' has wrong format. The pin was not included into the net 'NETR2_1'.
7 L* ~* h2 v0 @# b[W] Pin name 'R7-2' has wrong format. The pin was not included into the net 'NETR2_1'.
% k: f; b$ F8 d  F- G[W] Net 'NETR2_1' don't have properly pin pair. Vias of the net were not translated and traces were translated to open coppers.
/ h9 h1 Z5 c5 r: d[W] Pin name 'R3-1' has wrong format. The pin was not included into the net 'NETR3_1'.
) k3 `8 Y0 }" t) b4 k9 }[W] Pin name 'R8-2' has wrong format. The pin was not included into the net 'NETR3_1'.
. a# a# ]# @2 P2 @  J[W] Net 'NETR3_1' don't have properly pin pair. Vias of the net were not translated and traces were translated to open coppers.6 R! Z/ r1 K7 e$ Y% Y
[W] Pin name 'R4-1' has wrong format. The pin was not included into the net 'NETR4_1'.
, F' `% u# N6 {/ z' P6 G, P6 N[W] Pin name 'R9-2' has wrong format. The pin was not included into the net 'NETR4_1'.6 J6 u( b# V+ r; `: L* A
[W] Net 'NETR4_1' don't have properly pin pair. Vias of the net were not translated and traces were translated to open coppers.* j. M' R; v% U1 _9 n0 J
[W] Pin name 'R5-1' has wrong format. The pin was not included into the net 'NETR5_1'.
  d4 l: j) Z, a8 K- K[W] Pin name 'R10-2' has wrong format. The pin was not included into the net 'NETR5_1'.
6 a% e; b) {8 ?3 P[W] Net 'NETR5_1' don't have properly pin pair. Vias of the net were not translated and traces were translated to open coppers.: \3 \4 q3 L5 T: n+ u! [
[W] Pin name 'R2-2' has wrong format. The pin was not included into the net 'VCC'.
$ W1 {* u" S  Y; k# @) c2 a[W] Pin name 'R1-2' has wrong format. The pin was not included into the net 'VCC'.
: r% p# H" b* ^4 k. ][W] Pin name 'R3-2' has wrong format. The pin was not included into the net 'VCC'.
+ G* y* Y( C' n$ M% J8 z' {' k( J[W] Pin name 'R4-2' has wrong format. The pin was not included into the net 'VCC'.
0 C* j: r4 D# T' Z0 w[W] Pin name 'R5-2' has wrong format. The pin was not included into the net 'VCC'.
, ^# u/ @! R$ p$ Z; {[W] Net 'VCC' don't have properly pin pair. Vias of the net were not translated and traces were translated to open coppers.
! l. X% u8 P3 A  m* P$ i& F4 ][I] Completed& l+ P) \4 L4 A4 L5 z- }
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2#
发表于 2013-1-8 15:48 | 只看该作者
为什么要转,你不是两个工具都会用么

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 楼主| 发表于 2013-1-8 17:17 | 只看该作者
本帖最后由 xiesonny 于 2013-1-8 17:58 编辑 ' Q& w8 n8 {& ~8 K
dali618 发表于 2013-1-8 15:48 ) c  O( O% q3 z0 x; @, [* [
为什么要转,你不是两个工具都会用么
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: R& I% e! m. c9 R! D有些工程,比如AD的,或者PADS的,工程可能已经做了一部分,或者修改比较多,想转入EE中再重新布线。完成后,再转回PADS或者AD中,为一个完整的工程。

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4#
发表于 2013-1-9 12:29 | 只看该作者
我在转换时遇到icdb出错 请问楼主是怎么设置的?、
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5#
发表于 2013-1-9 16:21 | 只看该作者
把CES关闭再转试一试。
你让偶滚,偶滚了,你再让偶回来,对不起,滚远了!

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 楼主| 发表于 2013-1-9 19:36 | 只看该作者
TOTO 发表于 2013-1-9 16:21
7 i* Y; B! {# E) g) [' G/ x/ C$ A1 H) H把CES关闭再转试一试。
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呵呵,如果EE不能转PADS,比如导入错误,那么关闭CES后,的确就可以导入了。这个方法我知道。/ O$ L6 _4 j; R1 V4 Q5 J% N
我想知道的是,PADS转EE的文件,如果开启CES后,是不能导入的,但关闭后,虽然能导入,但就如我所问的问题一样,没有元件封装的。其它的可以转换

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发表于 2013-1-10 08:46 | 只看该作者
xiesonny 发表于 2013-1-9 19:36 ! ]) K" ?4 }! d! c
呵呵,如果EE不能转PADS,比如导入错误,那么关闭CES后,的确就可以导入了。这个方法我知道。
& W9 p, Y) V4 Z我想知道的 ...
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软件之间的转换不可能十分完美,由于没有看到实际情况,不太清楚造成所述问题的原因所在,但目前的解决方法可以保留转换后工程的线,铜皮孔等需要的信息,拷贝到没有问题的PADS工程上.由于本人能力有限,不知道这样的方法是否可以帮助您解决问题
你让偶滚,偶滚了,你再让偶回来,对不起,滚远了!

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8#
 楼主| 发表于 2013-1-10 14:17 | 只看该作者
TOTO 发表于 2013-1-10 08:46
1 ^' D/ a0 Q8 }& B8 j软件之间的转换不可能十分完美,由于没有看到实际情况,不太清楚造成所述问题的原因所在,但目前的解决方 ...
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呵呵,这样的解决方案貌似不好。7 s/ }+ z& v! x+ z
我说一下具体过程吧。
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1,不管用什么软件生成网络表,或者用原生的DX, 然后在EE中做的PCB工程。基本可以完美导入PADS中。9 a- Y  I$ h0 j  \- k
2,如果你是AD转PADS转EE,或者PADS转EE,你再想从EE转回PADS,问题就来了,如果打开了CES,要关闭CES才能导入PADS,虽然能导入了,但是,元件却不见了,就像我顶楼所贴的提示内容差不多。
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我想解决的是2过程。
6 ?3 ^; b, a  P3 |$ q5 s! T4 i因为有些工程可能原来是AD的,或者PADS,这样可以在EE中布局布线,完成后,再导回PADS,这样就是一个完整的工程。

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9#
发表于 2013-3-3 22:20 | 只看该作者
请问下,EE怎么转PADS?
4 f5 S7 S. @( @! }) p4 g谢谢!

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发表于 2013-11-12 16:01 | 只看该作者
规则都导进去了吗?

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11#
发表于 2014-12-9 16:01 | 只看该作者
CES没打开,在PADS里面import出现iCDB无法打开的错误
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