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我在做数模混合仿真的时候,在config中调用模拟电路和数字模块的symble,但是在进行display partition>all active时,系统报错:+ s, e* b6 G8 z) T6 J) \3 S B. N
\o *SYSERR: Unable to hdbBind for inst I15 in cell Module tiadc, lib design, view schematic, configViewString spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl.
- v8 d# N- P) N, _9 H% {, X$ u\o *USRERR: Selected context view string 'spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl'4 ~- Y8 T' L' ^ a" B5 {2 |
\o offers no suitable view for inst I15 referencing placed master design.add_and_mult.symbol. ~$ Z- P. x( @' M
\o in cell Module tiadc, lib design, view schematic, configViewString spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl.. P6 S4 W' I7 p: D
\o Please check HDB configuration or library setup.# P; V' J" L4 b; J
\o *USRERR: Selected context view string 'functional'
) r6 g9 ]) h- \7 t" B\o offers no suitable view for inst I14 referencing placed master design.average.symbol- F) P7 H3 ~ o* f( Z1 r/ B
\o in cell Module tiadc, lib design, view schematic, configViewString spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl.3 e) J/ j! J% p# T5 t
\o Please check HDB configuration or library setup.9 X9 K7 F9 R9 ^' ]
\o *USRERR: Selected context view string 'functional': O1 b3 E$ ]; b f2 c
\o offers no suitable view for inst I12 referencing placed master design.unit2.symbol
/ V2 Y, d7 e7 {& h D, u\o in cell Module tiadc, lib design, view schematic, configViewString spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl.
; G2 j5 B& v) I2 D0 ]9 T8 w\o Please check HDB configuration or library setup.
6 P% E) V7 }9 @' Q' r" l5 B\o *USRERR: Selected context view string 'functional'
* q" S. c$ W# w$ y3 z( y\o offers no suitable view for inst I11 referencing placed master design.unit1.symbol
' q& ?: e: Q* s4 v$ }\o in cell Module tiadc, lib design, view schematic, configViewString spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl.% e, K% W+ v. D, N( K- b
\o Please check HDB configuration or library setup.6 f9 V0 U N) p
\o *USRERR: Selected context view string 'functional'1 U/ Q# F: O7 g) W9 e$ ^) Q. C# C
\o offers no suitable view for inst I4 referencing placed master design.encode.symbol
. l$ L- T- k/ h7 g% W\o in cell Module tiadc, lib design, view schematic, configViewString spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl.
( C! H! M# e. R% j5 ?( c) p\o Please check HDB configuration or library setup.
2 t9 I [4 S `% y6 v\o *USRERR: Selected context view string 'functional') }# M7 g6 ?- u. p T3 n0 t2 U
\o offers no suitable view for inst I2 referencing placed master design.encode.symbol3 B. u5 q: I8 Y" M& G$ R. \6 ~# g
\o in cell Module tiadc, lib design, view schematic, configViewString spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl.. a; j; h- |+ T2 o
\o Please check HDB configuration or library setup.1 \% l! E* w6 ]* i" s! t
\e *Error* Failed to partition the design.
& ]0 r& f9 L& E1 R\e ) [. `) g c8 _/ z! f& \( a
\e *Error* mspDisplayPartition: Failed to create network
" w4 A0 E! }$ E! k @9 k" l) o, C* `8 x. e; }6 G
这是什么问题啊?求大神帮忙解决一下,鄙人不甚感激!!!
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