Hotfix_SPB16.60.013_wint_1of1

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Cadence SPB16.6下载(Hotfix013已发布)
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Cadence SPB16.6已经推出，需要的朋友可以点击下面的链接下载：
$ l, B. e0 x5 u; b6 V7 o( [# c' Vhttp://dl.vmall.com/c0ych9k8m3
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DATE: 07-26-2013  HOTFIX VERSION: 013
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CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
, C' H' _5 S4 r8 R# t) K===================================================================================================================================
$ B- x8 m* }' G9 ^' ?! d111368 CAPTURE        CORRUPT_DESIGN   Capture - will not produce allegro netlistwith 10.0
% Y0 C- Z) S2 b0 b- u134439 PD-COMPILE     USERDATA         caCell terminals should be top-levelterminals
0 K  F* b8 L" ?1 ~+ N. V! M186074  CIS            EXPLORER         refresh symbols from lib requires youto close CIS
583221 CAPTURE        SCHEMATIC_EDITOROption to have the Schematic Page Name as a Property in the Titleblock
: ~# x; s' R9 s  T591140 CONCEPT_HDL    OTHER            Scale overall output size inPublishPDF from command line
- T& h2 W% R+ x( z, |' V  F, ]801901 CONCEPT_HDL    CORE             Concept Menus use the same key"R" for the Wire and RF-PCB menus
813614  APD            DRC_CONSTRAINTS  With Fillets present the "cline toshape" spacing is wrong.
1 k" ]2 R2 W9 F) G9 b. q881796 ALLEGRO_EDITOR GRAPHICS        Enhancement request for Panning with Middle Mouse Button
4 n0 t& ~, H' p# z* u887191 CONCEPT_HDL    CORE             Cannot add/edit the locked property
911292 CONCEPT_HDL    CORE             Property command on editing symbolattaches property to ORIGIN immediately
987766  APD            SHAPE            Void all command gets result as novoids being generated on specific env.
& G) h( t7 @, c! f2 t# _6 e! d1001395 SIP_LAYOUT    ASSY_RULE_CHECK  Shape Minimumvoid check reports lots of DRCs which are not necessary to check out.
1030696 ALLEGRO_EDITOR INTERACTIV       Enh - Allow another behavior of PANmovement using middle mouse in Allegro
: b7 F- U7 V! O1043856 ADW           TDA              Diff between TDOand DE-HDL Hierarchy Viewer is confusing to the user
1046440 ADW           PCBCACHE         ADW: ImportSheetis not caching libraries under flatlib/model_sym when the source design is notan ADW project
1077552 F2B           PACKAGERXL       Diff Pairs get removed when packing withbackannotation turned on
1079538 F2B           PACKAGERXL       Ability to blockall 縮ingle noded nets� to the board while packaging.
7 o* c- j! E: R7 t1086362 ALLEGRO_EDITOR SHAPE            Enhancement request to autovoid a viaif shape cannot cover the center of the via.
1087958 PSPICE        MODELEDITOR      Is there anylimitation for pin name definition?
1087967 CIS           UPDATE_PART_STAT Update part status window shows incorrect differences
1090693 ADW           LRM              LRMauto_load_instances does not gray out Load instances Button
. M! ?( Z, M$ f6 F. V% |+ c# g; `: a1 Q. d1097246 CONCEPT_HDL   CORE             ConceptHDL -assign hotkeys to alpha-numerical keys
1099773 CONCEPT_HDL   CORE             DE HDL goes intorecursive loop if a custom text locked at site level is deleted from Tools >Option
1100945 SCM           SCHGEN           SCM generatedDE-HDL has $PN placement issue
1100951 PSPICE        SIMULATOR        Increasing theresolution of fourier transform results in out file
1103117 RF_PCB        FE_IFF_IMPORT    Enh- Allow theAllegro_Discrete_Library_to_ADS_Library_Translator to output in its originalunit
1105473 PSPICE        PROBE            Getting errormessages while running bias point analysis.
1106116 FLOWS         PROJMGR          view_pcb settingchange was cleared by switching Flows in projmgr.
4 m+ b: |) e4 M0 w7 j# |1106298 ALLEGRO_EDITOR INTERACTIV       Copy Shape uses last menu pick locationas origin and not the Symbol Origin as specified in Options.
1106626 CONCEPT_HDL   CORE             Concept HDL crashes when saving pages
1107086 ALLEGRO_EDITOR INTERACTIV       manual void with arc's goes in wrongdirection during arc creation
1107172 CONCEPT_HDL   OTHER            Project ManagerPackager does not report errors on missing symbol
) y. {8 v, J3 @- r% A1108193 CONCEPT_HDL   CORE             Using theleft/right keys do not move the cursor within the text you're editing
1108603 PCB_LIBRARIAN VERIFICATION     PDV ToolsVerification > View Verification (CheckPlus) leaves<project>.cpm_tmp.cpm
! [3 G% q9 M1 B/ S1109024 CIS            OTHER            OrCad performance issue from Asus.
1109109 CAPTURE       NETLIST_ALLEGRO  B1: Netlistmissing pins when Pack_short property pins connected
1109466 ALLEGRO_EDITOR ARTWORK          Artwork create some strange gerberlines for fillet.
1109647 SIP_LAYOUT    DEGASSING        Shape degassingcommand enhancement - control over what layers are counted in even/odd layersets.
1109926 CONCEPT_HDL   CORE             viewing a designdisables console window
1110194 SIP_LAYOUT    WIREBOND         If OpenGL settings for display ofdynamic net names is enabled, should be visible while push/shove wirebonds.
1112357 SIP_LAYOUT    WIREBOND         wirebond commandcrashes the application
7 s7 X' ~! |( S; `1 k2 c( n* g+ c1112395 CONCEPT_HDL   CORE             縗BASE\G� for global signal is not obeyedafter upreving the design to 1650.
1112658 CAPTURE       PROPERTY_EDITOR  Changing Part 縂raphic� value from property EditorChanges Occ refdes values to instance
1112662 CAPTURE       PROJECT_MANAGER  Capture crashesafter moving the library file and then doing Edit> Cut
1113177 PCB_LIBRARIAN CORE             Pin Shapes arenot getting imported properly
1113380 ALLEGRO_EDITOR INTERACTIV       Change layer to - option for packagetype .dra is not available in 16.6 release
1113656 SIP_LAYOUT    WIREBOND         Enable Changecharacteristic to work without unfixing its Tack point.
1113838 SIP_LAYOUT    DIE_ABSTRACT_IF  probe pinsdefined in XDA die abstract file are added with wrong location
, s% M  t) b0 x. }& j% d# K( p1113991 CAPTURE       GENERAL          Save Project Asis not working if destination is a linux machine
1114073 APD           DRC_CONSTRAINTS  Shape voidingdifferently if there are Fillets present in the design.
1114241 CAPTURE       SCHEMATIC_EDITOR Port not retaining assigned color, when moved on theschematic
1114442 PSPICE        PROBE            Getting Internalerror - Overflow Convert with marching waveform on
# \  U/ n2 ?& x1114630 CONCEPT_HDL   ARCHIVER         Archcore failsbecause the project directory on Linux has a space in the name
1114689 CONCEPT_HDL   CORE             Unknown projectdirective : text_editor
1114928 F2B           PACKAGERXL       縀rror (SPCODD - 5) while Export Physical even afterchange pin from A<0> to A
1116886 CONCEPT_HDL   CORE             Crefer hyperlinksdo not work fine when user use double digits partitions for page Border.
1118088 ALLEGRO_EDITOR EDIT_ETCH        Should Plan accurate and Optimize beremoved in 16.6?
1118734 APD           EDIT_ETCH        Multiline routingwith Clines on Null Net cannot route in downward direction
1118756 ALLEGRO_EDITOR SHAPE            Shape clearance parameter oversizevalues getting applied to Keepouts
1119606 CONCEPT_HDL   MARKERS          Filtering two ormore words in Filter dialog box
1119707 CONCEPT_HDL   CORE             Genview does not use site colors when gen schfrom block symbol
1119711 F2B           DESIGNSYNC       DesignDifferences show Net Differences wrongly
( p5 t- I( j5 _" o$ |6 v: A% F1120659 CAPTURE       PROJECT_MANAGER  "Saveproject as" does not support some of Nordic characters.
1120660 CONCEPT_HDL   CORE             Save hierarchysaves pages for deleted blocks.
1120817 SIP_LAYOUT    SYMB_EDIT_APPMOD Rotate Pads commands not working while in the SymbolEdit App. mode
% {. m' K+ `" g: V2 H( n1120985 PSPICE        MODELEDITOR      Unable to importattached IBIS model
1121171 CONCEPT_HDL   CREFER           PNN and correctproperty values not annotated on the Cref flat schematic
* E1 q+ o" L" N0 D1 ]. U1121353 ALLEGRO_EDITOR INTERACTIV       Local env setting will change aftersaving and reopening.
3 b' h* T6 ^; ?1 P8 h. v1121382 ALLEGRO_EDITOR INTERACTIV       Undo command is limited to two for thisdesign
5 r. r0 l9 o( J1121540 F2B           PACKAGERXL       pxl.chg keepsdeleting and adding changes on subsequent packager runs
1121558 ALLEGRO_EDITOR MODULES          Unrouted net and unrouted connectionwhen module is placed of completely routed board file.
1121585 ALLEGRO_EDITOR OTHER            Drill Hole to Shape Same NetSpacing with Dynamic Shapes shows wrong result.
6 q3 W% d' Z9 h5 `/ g1121651 CAPTURE       SCHEMATIC_EDITOR "PCB editor select" menu option is missing
" k# H" w1 t* K0 x- U: Z) `1 z1122136 SIP_LAYOUT    PLACEMENT        Moving acomponent results in the components outline going to bottom side of the design.
1122340 CAPTURE       NETLIST_ALLEGRO  Cross probe ofnet within a bus makes Capture to hang.
3 ~, P; w0 e$ q1 o3 d. o1122489 CONCEPT_HDL   OTHER            Save _Hierarchycausing baseline to brd files
$ j3 n0 u7 j: B* C1 B1122781 CONCEPT_HDL   CORE             cfg_package isgenerated for component cell automatically
1122909 CONCEPT_HDL   CORE             changing versionreplicates data of first TOC on 2nd one
2 ]  x) V& V2 |$ `8 u1123150 CONCEPT_HDL   CORE             property on yaxis in symbol view was moved by visibility change to None.
1123176 ALLEGRO_EDITOR UI_FORMS         Negative values for pop-up location isnot retained with multiple monitors (more than 2)
0 z4 D* P" {2 r6 u1123815 ALLEGRO_EDITOR GRAPHICS         Embedded netname changes to a differentnetname
1 B0 O* Q- m" n' i% Z# M& M1124369 ALLEGRO_EDITOR INTERACTIV       Sliding a shape using iy coordinate doesnot work indepedent of grid.
1124544 CONCEPT_HDL   CORE             About SearchHistory of find with SPB16.5
1124570 APD           IMPORT_DATA      When importingStream adding the option to change the point
1125201 CONCEPT_HDL   CORE             Connectivityedits in NEW block not saved( lost) if block is created using block add
1125314 ALLEGRO_EDITOR INTERACTIV       Enved crash during setting of library paths inuser preference
1125366 CONCEPT_HDL   CORE             DE-HDL crachesduring Import Physical if CM is open on Linux
1125628 CONCEPT_HDL   CORE             Crash on doingsave hierarchy
6 m; Q# W7 N+ ]2 j7 z) v+ L) O5 ]1130555 APD           WIREBOND         Wirebond Import should connect to pinsof the die specified on the UI.
. c, O' _4 N/ C" e5 H1131030 PSPICE        ENVIRONMENT      Unregistered iconof Simulation setting in taskbar
, A# Y  Q$ I7 J' H0 I4 e1131083 ALLEGRO_EDITOR INTERACTIV       Bug: 16.6 crash in changing the mode inFind filter window
1131226 ALLEGRO_EDITOR PLACEMENT        When Angle is set in design parameterswhile placement component is rotated but outline is not.
& `  h0 l3 L/ l% M! e1131567 CONCEPT_HDL   OTHER            Lower case valuesfor VHDL_MODE make genview use pin location to determen direction.
2 i' Q) _) e- b: d9 q$ P' ?* y1131699 PSPICE        PROBE            Probe windowcrash on trying to view simulation message
1132457 CONCEPT_HDL   CORE             The schematicnever fully invokes and has connectivity errors.
1132575 CONCEPT_HDL   CORE             2 pin_name weredisplayed and overlapped by spin command.
1132698 ALLEGRO_EDITOR EDIT_ETCH        Slide Via with Segment option with newSlide command
1132964 ALLEGRO_EDITOR SHAPE            Same net "B&B via toshape" errors created when adding shape
2 }, m0 O  N. A: Z. G6 e1133677 CONCEPT_HDL   CORE             Cant delete norreset LOCATION prop in context of top
$ s) y* K0 f" R- \1133791 CONCEPT_HDL   CORE             Cant do textjustification on a single selected NOTE in Windows mode.
1134761 CONCEPT_HDL   CORE             Why does MousePointer/Tooltip display LOCATION instead of $LOCATION property
1135118 ALLEGRO_EDITOR INTERACTIV       Mirror and other editing commands aremissing for testpoint label text in general edit mode.
6 o* G( r7 N3 L/ H+ \8 a$ \1136420 CAPTURE       GENERAL          Registrationissue when CDSROOT has a space in its path
1136808 PSPICE        STABILITY        Pspice crashmarker server has quite unexpectedly
1136840 CAPTURE       SCHEMATICS       Enh: Alignment oftext placed on schematic page
4 c( t6 V4 y6 N. C# h, g1138586 ADW           MIGRATION        design migrationdoes not create complete ptf file for hierarchical designs
) Q5 y+ F$ \! V: f5 W8 X1139376 CONCEPT_HDL   CORE             setting wirecolor to default creates new wire with higher thickness
1140819 APD           GRAPHICS         Bbvia does notretain temp highlight color on all layers when selected.
* ]" \. J& y/ z! p# g1141300 CONCEPT_HDL   CORE             DE HDL hier_writesave hierarchy log reports summarizes Successfully saved block x while blockwas skipped
1141723 ADW           PURGE            purge commandcrashes with an MFC application failure message
" q9 H6 k8 r# L! \& N# C( N1143448 CAPTURE       GENERAL          About copy &paste to Powerpoint from CIS
5 B$ j; P. u9 A/ B( @) X& v; J1143670 SIP_LAYOUT    OTHER            Cross Probingbetween SiP and DEHDL not working in 16.6 release
1143902 ALLEGRO_EDITOR DATABASE         when the shape is rotated 45 degreesthe void is moved.
1144990 PCB_LIBRARIAN CORE             PDV expand &collapse vector pins resizes symbol outline to maximum height
1145112 CONCEPT_HDL   CORE             Warning message:Connectivity MIGHT have changed
- u% }6 J8 v! q, o$ s) H" M1145253 CONCEPT_HDL   CORE             Component Browseradds properties in upper case
1146386 ALLEGRO_EDITOR INTERACTIV       Place Replicate Create add Static shapewith Fillet shape
1146728 F2B           PACKAGERXL       DCF with upperand lower case values on parts causes pxl to fail
1146783 ALLEGRO_EDITOR INTERFACES       Highlighted component is missing fromexported IPF file.
1147326 CONCEPT_HDL   CORE             HDL crashes whentrying to reimport a block
# T( a- @3 r8 T! E) d. U1148337 CAPTURE       ANNOTATE         Checking "refdes control" isnot giving the proper annotation result
1148633 SIP_LAYOUT    INTERACTIVE      Add "%"to the optical shrink option in the co-design die and compose symbol placementforms
4 F3 z3 w5 M* z1 [" O1149778 CAPTURE       SCHEMATICS       Rotation of pspice marker before placementis not appropriate
1149987 PCB_LIBRARIAN PTF_EDITOR       Save As pushingthe part name suffix into vendor_part_number value
3 m) o* |" N3 o) c! k# K3 v1151748 ALLEGRO_EDITOR OTHER            If the pad and cline are the samewidth don't report a missing Dynamic Fillet.
1152206 CONCEPT_HDL   CORE             ROOM Propertyvalue changes when saving another Page
1152755 CONCEPT_HDL   COPY_PROJECT     Copy projecthangs if library or design name has an underscore
) S0 \, T8 N# A2 |1152769 PSPICE        ENCRYPTION       Unable to simulate Encrypted Models in16.6
1153308 ALLEGRO_EDITOR DRC_CONSTR       Creating Artwork Getting Warning"DRC is out of Date" even when DRC is up to date
7 w& l  [% E) {0 K9 n/ T) w& X  A1153893 F2B           DESIGNVARI       16.6 VariantEditor not supporting - in name
1154185 SIG_INTEGRITY SIGNOISE         Signoise didn'tdo the Rise edge time adjustment.
1154860 ALLEGRO_EDITOR MANUFACT         Double digit drill character overlapswith figures triangle, hexagon and octagon in NC drill legend
1155167 ALLEGRO_EDITOR EDIT_ETCH        Via structure placed in Create Fanouthas incorrect rotation.
1155728 CONCEPT_HDL   CORE             Unable to uprevpackaged 16.3 design in 16.5 due to memory
  j1 ~) p3 b7 J5 ~) z( U' M1155855 SCM           SCHGEN           A newlyuser-defined net property is not transferred from SCM to DEHDL in PreservedMode
1156274 ALLEGRO_EDITOR INTERFACES       Exported Step file from Allegro is wrong
1156316 CONSTRAINT_MGR OTHER            Break in functionality whilecreation of pin-pairs under Xnet in Constraint Manager
6 l, L( s$ _0 T7 J; F1156351 CONCEPT_HDL   CONSTRAINT_MGR   Loose members inPhysical Net Class between DEHDL and Allegro
9 N" E6 O! B1 s; ~1156547 ALLEGRO_EDITOR DRC_CONSTR       Etch Turn under SMD pin rule checkthrough pin Etch makes confused.
1156779 CONSTRAINT_MGR OTHER            Electrical Cset References in CM notworking correctly
1157167 ALLEGRO_EDITOR SKILL            axlPolyFromDB with ?line2poly isbroken
1158042 ALLEGRO_EDITOR DFA              DFA_DLG writes the dra file namein uppercase.
1 i0 j0 \& x; n; U, p1158718 CONCEPT_HDL   CHECKPLUS        Customer couldnot get $PN property values on logical rule of CheckPlus16.6.
) t1 ?% K9 ~4 O9 L) _5 ^1 r! ]+ ~/ p* U1158970 ALLEGRO_EDITOR SCHEM_FTB        Changing LOCATION to $LOCATION in DEHDLdoes not update the .brd file
5 M, B- i2 W# t5 P4 u1158989 ALLEGRO_EDITOR INTERFACES       pdf_out -l creates a PDF
1159285 APD           DXF_IF           DXF_OUT fails;some figures are not exported
4 q2 {$ p1 D( k, [- H) D5 ~/ ?6 x8 s1159432 ALLEGRO_EDITOR SHOW_ELEM        http:// in the Show Element in 166 donot have HTML link to open the Website
1159483 PCB_LIBRARIAN SETUP            part developercrashing with
1 l5 w" s/ e; a% z1159516 ALLEGRO_EDITOR EDIT_ETCH        Unable to slide cline segment with newslide.
1159959 ALLEGRO_EDITOR GRAPHICS         3D viewer displays clines arcsincorrectly
1160004 SCM           UI               The RMB->Pastedoes not insert signal names.
1160410 ALLEGRO_EDITOR DATABASE         Lock databse with View Lock option ismisleading
2 h5 g8 j  V! H! _2 ]6 c; Y/ d5 Y1160529 SCM           SCHGEN           Schematicgeneration stopped because the tool was unable to create an appropriateinternal symbol structure
4 t, X, q) U4 s' I& [9 k1160537 SPIF          OTHER            Cannot start PCBRouter
3 a6 y4 Q3 [6 m2 e1161363 ALLEGRO_EDITOR SYMBOL           Getting error SPMHGE-73 when tryingto mirror symbol
" W0 z) b2 f+ X) ^! n1161781 CONSTRAINT_MGR CONCEPT_HDL      SigXp crash when selecting ECset indesign
1161896 ALLEGRO_EDITOR DRAFTING         Tolerance value added for Dimensionsis not working correctly (HF11-12)
- P" `+ ^% A6 Q* j! w) _; U& N$ @1162193 SIP_LAYOUT    DIE_ABSTRACT_IF  shapes in diafile not linked to the die after edit co-design die
1162754 APD           VIA_STRUCTURE    Replace Via Structurecommand selecting dummy nets.