Hotfix_SPB16.60.013_wint_1of1

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Cadence SPB16.6下载(Hotfix013已发布)

; \+ W# m* R' a: m# _7 ^Cadence SPB16.6已经推出，需要的朋友可以点击下面的链接下载：
3 D/ m: M! O9 y6 Y4 i5 t5 Phttp://dl.vmall.com/c0ych9k8m3
7 t$ F$ J4 ~. _; q9 C

6 ^" X6 H! Q  [4 }) sDATE: 07-26-2013  HOTFIX VERSION: 013
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- ^2 K7 k/ u8 s# L( mCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
===================================================================================================================================
111368 CAPTURE        CORRUPT_DESIGN   Capture - will not produce allegro netlistwith 10.0
134439 PD-COMPILE     USERDATA         caCell terminals should be top-levelterminals
, l1 T$ S4 o( A" V" j. B186074  CIS            EXPLORER         refresh symbols from lib requires youto close CIS
0 _# l1 B* K4 A( S7 |: m583221 CAPTURE        SCHEMATIC_EDITOROption to have the Schematic Page Name as a Property in the Titleblock
5 X9 X* ^5 P0 W1 m1 ?* X- ]591140 CONCEPT_HDL    OTHER            Scale overall output size inPublishPDF from command line
801901 CONCEPT_HDL    CORE             Concept Menus use the same key"R" for the Wire and RF-PCB menus
813614  APD            DRC_CONSTRAINTS  With Fillets present the "cline toshape" spacing is wrong.
881796 ALLEGRO_EDITOR GRAPHICS        Enhancement request for Panning with Middle Mouse Button
/ i. q+ a1 p: ~4 f- H8 b" o! z  W887191 CONCEPT_HDL    CORE             Cannot add/edit the locked property
911292 CONCEPT_HDL    CORE             Property command on editing symbolattaches property to ORIGIN immediately
987766  APD            SHAPE            Void all command gets result as novoids being generated on specific env.
1001395 SIP_LAYOUT    ASSY_RULE_CHECK  Shape Minimumvoid check reports lots of DRCs which are not necessary to check out.
1030696 ALLEGRO_EDITOR INTERACTIV       Enh - Allow another behavior of PANmovement using middle mouse in Allegro
5 t+ @( e$ W) q/ }! w1043856 ADW           TDA              Diff between TDOand DE-HDL Hierarchy Viewer is confusing to the user
2 V/ f/ N, w: I) b. p1046440 ADW           PCBCACHE         ADW: ImportSheetis not caching libraries under flatlib/model_sym when the source design is notan ADW project
1077552 F2B           PACKAGERXL       Diff Pairs get removed when packing withbackannotation turned on
# Z6 v; _/ x9 n! w$ \2 h$ F: `1079538 F2B           PACKAGERXL       Ability to blockall 縮ingle noded nets� to the board while packaging.
5 x+ p. g" Y$ _' U. q1086362 ALLEGRO_EDITOR SHAPE            Enhancement request to autovoid a viaif shape cannot cover the center of the via.
( L! c  d& i3 e  m& ?  D1087958 PSPICE        MODELEDITOR      Is there anylimitation for pin name definition?
$ I* v0 T9 ^7 B- T1087967 CIS           UPDATE_PART_STAT Update part status window shows incorrect differences
+ p  Y+ ~$ Y% g9 T; x1 ]1090693 ADW           LRM              LRMauto_load_instances does not gray out Load instances Button
8 G) Q& {1 X" @* ?2 \9 x1097246 CONCEPT_HDL   CORE             ConceptHDL -assign hotkeys to alpha-numerical keys
" G$ O' f7 A# N: I3 @1099773 CONCEPT_HDL   CORE             DE HDL goes intorecursive loop if a custom text locked at site level is deleted from Tools >Option
1100945 SCM           SCHGEN           SCM generatedDE-HDL has $PN placement issue
1100951 PSPICE        SIMULATOR        Increasing theresolution of fourier transform results in out file
1103117 RF_PCB        FE_IFF_IMPORT    Enh- Allow theAllegro_Discrete_Library_to_ADS_Library_Translator to output in its originalunit
2 R, L7 w" C& \8 c+ H1105473 PSPICE        PROBE            Getting errormessages while running bias point analysis.
9 X9 Z6 L2 e0 r5 h0 L; l1106116 FLOWS         PROJMGR          view_pcb settingchange was cleared by switching Flows in projmgr.
7 h" O% B5 [) ^/ s# [, n1106298 ALLEGRO_EDITOR INTERACTIV       Copy Shape uses last menu pick locationas origin and not the Symbol Origin as specified in Options.
9 \' z) Q$ \$ N; L4 E5 ~9 P1106626 CONCEPT_HDL   CORE             Concept HDL crashes when saving pages
1107086 ALLEGRO_EDITOR INTERACTIV       manual void with arc's goes in wrongdirection during arc creation
! H2 C$ M+ ]) [; T6 k, i6 e# e# E1107172 CONCEPT_HDL   OTHER            Project ManagerPackager does not report errors on missing symbol
1 ?- D8 ?* z0 B  s2 J1108193 CONCEPT_HDL   CORE             Using theleft/right keys do not move the cursor within the text you're editing
# j) K3 n1 B0 `0 D6 e1108603 PCB_LIBRARIAN VERIFICATION     PDV ToolsVerification > View Verification (CheckPlus) leaves<project>.cpm_tmp.cpm
1109024 CIS            OTHER            OrCad performance issue from Asus.
1109109 CAPTURE       NETLIST_ALLEGRO  B1: Netlistmissing pins when Pack_short property pins connected
1109466 ALLEGRO_EDITOR ARTWORK          Artwork create some strange gerberlines for fillet.
0 Q2 ^9 `  l5 @( ^4 s, K6 t$ y1109647 SIP_LAYOUT    DEGASSING        Shape degassingcommand enhancement - control over what layers are counted in even/odd layersets.
% {% ?& }$ F& _. \4 Q1109926 CONCEPT_HDL   CORE             viewing a designdisables console window
1110194 SIP_LAYOUT    WIREBOND         If OpenGL settings for display ofdynamic net names is enabled, should be visible while push/shove wirebonds.
1 q) R7 X- C8 v: v4 Z0 b1112357 SIP_LAYOUT    WIREBOND         wirebond commandcrashes the application
1112395 CONCEPT_HDL   CORE             縗BASE\G� for global signal is not obeyedafter upreving the design to 1650.
( K; A. @5 d2 `9 ^, K+ M4 K$ D2 M1112658 CAPTURE       PROPERTY_EDITOR  Changing Part 縂raphic� value from property EditorChanges Occ refdes values to instance
5 p  ?- Q  H# j" U3 L1112662 CAPTURE       PROJECT_MANAGER  Capture crashesafter moving the library file and then doing Edit> Cut
+ f1 Q: t* c8 l- r# u( e1113177 PCB_LIBRARIAN CORE             Pin Shapes arenot getting imported properly
& b% C" B9 _$ I' t1113380 ALLEGRO_EDITOR INTERACTIV       Change layer to - option for packagetype .dra is not available in 16.6 release
1113656 SIP_LAYOUT    WIREBOND         Enable Changecharacteristic to work without unfixing its Tack point.
1 A& T% G$ h6 d* L# m/ Q4 Q' O1113838 SIP_LAYOUT    DIE_ABSTRACT_IF  probe pinsdefined in XDA die abstract file are added with wrong location
& x5 h9 o3 x2 `# \4 N, a1113991 CAPTURE       GENERAL          Save Project Asis not working if destination is a linux machine
9 C, v; |* N" s1 {1114073 APD           DRC_CONSTRAINTS  Shape voidingdifferently if there are Fillets present in the design.
: u$ J: e4 L/ a+ l" [6 x6 v1114241 CAPTURE       SCHEMATIC_EDITOR Port not retaining assigned color, when moved on theschematic
1114442 PSPICE        PROBE            Getting Internalerror - Overflow Convert with marching waveform on
1114630 CONCEPT_HDL   ARCHIVER         Archcore failsbecause the project directory on Linux has a space in the name
" A! I. ~' e, V+ P0 h0 u- W% ]1114689 CONCEPT_HDL   CORE             Unknown projectdirective : text_editor
1114928 F2B           PACKAGERXL       縀rror (SPCODD - 5) while Export Physical even afterchange pin from A<0> to A
1116886 CONCEPT_HDL   CORE             Crefer hyperlinksdo not work fine when user use double digits partitions for page Border.
1118088 ALLEGRO_EDITOR EDIT_ETCH        Should Plan accurate and Optimize beremoved in 16.6?
1 M! v) Z2 L3 ^$ i1118734 APD           EDIT_ETCH        Multiline routingwith Clines on Null Net cannot route in downward direction
1118756 ALLEGRO_EDITOR SHAPE            Shape clearance parameter oversizevalues getting applied to Keepouts
1119606 CONCEPT_HDL   MARKERS          Filtering two ormore words in Filter dialog box
5 }: y% C; p+ J( Z' x1119707 CONCEPT_HDL   CORE             Genview does not use site colors when gen schfrom block symbol
1119711 F2B           DESIGNSYNC       DesignDifferences show Net Differences wrongly
+ f# ]: k! C' d- g- @% t# W1 z1120659 CAPTURE       PROJECT_MANAGER  "Saveproject as" does not support some of Nordic characters.
5 y5 n4 X* t3 y0 H+ p; i1120660 CONCEPT_HDL   CORE             Save hierarchysaves pages for deleted blocks.
1120817 SIP_LAYOUT    SYMB_EDIT_APPMOD Rotate Pads commands not working while in the SymbolEdit App. mode
1120985 PSPICE        MODELEDITOR      Unable to importattached IBIS model
1121171 CONCEPT_HDL   CREFER           PNN and correctproperty values not annotated on the Cref flat schematic
8 t9 `" ]! t# [  R1121353 ALLEGRO_EDITOR INTERACTIV       Local env setting will change aftersaving and reopening.
1121382 ALLEGRO_EDITOR INTERACTIV       Undo command is limited to two for thisdesign
* U# K# B% E9 y$ ?3 R5 v7 H$ y* L1121540 F2B           PACKAGERXL       pxl.chg keepsdeleting and adding changes on subsequent packager runs
1121558 ALLEGRO_EDITOR MODULES          Unrouted net and unrouted connectionwhen module is placed of completely routed board file.
1121585 ALLEGRO_EDITOR OTHER            Drill Hole to Shape Same NetSpacing with Dynamic Shapes shows wrong result.
1121651 CAPTURE       SCHEMATIC_EDITOR "PCB editor select" menu option is missing
1122136 SIP_LAYOUT    PLACEMENT        Moving acomponent results in the components outline going to bottom side of the design.
1122340 CAPTURE       NETLIST_ALLEGRO  Cross probe ofnet within a bus makes Capture to hang.
8 r+ n3 g/ \* J; X# \0 L- f( s1122489 CONCEPT_HDL   OTHER            Save _Hierarchycausing baseline to brd files
* f1 N8 F  I( |, X2 e* Y% Z# t1122781 CONCEPT_HDL   CORE             cfg_package isgenerated for component cell automatically
/ X! ?% S8 M: h) E  E9 g1122909 CONCEPT_HDL   CORE             changing versionreplicates data of first TOC on 2nd one
1123150 CONCEPT_HDL   CORE             property on yaxis in symbol view was moved by visibility change to None.
$ N# r5 |: h( I: c4 I* J( a1123176 ALLEGRO_EDITOR UI_FORMS         Negative values for pop-up location isnot retained with multiple monitors (more than 2)
) ?% y  `- ~% U; `4 x+ `8 ?1123815 ALLEGRO_EDITOR GRAPHICS         Embedded netname changes to a differentnetname
: R$ a) w( a3 b1124369 ALLEGRO_EDITOR INTERACTIV       Sliding a shape using iy coordinate doesnot work indepedent of grid.
1124544 CONCEPT_HDL   CORE             About SearchHistory of find with SPB16.5
1124570 APD           IMPORT_DATA      When importingStream adding the option to change the point
0 v2 P6 g0 j4 S# y1125201 CONCEPT_HDL   CORE             Connectivityedits in NEW block not saved( lost) if block is created using block add
5 N; w( a  s7 A1125314 ALLEGRO_EDITOR INTERACTIV       Enved crash during setting of library paths inuser preference
: Z$ w  Q, \5 _( W# G1125366 CONCEPT_HDL   CORE             DE-HDL crachesduring Import Physical if CM is open on Linux
) g' ?& L) P& T; |# c+ v1125628 CONCEPT_HDL   CORE             Crash on doingsave hierarchy
2 |3 Y8 L$ n, ~' ^! X# ]; c5 G1130555 APD           WIREBOND         Wirebond Import should connect to pinsof the die specified on the UI.
+ X( ~7 E0 `- l" P1131030 PSPICE        ENVIRONMENT      Unregistered iconof Simulation setting in taskbar
3 l2 L! Y7 c8 p4 X1131083 ALLEGRO_EDITOR INTERACTIV       Bug: 16.6 crash in changing the mode inFind filter window
1131226 ALLEGRO_EDITOR PLACEMENT        When Angle is set in design parameterswhile placement component is rotated but outline is not.
* A3 ]3 \) v/ u. s, B1131567 CONCEPT_HDL   OTHER            Lower case valuesfor VHDL_MODE make genview use pin location to determen direction.
1131699 PSPICE        PROBE            Probe windowcrash on trying to view simulation message
. a+ @! A6 C' R' |, k; z1132457 CONCEPT_HDL   CORE             The schematicnever fully invokes and has connectivity errors.
1132575 CONCEPT_HDL   CORE             2 pin_name weredisplayed and overlapped by spin command.
1132698 ALLEGRO_EDITOR EDIT_ETCH        Slide Via with Segment option with newSlide command
1132964 ALLEGRO_EDITOR SHAPE            Same net "B&B via toshape" errors created when adding shape
1133677 CONCEPT_HDL   CORE             Cant delete norreset LOCATION prop in context of top
1133791 CONCEPT_HDL   CORE             Cant do textjustification on a single selected NOTE in Windows mode.
1134761 CONCEPT_HDL   CORE             Why does MousePointer/Tooltip display LOCATION instead of $LOCATION property
1135118 ALLEGRO_EDITOR INTERACTIV       Mirror and other editing commands aremissing for testpoint label text in general edit mode.
( C/ W5 Y$ c+ ]1136420 CAPTURE       GENERAL          Registrationissue when CDSROOT has a space in its path
1136808 PSPICE        STABILITY        Pspice crashmarker server has quite unexpectedly
$ O% E# U# N4 j- Z  X* F. v1136840 CAPTURE       SCHEMATICS       Enh: Alignment oftext placed on schematic page
9 S: i; S3 N5 i) f, a# Y1138586 ADW           MIGRATION        design migrationdoes not create complete ptf file for hierarchical designs
1139376 CONCEPT_HDL   CORE             setting wirecolor to default creates new wire with higher thickness
1140819 APD           GRAPHICS         Bbvia does notretain temp highlight color on all layers when selected.
- {* m: B* u, m$ @6 w5 t1141300 CONCEPT_HDL   CORE             DE HDL hier_writesave hierarchy log reports summarizes Successfully saved block x while blockwas skipped
6 W; H9 _9 ?- `; c3 N5 u' j: u" h1141723 ADW           PURGE            purge commandcrashes with an MFC application failure message
6 o! o$ @6 M! X7 p/ {1143448 CAPTURE       GENERAL          About copy &paste to Powerpoint from CIS
1143670 SIP_LAYOUT    OTHER            Cross Probingbetween SiP and DEHDL not working in 16.6 release
1143902 ALLEGRO_EDITOR DATABASE         when the shape is rotated 45 degreesthe void is moved.
2 B. E: P+ A0 O; u) r3 v. O3 `2 |: E1 g1144990 PCB_LIBRARIAN CORE             PDV expand &collapse vector pins resizes symbol outline to maximum height
$ ?0 V5 b+ V4 {1145112 CONCEPT_HDL   CORE             Warning message:Connectivity MIGHT have changed
1145253 CONCEPT_HDL   CORE             Component Browseradds properties in upper case
1146386 ALLEGRO_EDITOR INTERACTIV       Place Replicate Create add Static shapewith Fillet shape
) Q3 V3 _( Y7 ^/ h% N5 n8 N0 R1146728 F2B           PACKAGERXL       DCF with upperand lower case values on parts causes pxl to fail
0 z. k: W; |' u) ]" U4 t9 ^1146783 ALLEGRO_EDITOR INTERFACES       Highlighted component is missing fromexported IPF file.
: Z- @- \" R! u0 r1147326 CONCEPT_HDL   CORE             HDL crashes whentrying to reimport a block
1148337 CAPTURE       ANNOTATE         Checking "refdes control" isnot giving the proper annotation result
1148633 SIP_LAYOUT    INTERACTIVE      Add "%"to the optical shrink option in the co-design die and compose symbol placementforms
1149778 CAPTURE       SCHEMATICS       Rotation of pspice marker before placementis not appropriate
1149987 PCB_LIBRARIAN PTF_EDITOR       Save As pushingthe part name suffix into vendor_part_number value
1151748 ALLEGRO_EDITOR OTHER            If the pad and cline are the samewidth don't report a missing Dynamic Fillet.
+ R- f$ V. X) r$ ~# f1152206 CONCEPT_HDL   CORE             ROOM Propertyvalue changes when saving another Page
5 X( [+ |7 S( a( v; y  J6 I1152755 CONCEPT_HDL   COPY_PROJECT     Copy projecthangs if library or design name has an underscore
' T' d6 y- D& M6 n' e1152769 PSPICE        ENCRYPTION       Unable to simulate Encrypted Models in16.6
1153308 ALLEGRO_EDITOR DRC_CONSTR       Creating Artwork Getting Warning"DRC is out of Date" even when DRC is up to date
1153893 F2B           DESIGNVARI       16.6 VariantEditor not supporting - in name
: E0 S) j4 p2 V" w2 k1154185 SIG_INTEGRITY SIGNOISE         Signoise didn'tdo the Rise edge time adjustment.
1154860 ALLEGRO_EDITOR MANUFACT         Double digit drill character overlapswith figures triangle, hexagon and octagon in NC drill legend
- A0 @# V/ `0 A- K! j1155167 ALLEGRO_EDITOR EDIT_ETCH        Via structure placed in Create Fanouthas incorrect rotation.
5 E0 {) c0 U0 j* j1155728 CONCEPT_HDL   CORE             Unable to uprevpackaged 16.3 design in 16.5 due to memory
( D+ s0 @. E2 ?! r# I1155855 SCM           SCHGEN           A newlyuser-defined net property is not transferred from SCM to DEHDL in PreservedMode
8 M% N, a7 e- p9 X0 \! E) F2 P1156274 ALLEGRO_EDITOR INTERFACES       Exported Step file from Allegro is wrong
- N  q& O) M# {/ `" w5 o: ~1156316 CONSTRAINT_MGR OTHER            Break in functionality whilecreation of pin-pairs under Xnet in Constraint Manager
: u2 ^5 u8 x# \+ N& \$ Y# o1156351 CONCEPT_HDL   CONSTRAINT_MGR   Loose members inPhysical Net Class between DEHDL and Allegro
1156547 ALLEGRO_EDITOR DRC_CONSTR       Etch Turn under SMD pin rule checkthrough pin Etch makes confused.
1156779 CONSTRAINT_MGR OTHER            Electrical Cset References in CM notworking correctly
0 f1 z' d9 F" M1157167 ALLEGRO_EDITOR SKILL            axlPolyFromDB with ?line2poly isbroken
1158042 ALLEGRO_EDITOR DFA              DFA_DLG writes the dra file namein uppercase.
1158718 CONCEPT_HDL   CHECKPLUS        Customer couldnot get $PN property values on logical rule of CheckPlus16.6.
. [  M. u+ q7 f) h1158970 ALLEGRO_EDITOR SCHEM_FTB        Changing LOCATION to $LOCATION in DEHDLdoes not update the .brd file
1158989 ALLEGRO_EDITOR INTERFACES       pdf_out -l creates a PDF
  A$ b/ K$ l6 X; H4 u& q1159285 APD           DXF_IF           DXF_OUT fails;some figures are not exported
) s1 S4 r8 A9 v8 M$ N. q1159432 ALLEGRO_EDITOR SHOW_ELEM        http:// in the Show Element in 166 donot have HTML link to open the Website
5 k( ^: c5 t+ Z! U7 ]: `7 {8 ?9 Q1159483 PCB_LIBRARIAN SETUP            part developercrashing with
" P$ @% o& K' W1159516 ALLEGRO_EDITOR EDIT_ETCH        Unable to slide cline segment with newslide.
5 x( J7 p/ p1 J$ {% r, j3 V1159959 ALLEGRO_EDITOR GRAPHICS         3D viewer displays clines arcsincorrectly
% \/ K3 A& h# p) Y1160004 SCM           UI               The RMB->Pastedoes not insert signal names.
1160410 ALLEGRO_EDITOR DATABASE         Lock databse with View Lock option ismisleading
! w- d( z, ^+ X  b7 }1160529 SCM           SCHGEN           Schematicgeneration stopped because the tool was unable to create an appropriateinternal symbol structure
1 ^; y8 |% Q) w- F1160537 SPIF          OTHER            Cannot start PCBRouter
1161363 ALLEGRO_EDITOR SYMBOL           Getting error SPMHGE-73 when tryingto mirror symbol
( c2 x& F( A7 M# h/ e: e1161781 CONSTRAINT_MGR CONCEPT_HDL      SigXp crash when selecting ECset indesign
$ f$ M/ c! i& H; V8 I! _( ?* F5 F1161896 ALLEGRO_EDITOR DRAFTING         Tolerance value added for Dimensionsis not working correctly (HF11-12)
; `" B6 o! Q" U/ M# o1162193 SIP_LAYOUT    DIE_ABSTRACT_IF  shapes in diafile not linked to the die after edit co-design die
; J/ O5 r, S& ~. A" R4 b; W0 i1162754 APD           VIA_STRUCTURE    Replace Via Structurecommand selecting dummy nets.