基于FPGA的单稳态脉冲展宽电路的设计问题！

marshal403006

请各位高手看看本人的程序，编译通过了，仿真却没有结果。我想实现的功能是单稳态脉冲展宽（通过外端口控制展宽宽度）。程序如下：
7 s. S. I; v# n, [8 @计数器（控制展宽电路的宽度）部分：
; N% e, \, h- y8 E, dlibrary IEEE;
use IEEE.STD_LOGIC_1164.ALL;
; j9 h1 i! Z5 _$ _' Ouse IEEE.STD_LOGIC_ARITH.ALL;
1 ?9 ~+ \6 I9 @+ O3 e1 buse IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
; d/ T  K1 R/ |) J  port(reset,en,clk: in std_logic;
. E( s0 ]+ h9 k# V5 y1 [8 @7 g       N1,N2,N3,N4: in std_logic;
       feed_out: out std_logic);
1 n0 T, Y3 ?9 s0 |0 h$ s4 o- `  end counter;
architecture Behavioral of counter is
signal temp: integer range 0 to 15:=0;
signal k:integer:=0;
begin
process(N1,N2,N3,N4,k,clk) is
begin
4 K8 Y3 R8 s  J: f2 N- {) q   if(N1='1') then temp<=temp+1;
. q- Z) O3 N4 o0 ?  elsif(N2='1') then temp<=temp+2;
  m8 w8 ?% p9 l# l0 a! x  elsif(N3='1') then temp<=temp+4;
' B8 i3 E1 n6 A  elsif(N4='1') then temp<=temp+8;
. I  |& a5 Z; V. j+ P# D, W  else null;
  end if;
  if (clk'event and clk='1') then
# A1 {/ @4 O, Y    if (reset='1') then
2 _5 H; b9 f4 c4 l       k<=0;
9 q  K9 {" G$ N7 W! `& `1 t; F     feed_out<='0';
, n5 r2 O: D8 o  }2 ]9 N5 d     elsif (en='1') then   
    if (k=temp-1) then
         feed_out<='1';
         k<=temp-1;
     else k<=k+1;
, k0 x7 Z( c" c1 P    end if;
    end if;
end if;
1 [1 I( _5 ^- x( e( C1 l: ]end process;
1 _5 ^. r4 ^8 h" X$ Send Behavioral;
D触发器（脉冲前沿产生电路，又是展宽脉冲宽度形成电路）：
8 h+ E- D1 W1 P' H3 ylibrary IEEE;
use IEEE.STD_LOGIC_1164.ALL;
# ]! `# D, A$ {, d: xuse IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity D_trigger is
6 X' s: V0 f1 j0 J  s; N' B2 X  port(D,clear: in std_logic;
5 E) J7 z3 J; p7 h! \       clk: in std_logic;
   Q: out std_logic);
end D_trigger;
architecture Behavioral of D_trigger is
7 L" [" u4 _6 Z4 `) ~& D4 Y% \begin
process(D,clear,clk) is
; P- U3 U. C& B5 Qbegin
: I- T3 V' z0 G" Q+ x+ y0 ^$ m  if (clear='1') then
    Q<='0';     
0 I+ e; `6 H/ @( [  elsif (clk'event and clk='1') then
3 G2 @) ~+ z5 _  [    Q<=D;
6 [' _; f9 O" x  end if;
end process;  
0 ~' R) b+ q$ F( U  Cend Behavioral;
1 ]4 C- v8 T0 e  H- F& ?1 l# b8 C" `外部综合部分：
library IEEE;
. i2 u4 U2 ]0 T2 Euse IEEE.STD_LOGIC_1164.ALL;
! O" }$ ?9 A" K; c% P( Uuse IEEE.STD_LOGIC_ARITH.ALL;
( P& K) x2 G2 G: K1 p" t/ ?* ouse IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pulse_expand is
  port(pulse_in,D_in: in std_logic;
& x, Y: e2 [; U- r9 P/ v       clk_in: in std_logic;
- ^, @2 M* q; w* h3 N0 h7 }6 t   n1,n2,n3,n4: in std_logic;
2 Z* m/ r/ b& C   pulsewidth_out: out std_logic);
end pulse_expand;
& |% p4 b% d. U2 h& tarchitecture Behavioral of pulse_expand is
6 B% @- w! M3 ]- `) b) N2 V7 S/ dsignal a1,a2,a3: std_logic;
/ u; _2 q5 K% |3 w* ?: T8 ^& c, icomponent counter is
) s7 ^  q* K) l3 X" o0 G! `   port(reset,en,clk: in std_logic;
      N1,N2,N3,N4: in std_logic;
        feed_out: out std_logic);
  end component counter;
& Y% A4 M& x5 z% o$ C3 t3 @3 N+ u  component  D_trigger is
     port(D,clear: in std_logic;
% q/ F- N6 |6 j, Z  [: x4 F          clk: in std_logic;
" W/ T+ |7 m' s      Q: out std_logic);
  end component D_trigger;
begin
8 k( q. V+ j* F& v2 d1 ~& q% OP1: D_trigger port map (D=>D_in,clear=>a1,clk=>pulse_in,Q=>a2);
5 |! ~& r- N9 B( M0 da3<= not a2;
+ j0 C6 x8 Y- \$ |5 t1 }/ a8 DP2: counter port map ( reset=>a3,en=>a2,clk=>clk_in,feed_out=>a1,
) f: X, n1 W# Z% B% C" I! ]! e$ A    N1=>n1,N2=>n2,N3=>n3,N4=>n4);
/ v, k$ K" A! E5 n$ F' Tpulsewidth_out<=a2;
end Behavioral;

[ 本帖最后由 marshal403006 于 2008-6-2 09:38 编辑 ]