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library IEEE;
& d Q5 @. ?/ B* Y: k9 H0 ?' F7 suse IEEE.STD_LOGIC_1164.ALL;
) ]7 Z$ `; g$ a6 Yuse IEEE.STD_LOGIC_ARITH.ALL;! b5 d7 N4 l) H& U" U) ` o
use IEEE.STD_LOGIC_UNSIGNED.ALL;, v+ m; f# P& R- P7 ^
entity spi is
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(
4 x4 ~8 q5 k- J/ T7 z/ b) Z reset : in std_logic; --global reset signal
& m- `0 ?" E9 Y5 f7 o4 a/ y sysclk : in std_logic; -- systerm clock
4 n6 l5 X$ j7 \, u# r data_in : in std_logic_vector(13 downto 0);. m6 \8 [ Y8 g$ h5 h* }. f
spi_o : out std_logic;
; Q4 ^/ x+ B& m: l: x% r sck_out : out std_logic;; j/ _. E- J. b# y
ss_n : out std_logic_vector(1 downto 0)
6 q$ t9 u" s& M( ^9 e. V );
1 a0 K( `4 J# B' b+ e* Y3 Jend spi;
! r; K7 u1 D4 {% [architecture b of spi is9 K( ?- i1 t% }: ~' E; g# ^
type state_type is (idle,shift,stop); -- data type define
3 { r, v' A4 M signal state : state_type;
; f! e- R! r0 \4 m3 o* s3 u signal out_reg : std_logic_vector(13 downto 0):=(others=>'0');
% M' E$ `3 E, } signal clkdiv_cnt : std_logic_vector(3 downto 0) :=(others=>'0'); g1 b2 a/ O: \2 M
signal bit_cnt : std_logic_vector(3 downto 0) :=(others=>'0');- S3 I4 J5 i) S8 f+ f6 T2 B2 r
signal sck_o : std_logic;
! W8 m( y2 N6 s7 K1 Z+ U2 t signal full : std_logic;
- o1 ]) l5 e, ? ^3 P. `
9 u/ Z( i& Y8 u' B8 ubegin
1 q2 c7 ^8 w9 h ]$ _9 c sck_out <= sck_o;$ {' y5 a ?! c+ Z# R. j+ m
process(sysclk)
+ r. w% D0 Q5 X# M# p, c. t4 t begin6 y; G0 J/ K" g
if (sysclk'event and sysclk = '1') then --reset8 \* |+ @6 F7 t
if (reset = '1') then9 u2 i1 y1 D1 L# i9 i3 S
ss_n <= (others=>'1'); --AD5553 idle CS =11 T4 @* h! I1 L5 d; m
out_reg <= (others=>'0');8 v* Q# y+ T1 ?* j$ ~+ j9 Z
clkdiv_cnt <= (others=>'0');- @: @0 O8 V2 b$ h$ H4 |
bit_cnt <= (others=>'0');1 \9 \5 `" e% ?, E1 r0 f! A
spi_o <= '1';, c( F! h7 ~( y
sck_o <= '0'; -- AD5553 SCK idle is 0
$ s b3 A8 y; k1 l2 x4 k/ `# G/ F state <= idle;, e3 p) C+ D2 {9 G) q
full <= '0';/ B; Q3 Q; }6 ^9 x* }. S6 x
else ; C k4 M& I; q+ b* c9 ?# r( f
if(full = '0') then( M+ s& N# U; {: _) |
out_reg <= data_in ;
' {: a& R+ p: T( v" E full <= '1';$ \0 K( \; u" J# V% c' J4 g+ N% ]
end if;
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case state is
% B* h. l( ] z; @0 [ when idle =>
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/ Z) g; b/ p% {# {( A9 B state <= shift;5 t1 d3 G5 F9 g* i6 v
spi_o <= out_reg(13);9 X: U' y; A( o8 J9 E# W6 h4 \3 _; r+ W
out_reg <= out_reg(12 downto 0) & '0';
/ E; |. S/ J. A sck_o <= '0';
9 Z5 l; x6 C$ i5 i' T$ A8 n when shift =>9 O% Q' H0 |& E, i: }! F# G
clkdiv_cnt <= clkdiv_cnt + '1';$ |: w4 g& h) g7 o/ X( r
if (clkdiv_cnt(2 downto 0)="111") then
3 O# g; T R" ?# l# S sck_o <= not sck_o;' x2 x( Z y: J: S
end if;2 q3 q e e7 y
, a; _* S0 [, K0 V$ } if (clkdiv_cnt = "1111") then* u$ A7 q9 ^0 W& ^ V/ v4 S# V3 X9 c
spi_o <= out_reg(13);, S6 S/ d9 f/ P$ U# t7 I7 y/ V2 j1 l
out_reg <= out_reg(12 downto 0) & '0';( v" m9 W" r5 Q( G
bit_cnt <= bit_cnt + '1';
9 _$ L% a' m4 m) u& L1 h* | end if;, j4 | b+ R; p y$ c
( }: S* A5 N$ V5 H7 L% {' g if (bit_cnt="1110" and clkdiv_cnt = "1111") then) J. Z& Q* r' i7 ^
state <= stop;" m$ y' _, j" ^% | _3 b; D
sck_o <= '0';9 E: j: o: \2 N& s
spi_o <= '1';
, M8 b [$ c7 j( g# p: | end if;
c* H$ l9 ~ S) B
/ J7 h5 L. S: \$ @( o) I when stop =>
7 M; E2 m) a3 v* x" L8 K state <= idle;
' D0 I9 S5 U' I/ i. G sck_o <= '0';5 }2 c) c8 a- I$ K; g ~
spi_o <= '1';' p% \% p1 [6 X; q
clkdiv_cnt <= (others=>'0');
3 r; H- K0 ?2 g( B& z4 z3 B bit_cnt <= (others=>'0');
2 n s; j% q0 T# I full <= '0';
# ^+ Y% Z: j, j0 S% o5 K6 ^0 P when others =>+ c. ~, x2 ~5 Z9 X1 J( p+ Z! Q6 t: [
state <= idle;1 o: Z+ I/ S0 U( U# U9 x; p
end case;
5 Y& w3 P7 |, {- ^( ` end if;# g: W' Y5 h% x( x( p
end if;
) U* z$ J) u# q0 v end process;
! m }, e' J. A* z: n \( R1 Gend b;% s+ H, j; c1 p, {; u/ R& o( v1 l7 j
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/ j1 g; m. P- M7 L7 u其中out_reg 一直是0,在idle状态赋不上值,大家看是怎么回事$ G9 Y! Z- Z3 M: L: _' {) [
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