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library IEEE;7 H- |5 i/ |! U' k' D) C' B
use IEEE.STD_LOGIC_1164.ALL;. a) g/ T( L3 u% @% J0 b* G2 X5 D& J
use IEEE.STD_LOGIC_ARITH.ALL;7 ~6 s6 o% B: P* O8 j! J, [
use IEEE.STD_LOGIC_UNSIGNED.ALL;
# y5 ]' t' H% X/ ^entity spi is 2 ]. ~! c) ?" F8 J9 n4 Z4 [
port
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reset : in std_logic; --global reset signal2 b; r# N- K. }$ k% p6 i
sysclk : in std_logic; -- systerm clock
( w! ?6 v% G4 J# f2 M4 t+ |( s' z data_in : in std_logic_vector(13 downto 0);$ d' w( V+ K( U% d/ g. Z" b3 y" Y/ ~: s
spi_o : out std_logic;2 G1 o) i) P9 v y5 F4 K& B3 b/ {
sck_out : out std_logic;6 a2 j8 A1 y& k0 {7 o3 v9 \
ss_n : out std_logic_vector(1 downto 0)2 a* f0 M/ A$ G0 H% C6 b
);
6 X, u- s+ Z. r0 h# S; t/ B; i2 Qend spi;& [- o$ \" O f4 P5 S1 W, s1 ]2 K
architecture b of spi is
: B' T1 ~0 W3 C5 N& U* D0 S7 Z type state_type is (idle,shift,stop); -- data type define8 z* W9 }' _& w# q l, ^' ?
signal state : state_type;/ J+ P2 p X. L0 M
signal out_reg : std_logic_vector(13 downto 0):=(others=>'0'); a% n c, R3 u- x) M0 o
signal clkdiv_cnt : std_logic_vector(3 downto 0) :=(others=>'0');
, t! g& O; j3 A4 F- Y2 `- a signal bit_cnt : std_logic_vector(3 downto 0) :=(others=>'0');
' r/ Z" ?! x2 u- ?( L signal sck_o : std_logic;9 u& z1 d2 D. m) B
signal full : std_logic;" W" E& N' Y: O2 P: @# m4 C1 q
B1 w& h" ^/ [: \
begin
1 o; E6 u% x) z1 P4 M. L/ u sck_out <= sck_o;
! K n6 B5 g. o$ W- Y process(sysclk)
, Z! z l4 v2 _9 ]: S* z; \ begin
! L. S! E) z; T4 F: | if (sysclk'event and sysclk = '1') then --reset
- X0 S4 t$ V- U5 g6 p" u' P if (reset = '1') then
7 [/ `$ l; t1 C$ T' ^; [1 e ss_n <= (others=>'1'); --AD5553 idle CS =1
! R5 e: \1 _# {3 {; g9 ] out_reg <= (others=>'0');
- @. Z7 y% A) K/ c clkdiv_cnt <= (others=>'0');
7 W- S; W9 }4 ]' s bit_cnt <= (others=>'0');3 t) I( d" a( b9 R8 {
spi_o <= '1';
j/ s6 g) ^8 M6 J, f, z3 V1 | sck_o <= '0'; -- AD5553 SCK idle is 0
$ E# I6 U& D+ P+ B$ a state <= idle;8 j3 f& w# s2 W5 D
full <= '0';
4 r& N" N% o) f5 g; L else 0 r3 h- i9 u# `4 R+ q0 `3 ^
if(full = '0') then0 x7 }7 j; E3 I7 X i1 a- n) e
out_reg <= data_in ;! y1 j# ]& P: f/ _
full <= '1';# @) j4 h2 c5 G6 V" H
end if;
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& Z# _4 |' @& Z) B case state is
/ b2 R& H$ l7 T0 ]; E when idle =>
! s! Q R* I4 x
# H; X0 Y- t# v9 n) t/ u1 U! P& @3 } state <= shift;
. t0 f% |9 U/ z0 ^/ f6 F3 o spi_o <= out_reg(13);, S- `$ d" p: p% L Z9 ~2 A
out_reg <= out_reg(12 downto 0) & '0';
/ W( l. s, z3 U0 J sck_o <= '0';
/ A2 Q, J3 s9 ~* |% d& m when shift =>5 N$ Z2 ~3 r0 K _7 d
clkdiv_cnt <= clkdiv_cnt + '1';
" a! h0 d6 i& J: Y5 a if (clkdiv_cnt(2 downto 0)="111") then2 K7 ]3 v+ p2 L: w4 [, L k
sck_o <= not sck_o;
3 T0 y* w! ]% V& v1 g, {3 Y end if;; v. }* Y3 V# `( e. \* w
1 b% ?4 D8 ~8 h/ S; `; l; l
if (clkdiv_cnt = "1111") then
% r# z( s1 D* n' D spi_o <= out_reg(13);
, o% |5 N$ `+ `- e, a/ Z( f! M- v7 {& F out_reg <= out_reg(12 downto 0) & '0';8 w3 v: u* ?# A# I5 u# E* h J
bit_cnt <= bit_cnt + '1';, u+ l# `$ c8 X) ?% N6 D7 h/ P* i
end if; k9 E. _& R& H+ m
. j8 n# F3 X+ W6 f/ U if (bit_cnt="1110" and clkdiv_cnt = "1111") then2 Z8 d& X' k6 H' |5 D* ]0 V
state <= stop;
* j) u6 v! v& v7 [ sck_o <= '0';
3 |8 @, n9 P0 C: I8 T+ N: q spi_o <= '1';. a, d* j" z; J U
end if;
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when stop =>/ k( Z4 m" [) `% w5 R
state <= idle;
, x* W9 W+ w- }6 _: X7 Y Y sck_o <= '0';, h. }% a, X$ H
spi_o <= '1';8 `9 H8 N6 B% H
clkdiv_cnt <= (others=>'0');
2 q. E/ t3 D) m { bit_cnt <= (others=>'0');! I7 k# M) {( @9 K
full <= '0';8 e1 L5 w5 k: s" r/ q
when others =>
% |+ ^8 f( x5 n7 V state <= idle;
9 }+ E" a% R% A) M end case;0 z1 j' l E6 t* D$ f
end if;! T* s/ x/ q& y. ^3 a8 r, G
end if;( u( {6 p( ?8 f! t/ J1 i. z& |
end process;
7 V4 \) ^7 d0 g& k( ^ tend b;) b8 `% d6 `- n+ a
# q! X9 L3 m$ a: H
2 B' W% {2 M4 Y: q9 T其中out_reg 一直是0,在idle状态赋不上值,大家看是怎么回事7 b' z/ x+ y& P" |$ b
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