问点Quartus II 的问题

sutee7907 · 发表于 2009-4-20 16:49

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为什么我用Verilog HDL语言在 Quartus II 里加上'timescale 10ns/1ns 会提示出错 Error: Verilog HDL syntax error at mult_tp.v(3) near text '
Error: Verilog HDL syntax error at mult_tp.v(3) near text "'"; expecting "module", or "macromodule", or "primitive", or "(*", or "config", or "include", or "library"
Error: Ignored module "mult_tp" at mult_tp.v(4) because of previous errors
Error: Ignored module "mult8" at mult_tp.v(21) because of previous errors
源程序是这样的，
'timescale 10ns/1ns
module mult_tp;
reg[7:0] a,b;
wire[15:0] out;
integer i,j;
mult8 m1(out,a,b);
initial begin
a=0;b=0;
for(i=1;i<255;i=i+1) #10 a=i;
end
initial begin
for(j=i;j<255;j=j+1) #10 b=j;
end
initial begin
$monitor($time,,,"%d*%d=%d",a,b,out);
#2560 $finish;
end
endmodule
module mult8(out,a,b);
parameter size=8;
input[size:1] a,b;
output[2*size:1] out;
assign out=a*b;
endmodule
请问还需要设置什么吗？时序和功能仿真都有错。