各位大神，请进来看看，急急急~~~

zhangsong123

              各位大神此设计有什么毛病吗，能麻烦你们帮我指出来吗？
  设计要求，40秒倒计时，9秒之后3秒一次的SOS警示，我调试之后蜂鸣器不响，怎么回事，跪求大神指教！！！！
module led_rxd(clk,rst_n,SOS_En_Sig,led,led_seg);
input clk,rst_n;
2 z! P2 y2 F  f/ x9 M% b" V5 @output [7:0]led;
output [5:0]led_seg;
output SOS_En_Sig;
parameter seg_num0=8'hc0,
; @: F3 l) |- ^6 v- z6 }$ ^          seg_num1=8'hf9,
6 \. y: M) _7 Z5 E. W/ S5 U: Z: [8 y    seg_num2=8'ha4,
    seg_num3=8'hb0,
    seg_num4=8'h99,
) ?0 e( M  C+ J& B3 p    seg_num5=8'h92,
    seg_num6=8'h82,
8 i9 F9 ]" a/ U2 W# u# [: ~    seg_num7=8'hf8,
    seg_num8=8'h80,
: l3 Z, ]; C" n# `. X, e) c- o    seg_num9=8'h90;
parameter seg_en0=6'b111110,
. ~9 {( S$ _3 z          seg_en1=6'b111101,
9 {/ X7 R, R' z; b6 S. v* `    seg_en2=6'b111011,
+ s! X) U# r9 h! ]* O2 |$ U    seg_en3=6'b110111,
    seg_en4=6'b101111,
3 n% Q: h2 k7 p: j, T. ]    seg_en5=6'b011111;
reg [26:0]count;
& ]# P6 d5 o! a: K6 Vreg [3:0] count1;
reg [3:0] count2;
; e# h& j/ {$ `: v% t% n; a( s) treg [7:0] led_reg;
/ [( h: P$ g3 p7 breg [5:0] led_seg_reg;
always@(posedge clk or negedge rst_n)
7 h& ?5 _/ _0 c2 W& \) Bif(!rst_n) count<=27'd0;
! `, x5 Q9 v  v: H+ ~else if(count==27'd49_999_999) count<=27'd0;
5 [+ G8 }6 I' U$ R# welse count<=count+1'b1;
0 s, X' r( u; U& s* m& Wwire clk_div=(count==27'd49_999_999);
# v7 i2 U. `8 c4 ^1 a/ V$ kalways@(posedge clk_div or negedge rst_n)
5 t9 \% q* ^" i! Fif(!rst_n)
begin
$ A# f+ e6 I6 I* H9 p7 k* |9 l/ v/ \' {2 icount1<=4'd0;
5 ~9 ]5 z' p% hcount2<=4'd4;
end
$ i+ f1 A; K! xelse if((count1==4'd0)&&(count2==4'd0))
# e: ?8 O7 t9 {- M6 Ibegin
1 m, U& \1 V$ a: b1 J+ z" Lcount1<=4'd0;
count2<=4'd4;
end
7 L. q- y% a& k1 N6 V  felse if(count1==4'd0)
, [1 `4 ?# r2 M  s: v4 j2 A7 Z; \begin
4 U  \) }, F7 D3 W; S+ ]1 [count2<= count2-1'b1;
: S# w  a' V' ]. Z" [6 D* F( ^( X$ D0 gcount1<=4'd9;
7 Q$ T7 y3 T$ n! E) dend
else count1<=count1-1'b1;
reg [26:0]count_1ms;//
6 f. o) q( G2 g. Y3 |9 zalways@(posedge clk or negedge rst_n)
if(!rst_n) count_1ms<=27'd0;  
else if(count_1ms==27'd49_999) count_1ms<=27'd0;
else count_1ms<=count_1ms+1'b1;
wire clk_dis=(count_1ms==27'd49_999);//
//
reg [1:0]state;
  ^2 C% H# u0 Z- h3 [always@(posedge clk_dis or negedge rst_n)
5 {* H! k; @' R& \7 a$ |if(!rst_n)
9 m5 w& c& f) L4 U( J9 t9 }begin
3 K; X4 V8 Q$ {" Z5 e: ~led_reg<=8'hff;
led_seg_reg<=6'b111111;
- x! {0 s4 T! C% |1 H7 c, L! rstate<=2'b00;
2 b1 W- g' L* j4 I9 oend
: ?9 N( E, u& }0 c0 O/ ~% H; P, C2 Oelse if(state==2'b00)
/ Z% y1 _- j% i6 _& g6 Dbegin
& G4 r+ z9 K5 x3 R7 {state<=2'b01;
led_seg_reg<=6'b111101;
case(count2)
, W/ V  D5 M/ `/ e4'd0: led_reg<=seg_num0;  
4'd1: led_reg<=seg_num1;  
2 J. B6 j, {+ B! o4'd2:led_reg<=seg_num2;
; n$ J  ^6 r8 k% y4'd3: led_reg<=seg_num3;  
4'd4: led_reg<=seg_num4;  
8 k! M: t' B0 C( ~- a4'd5: led_reg<=seg_num5;  
4'd6: led_reg<=seg_num6;  
4'd7: led_reg<=seg_num7;  
* V) {4 d) ~+ p4'd8: led_reg<=seg_num8;   
4'd9: led_reg<=seg_num9;  
default: led_reg<=seg_num0;  
endcase
end
else if(state==2'b01)
4 O: s* s: C" N/ w" v+ E/ Ybegin
state<=2'b00;
: d0 u# z/ ~5 h- I6 u# N9 tled_seg_reg<=6'b111110;
: O: s: Q- B! [" H0 z" gcase(count1)
4'd0:led_reg<=seg_num0;
4'd1:led_reg<=seg_num1;
4'd2:led_reg<=seg_num2;
4'd3:led_reg<=seg_num3;
4'd4:led_reg<=seg_num4;
0 R6 U& c! N  n2 P% s4'd5:led_reg<=seg_num5;
) [+ E# W1 S  f, e8 |( d4'd6:led_reg<=seg_num6;
0 Y% D* r  _+ k! |* E% J4'd7:led_reg<=seg_num7;
3 I: ~2 i& S! Z, i6 V4'd8:led_reg<=seg_num8;
4'd9:led_reg<=seg_num9;
default:led_reg<=seg_num0;
! i2 N3 E3 _4 G3 j! g; C0 ^0 u( aendcase
end
# ^: W/ q6 b* Wreg isEn;
reg [27:0]count3;
7 e- c5 ^4 s. o! ?9 L- M9 b. Ualways@(posedge clk or negedge rst_n)
if(!rst_n)
begin
0 [8 o; T# h+ RisEn<=1'b0;
* I9 m8 i2 p9 q6 G; |( @count3<=28'd0;
1 a, f( v+ s. c  X6 }' Uend
9 f/ @7 z+ A3 ^5 w5 ^3 gelse if((count2)&&(count3==28'd149_999_999))
begin
isEn<=1'b1;
: d! o+ f: P0 ^8 m2 X4 ^count3<=1'b0;
end
# ]8 n, [1 d; b4 jelse
0 B2 D/ G5 S  Z- r* dbegin
; _" f& t0 s: f' o$ k& MisEn<=1'b0;
0 |% X8 f8 C' `* ycount3<=count3+1'b1;
end
, D+ Z0 n( _" o/ b+ passign led=led_reg;
assign led_seg=led_seg_reg;
. ~, B' v, g- T- qassign SOS_En_Sig=isEn;
endmodule