各位大神，请进来看看，急急急~~~

zhangsong123

              各位大神此设计有什么毛病吗，能麻烦你们帮我指出来吗？
  设计要求，40秒倒计时，9秒之后3秒一次的SOS警示，我调试之后蜂鸣器不响，怎么回事，跪求大神指教！！！！
" m# e% B0 i" P8 s6 fmodule led_rxd(clk,rst_n,SOS_En_Sig,led,led_seg);
input clk,rst_n;
1 b8 i. r$ T8 d1 J, |: woutput [7:0]led;
output [5:0]led_seg;
/ a) E$ P/ O0 a: j' y8 p% j- soutput SOS_En_Sig;
parameter seg_num0=8'hc0,
          seg_num1=8'hf9,
, G6 s$ ^; ^, i2 j    seg_num2=8'ha4,
  o( d$ Z5 |1 }. n    seg_num3=8'hb0,
; h! N! p+ w. v" Y) e    seg_num4=8'h99,
    seg_num5=8'h92,
    seg_num6=8'h82,
    seg_num7=8'hf8,
    seg_num8=8'h80,
7 M1 X' r# i2 J    seg_num9=8'h90;
parameter seg_en0=6'b111110,
% @3 t6 e5 Q- a  ~          seg_en1=6'b111101,
    seg_en2=6'b111011,
% o; }& O$ P5 E6 c8 q4 H    seg_en3=6'b110111,
    seg_en4=6'b101111,
1 j6 s: |. p8 [; n    seg_en5=6'b011111;
7 _/ l; y. |+ freg [26:0]count;
  X6 F0 m* G6 r$ |reg [3:0] count1;
reg [3:0] count2;
8 u2 V  f1 S/ O- `8 Rreg [7:0] led_reg;
# L9 J% W* Z, Y' \& @4 creg [5:0] led_seg_reg;
always@(posedge clk or negedge rst_n)
if(!rst_n) count<=27'd0;
1 a9 x+ p: i" j( j3 f7 O4 celse if(count==27'd49_999_999) count<=27'd0;
else count<=count+1'b1;
8 A9 d- q. O0 a" a* \7 b/ P# Fwire clk_div=(count==27'd49_999_999);
9 b& Y$ N" s; |. @# x* u; [always@(posedge clk_div or negedge rst_n)
if(!rst_n)
0 C7 v0 w0 [% ?, b: A! Sbegin
count1<=4'd0;
count2<=4'd4;
0 u& Z; x/ j5 d1 l, [0 ~end
( b/ c* ~! O# J% Helse if((count1==4'd0)&&(count2==4'd0))
begin
count1<=4'd0;
4 }# b7 C: {2 o- x1 Lcount2<=4'd4;
' }% G6 F9 v9 U( a( n+ W! Gend
+ ?3 L7 ]3 g  }( Z: Jelse if(count1==4'd0)
begin
( b3 k# n2 Q3 n2 |count2<= count2-1'b1;
( ]+ i# i9 R' a& L/ |count1<=4'd9;
end
7 P1 c) O4 L2 t& c6 R2 A0 ielse count1<=count1-1'b1;
+ J8 w. ?1 ^% z! f! Rreg [26:0]count_1ms;//
7 x/ }+ }7 ]4 e' m( [$ L; A' talways@(posedge clk or negedge rst_n)
if(!rst_n) count_1ms<=27'd0;  
else if(count_1ms==27'd49_999) count_1ms<=27'd0;
else count_1ms<=count_1ms+1'b1;
wire clk_dis=(count_1ms==27'd49_999);//
//
reg [1:0]state;
5 h. ^, L0 ?: @5 ^4 y6 Ralways@(posedge clk_dis or negedge rst_n)
, `$ n% j/ w2 p; L- oif(!rst_n)
begin
' [, s+ J# x1 G. l( u+ Iled_reg<=8'hff;
led_seg_reg<=6'b111111;
state<=2'b00;
4 A7 t) q' s4 q2 S. Fend
, ?9 q+ A) ?  O( ]2 z+ V+ I6 N# Selse if(state==2'b00)
& M) H& _+ `' g( lbegin
; H/ s  c' s* B/ Estate<=2'b01;
$ l& Y3 e, Q: a- ~& D( fled_seg_reg<=6'b111101;
case(count2)
4'd0: led_reg<=seg_num0;  
4'd1: led_reg<=seg_num1;  
4'd2:led_reg<=seg_num2;
4'd3: led_reg<=seg_num3;  
4'd4: led_reg<=seg_num4;  
4'd5: led_reg<=seg_num5;  
4'd6: led_reg<=seg_num6;  
2 n# d! ~- J& V2 U! k4'd7: led_reg<=seg_num7;  
4'd8: led_reg<=seg_num8;   
4'd9: led_reg<=seg_num9;  
default: led_reg<=seg_num0;  
endcase
4 M; f% r. U* Lend
else if(state==2'b01)
begin
: d0 n( M! K0 \8 B. F5 {$ [8 tstate<=2'b00;
led_seg_reg<=6'b111110;
case(count1)
4'd0:led_reg<=seg_num0;
4'd1:led_reg<=seg_num1;
4'd2:led_reg<=seg_num2;
4'd3:led_reg<=seg_num3;
4'd4:led_reg<=seg_num4;
4'd5:led_reg<=seg_num5;
4'd6:led_reg<=seg_num6;
4'd7:led_reg<=seg_num7;
4'd8:led_reg<=seg_num8;
' q6 C6 h3 n& D; K, w4'd9:led_reg<=seg_num9;
+ G0 G1 }: f" R9 d3 gdefault:led_reg<=seg_num0;
/ C, Z0 {1 G! ]# m$ K" nendcase
: [6 q! b5 Z( m) G8 oend
- Q( d" R9 {4 d1 x% M. _reg isEn;
' d: U1 i! \9 s  k0 Creg [27:0]count3;
8 S0 t* F* S5 Malways@(posedge clk or negedge rst_n)
- I% C7 r7 k% {% V5 d  ~! Mif(!rst_n)
& j  L8 B6 a( ^1 c1 }: A7 B6 Vbegin
isEn<=1'b0;
count3<=28'd0;
end
- H! h' U+ k: {  L% telse if((count2)&&(count3==28'd149_999_999))
begin
$ q5 \3 r5 G( ^$ P6 ~+ fisEn<=1'b1;
count3<=1'b0;
, j$ Z3 t& v% j  ?& [end
else
+ W+ i5 w) E) X6 ~  R& o1 Ebegin
/ ^" r( z2 L, l) `9 nisEn<=1'b0;
$ _: O' S  J8 tcount3<=count3+1'b1;
0 K+ U1 N( f( E6 Q, w5 s: Lend
+ r+ E% Z4 E- ?& H# ?assign led=led_reg;
assign led_seg=led_seg_reg;
+ z1 g* r) f( N+ R# b. aassign SOS_En_Sig=isEn;
endmodule