|
|
EDA365欢迎您！
您需要 登录 才可以下载或查看，没有帐号？注册
x
本帖最后由 zgyzgy 于 2015-10-10 11:35 编辑 ! M R( f3 H! c6 }/ h* V* x; X
& X) u: z ]3 y! z) J. \# M8 k1 i
昨天刚出来的。。。。。。' m0 z: U a9 \+ M, Y0 f2 O7 M
. g& M" l; n6 L- q6 u' O. p
DATE: 09-31-2015 HOTFIX VERSION: 0597 C6 l( q( H2 S2 C
===================================================================================================================================2 N8 B# L3 h$ S+ ]0 }/ P. H
CCRID PRODUCT PRODUCTLEVEL2 TITLE* [( w( _7 r' N0 K
===================================================================================================================================: g1 [; o: r9 U: p& ^5 f# q
1181942 SIP_LAYOUT ASSY_RULE_CHECK ADRC reports different results from the spacing set-up
3 p$ M7 f1 n4 M2 H$ ~6 P7 L1328452 ALLEGRO_EDITOR INTERACTIV When changing the shape type, Right-click - Next does not work for subsequent changes
E4 u, x# F: n1441502 GRE IFP_INTERACTIVE Design partition cannot be imported.
; |, D; |6 |* y7 w. c" [5 Z/ x& X1457920 SIP_LAYOUT OTHER Wire Bond Import is not working correctly with discrete parts
3 i, u0 H- t9 k5 x6 x/ y, |9 }1464865 CONCEPT_HDL CONSTRAINT_MGR For identical nets, topology in DE-HDL CM is different from the topology in PCB Editor CM
1 n% U3 ?8 _ r1467365 ALLEGRO_EDITOR OTHER Cadence cshrc for LINUX has an extra space in it.
' \6 Q9 u* S. D' E/ v7 X1473744 ALLEGRO_EDITOR INTERACTIV The 'Chamfer' function does not work correctly if the second Trim Segment value is specified instead of the first.
: N$ U& _0 G5 j$ ]5 ^ B1475599 SIP_LAYOUT SYMB_EDIT_APPMOD Refresh co-design die of an enlarged die is not placed correctly
: w( n' \2 I! U2 ]; O5 F: t5 i1476284 CONSTRAINT_MGR OTHER Changes with Tpoint pairing not being propagated to the brd file
7 g, i6 k( e# `' \* v' ^9 I1476528 ORBITIO ALLEGRO_SIP_IF While translating a .mcm to OrbitIO, the error 'allegro2orbit.exe has stopped working' is thrown
4 J4 \9 ~6 L. X1476855 ALLEGRO_EDITOR DATABASE Trying to import Netlist, getting SPMHNI-194 error
7 i5 X, u( b5 V( N! n3 v' }1476920 CONCEPT_HDL OTHER Genview consistently fails in some indeterminant manner.+ I/ y1 x, ]7 m, g4 L) u
1478111 F2B DESIGNVARI Hierarchical block variant not shown in testcase with S57 although it was working with 2015 release
& b& V' l5 A9 G1 B1478225 SIP_LAYOUT DIE_EDITOR IOP incorrectly rotates pins at a co-design die
* g& `. Z% y8 K# { u& X6 J1478465 SIP_LAYOUT WIREBOND Ability to set default bond wire option to on for wirebond import/export commands
/ B/ i& S5 Q3 n+ K7 V3 s7 t1478994 SIP_LAYOUT SKILL axlUIMenuChange does not work on Linux
" @+ E+ P) t& |) p1479023 CONSTRAINT_MGR OTHER The cmDiff reports different data when files are reversed in UI
( ?0 }$ L' ~. q% ^; e% k1479785 ORBITIO ALLEGRO_SIP_IF brd file does not get loaded in OrbitIO& ?$ y: S% b$ {) r! x6 p8 D# q
1480367 SIG_INTEGRITY OTHER Differential pair extraction SKILL error, 'parseString: argument #1 should be either a string or a symbol'* b2 j% T/ C8 `4 ?
1480538 SIP_LAYOUT DIE_EDITOR CTE compensation is limited to 3 decimal places, can that be increased3 J$ c, m% y! u/ n5 F2 k
1481109 APD MANUFACTURING control Package Design Integrity for snapping the via to pin- Z7 X. I( }0 G" l. S
1482771 SIP_LAYOUT WIREBOND Fingers and wires cross when moving the guide path
( g2 `; |' _5 M8 ?
9 w9 t! C* _* e" [正在下载文件中，稍后分享链接。。。。。。2 C, B0 Q: a% `6 \1 R
6 s7 O* q& T, q- O1 Z1 n1 {8 z
6 V& L( I; y/ l1 d) j
8 E+ r" x) C7 w/ m" k" R7 ~6 A7 ]# I& D' C, S% K
9 n# W; V" t+ G% e. p1 N/ y3 U! l+ q7 l# J7 I7 q: U
* N( z' N! U1 U$ S: e0 o) ^ u& \$ @5 e7 \- V
" c6 t0 n0 e: |, @2 }: R$ y7 R
http://pan.baidu.com/s/1gdnouNx" y+ a! l2 r/ n7 k0 ~5 O3 H! `& J
1 _- Q5 _ A$ E0 S8 g$ S% Q* {
: F# ~, S8 I! z- f% d+ F: g
0 ~4 k# I' ^& O. }# z m! l
6 `3 G/ Z% A* Q, B0 n: E: Z7 T2 y# F+ a/ d6 M. G, n
" q- R. S& x5 l3 E! Q' J: h& H/ ^
|
评分
-
查看全部评分
|
/1 
发表于 2015-10-10 09:07
QQ好友和群
QQ空间
腾讯微博
腾讯朋友
微信
收藏
支持！
反对！
楼主
