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本帖最后由 streetflower 于 2014-11-14 17:14 编辑 4 R; j1 S$ d& ^, P! ]
9 q3 f" a m1 @1 \5 P5 O* i iCadence 16.6 Hotfix_SPB16.60.038
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http://pan.baidu.com/s/1gdCb4cV
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" w0 e }8 h, @; |% `# BDATE: 10-31-2014 HOTFIX VERSION: 038& j, Z5 Y# r: ~# @) N/ B
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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1103937 PCB_LIBRARIAN VERIFICATION con2con should not have any need for a graphical terminal( Y- M: `) U& B
1107843 FSP OTHER Support for lrf and lmf in archived project
" Q$ J7 F8 r: |, X1 e, j3 A1123765 CAPTURE GENERAL .OLBlck file not deleted if library is closed in Capture
7 W( H4 b8 |# {1 e1169740 FSP OTHER Ability to import "Assigned Pin" column to connect Generic connector and FPGA.
% [8 q8 Y! `: b6 L4 ]4 S1172641 FSP FPGA_SUPPORT Support for 5SGSMD5K2F40I2N device, m# n/ Y4 D- I6 D4 V$ t
1177760 CAPTURE OTHER IC pins cannot be cross probed from Capture to PCB Editor
1 o1 ~) H' a1 X1 S8 Y4 e1195672 ALLEGRO_EDITOR PLACEMENT Place replicate update should update component value text
; p/ y6 d, G2 J9 H f1206563 FSP GUI Spreadsheet import support for xc3s400afg400- l; h/ T2 A$ }" P6 V
1208169 FSP FPGA_SUPPORT New FPGA model request
* [! {& [0 r; H* J; g* S. G+ n+ B4 \1224428 ALLEGRO_EDITOR PLACEMENT Get message "W-(SPMHGE-579): Unable to complete path to circuit for all selections" when updating place replicate circuit
; ~1 r- R# J, m$ \# x1230064 ALLEGRO_EDITOR INTERACTIV Place replicate is trying to match dimensions/ ^$ L5 X2 l8 q+ y" _$ B# b$ m6 w N) U
1253986 CONCEPT_HDL CORE Not able to define Source when adding property to a selected group
9 h+ O8 L/ V3 C; A1266615 ADW SHOPINGCART Error(SPDWUB-48) while placing the part from the shopping cart
/ M0 F% n: h. d8 X( w$ U& m4 K+ w1269658 ALLEGRO_EDITOR EDIT_ETCH Ratsnest disappears near pin when routing
; H8 O/ m: A: C8 P( O, d+ y* k) I1270158 CONCEPT_HDL CONSTRAINT_MGR Orphan nets are visible in CM but not in DE-HDL0 o% U( \2 [ S2 E) i. L3 l( j
1275042 CONCEPT_HDL COMP_BROWSER Unit specifier 'HC' not found in UNITS environment while placing the part on schematic+ Z# Q+ y2 w- X, F
1276269 ALLEGRO_EDITOR TESTPREP On creating a fixture, a test point is generated but refs are not visible. 4 o) w- b' \2 [" j! }- n& F3 N
1278037 SIP_LAYOUT ASSY_RULE_CHECK DRC soldermask to finger check required for cases when the finger has no wire attached0 c7 u" l$ T- R+ M/ \/ w
1278475 ALLEGRO_EDITOR DATABASE Import Logic changes VIA net names to GND- d- y& l: D. F& W, s( X
1279162 SIP_LAYOUT DIE_ABSTRACT_IF Add codesign die should default shrink/scribe settings from die abstract if abstract contains this information.
x1 G0 z; ^5 u7 T" a' q1282358 SIP_LAYOUT OTHER Why are IC/PKG symbols always mirrored when placed on a sip design?
2 w ~( N& [, J; O2 T1283439 CAPTURE ANNOTATE Inter Sheet Refs placed on top of Off Page Connector name
6 @# O' I9 H9 p' `% m7 w1284809 ALLEGRO_EDITOR INTERACTIV Using the Fix icon in the toolbar will not apply the Fixed property to Groups) }2 J7 c# ?( X7 O4 r" R+ q
1286277 CAPTURE SCHEMATICS Capture crashes on adding Bezier curves
5 p* ?5 s2 g* F1286354 CONCEPT_HDL CORE The GENERATE_SCH_METADATA 'ON' directive causes significant DE-HDL performance degradation
* L* w; x3 l' E) I- q+ E1286617 CONCEPT_HDL CORE Generate View failure
7 W9 ^, j$ K, G4 r& J) W1 d1287020 CAPTURE OTHER Option to disable Autobackup
4 Y% P1 e- Y3 {$ P# R# W l+ R1287100 FSP DESIGN_SETTINGS FSP global edit of Capture library paths% ~: I, B0 S1 W) Q l
1287877 CONCEPT_HDL CHECKPLUS Graphic check in CheckPlus hangs with sch_something view+ o* d8 G3 |' `: j7 r' }7 e
1289056 ADW OTHER MKnet program to also read the alim.auto from ADW_CONF_ROOT
W5 ^) D) h. c$ G5 y1289107 CONCEPT_HDL CORE Find with Schematic Selection fails after clicking Find All three times4 Y* \9 r3 h/ h$ s/ u) @3 _* `! t8 G
1289175 CAPTURE OPTIONS Autobackup changes timestamp of each and every part in the library.; c, S+ z5 L F! O6 g0 ?
1289447 TDA CORE Undo Check-out removes new design data from local area
* ^& f {8 C, T8 S8 v8 r* r1289677 ALLEGRO_EDITOR SHAPE Complex shape filling fails without DRC' Z- ~' a* c) D8 R
1289755 ALLEGRO_EDITOR EDIT_ETCH Timing Vision Display error
; t1 ^4 A2 g$ H1289913 ALLEGRO_EDITOR EDIT_ETCH Enhance the fanout function to speed up the layout design in Allegro PCB Editor.
, r9 g& ^) b! H- U: Q; `1290136 ALLEGRO_EDITOR EDIT_ETCH Unable to connect IC pin to ground
$ H$ p: ?; D. S2 K2 A0 x C1290426 SIP_LAYOUT LOGIC Deleting a distributed codesign component from parts list does not remove the component information from the design database& I9 m+ N! D9 o( E1 F
1291888 ALLEGRO_EDITOR INTERACTIV Property DYN_DELETED_ISLAND is not added on all the voids created by Delete Island command4 b4 l5 ^3 K" a" {- l9 P3 i
1292206 ALLEGRO_EDITOR OTHER Allow netname to be visible for pin/cline when viewed in Allegro PDF Publisher z2 P; C; B; }3 Y7 X& }
1292234 APD SHAPE Shape does not Void around Clines and Vias due to some corruption! @4 h# N5 P, T! Z! M0 p' A; j
1292877 ALLEGRO_EDITOR DATABASE DB doctor fixed void boundary but deleted all boundary without detail information. ?; ]1 C' t7 ^8 h
1293041 ADW COMPONENT_BROWSE Component Browser does not show results if you filter on the PPL and an additional column
9 p2 X9 r1 x+ f3 X- B" n1293188 ALLEGRO_EDITOR EDIT_ETCH fanout function(via in pad) deleted the cline & thermal
. A2 r2 n' \2 S) q/ w" C8 r1293626 CONCEPT_HDL CORE Delete Page command could not delete the dependency file (page2.csd).$ ?, a/ f% T7 |; x) a; x# ^
1293710 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes during copy fanout
! u2 {1 `6 N+ D% I2 R/ k% `1294355 PSPICE SIMULATOR Function "ddt( )" behavior in DC sweep analysis# c# f: V {! p3 P: s2 h+ f
1295232 CAPTURE SCHEMATIC_EDITOR Remove from group changes not reflected consistently in Part Manager- l1 p0 q- p% D. ^) B
1295434 ALLEGRO_EDITOR INTERACTIV Enable Pin Name to be imported into a .BRD and display this in the show info output as done in APD and SIP! d% l5 Z; q9 A; z7 @4 r v( ?7 n
1296583 ALLEGRO_EDITOR FSP_PINSWAP Crash for FSP Auto Pinswap with PCB Editor- o) b6 G' e1 u, R$ A3 E# z- H% _
1297095 ADW LRM LRM replaces incorrect part in schematic.
% w4 d) W# b+ x: P% ~1297685 F2B DESIGNVARI 'Could not open xmodules.dat file' Error during 'Save'.: Y y* }3 f. W. t9 H, Q" e
1297835 ALLEGRO_EDITOR INTERACTIV DFA-Driven Interactive Placement not working correctly for components on bottom side
) c3 s w5 w) |8 b1297870 SIP_LAYOUT ASSY_RULE_CHECK Wire to Wire Optical short ADRC reports wrong DRC violation$ [! z M5 i8 J) A% K+ a
1297994 ALLEGRO_EDITOR INTERACTIV When moving a via and splitting the stack, the via moves off the design work surface.) Y1 _4 i; b0 o
1298129 ALLEGRO_EDITOR EDIT_ETCH Auto Interactive Phase tuning should have option to Allow DRCs& u2 S0 U2 [6 i
1299050 ADW PCBCACHE Need a way to turn off all project ptf file backup files under flatlib
9 c$ Z4 S+ M" f. b% C% ?) z2 s* B( T2 X1299873 CONCEPT_HDL CORE DE-HDL window size and position is not saved on exit& ~ }# S" f9 O- X, v! a
1300101 ALLEGRO_EDITOR GRAPHICS Inconsistency in symbol editor and PCB Editor while showing 3D view5 s' t" ]0 {0 F/ j3 J0 _
1300557 ALLEGRO_EDITOR EDIT_ETCH Move Component with "Slide Etch" or "Stretch Etch" removes DYN_CLEARANCE_OVERSIZE from clines3 c! G# Y5 x$ K; m/ g# `
1300806 ALLEGRO_EDITOR GRAPHICS Stroke command in 16.6 works differently as compared with earlier versions- V) h% V u8 Q. M5 w
1302103 CONCEPT_HDL CONSTRAINT_MGR DE-HDL CM startup time on large hierarchical is extremely large(6-8 min)
- S! Q; P: X8 T/ g( ?0 p N' L1302939 ALLEGRO_EDITOR PARTITION Place replicate modules lost with design partition4 n d& l5 A9 A5 b% R
1303078 CAPTURE STABILITY Capture crashes on View -- Status Bar with no design open& R. A! H h2 s6 V
1303106 ALLEGRO_EDITOR SKILL Creating shape with SKILL script does not work on SPB16.5 and SPB16.6.
( S$ v9 q) ]( ~+ R) k0 I1303442 ALLEGRO_EDITOR EDIT_ETCH auto-interactive convert corner function crashes PCB Editor: o. ^, ^* T" G5 t i0 h
1303921 ADW COMPONENT_BROWSE Datasheets with spaces are not viewable in component browser( Q) O- w. L4 l- z7 i" O
1304042 APD LOGIC ERROR(SPMHUT-43):netin command is not working for .mcm." t% F7 ]1 i: o9 b
1304725 ALLEGRO_EDITOR INTERACTIV Value 0 in Allegro Text Setup not valid anymore
! P* Y1 G9 W7 H+ L8 m1304734 ALLEGRO_EDITOR PADS_IN PADS_IN does not follow the settings in the options file
2 T# }& P" i- S0 W1304882 CONCEPT_HDL CORE Hierarchy Viewer jumps up to the top on File Save8 T2 ~5 z- `, O: V. F+ Y
1305147 ALLEGRO_EDITOR MANUFACT Auto silk result is unstable.& @) N0 f( ^: `/ \0 t. C8 ~% u# i
1306323 ALLEGRO_EDITOR INTERACTIV Mirror command does not seem to work correctly.. ]( c2 \# R; a* `" R# v
1306468 ALLEGRO_EDITOR DATABASE Dbdoctor Crash
1 v8 c8 H* o J( b+ M1307277 SIP_LAYOUT IMPORT_DATA Wants BGA Text-In Wizard to maintain Pad layer set in the text file instead of defaulting to Bottom layer.2 `1 E$ H m5 R5 B E, w
1307367 FSP FPGA_SUPPORT FSP user needs 5SGSMD5K3F40I3N/5SGSED6K3F40I3N in FPGA models.& M+ |* z8 R1 t( [
1307478 ALLEGRO_EDITOR MENTOR unable to do PADS Library translation. T) `6 W: H5 \" ?0 C
1307626 ALLEGRO_EDITOR INTERACTIV Pick window is different for command and from GUI$ S6 B9 M) P3 }* u' x( V! W
1307785 ASI_PI GUI Decap Configuration GUI does not update until you deselect then select GND& d( a& D4 d6 R$ X' C# i7 | C
1308163 SIP_LAYOUT ORBITIO_IF Importing OrbitIO with multiple packages and XDA file into SIP layout results in incomplete data* z3 ] K; t. E4 i' W0 \% U! d
1308289 SIP_LAYOUT ORBITIO_IF Import OrbitIO into existing SIP database fails. Testing an ECO type of design flow
" y2 O5 A1 X7 r0 ^5 `, c1309315 CAPTURE ANNOTATE Incremental annotation is not giving correct refdes in case of attached complex hierarchical design1 i7 Z* s5 }+ m
1310614 CONCEPT_HDL CORE Part Manager creates bogus directory on linux system& k. L% _4 Q! ]$ U) [
1311184 CAPTURE NETLIST_ALLEGRO Incorrect warning for DEVICE property value in netlisting.+ Q- \6 ~9 |- _4 J) J7 O ?% }4 D
1311719 ALLEGRO_EDITOR INTERACTIV Allegro Component will not place on the canvas
7 X& r* ^+ C" ~$ ^1311757 CONCEPT_HDL CORE Cannot change a property from instance level to non-instance level1 }, a* A5 a, m$ B9 S) L
1311848 CONSTRAINT_MGR OTHER PFE is adding a capacitor after creating PI CSet
6 B( C# [( ^& @" {4 t1312553 CONCEPT_HDL CORE Customer could not add their net property after deleting it./ e. t1 m: \0 f( d+ S
1313068 APD DIE_ESCAPE die escape gen: Cannot route from pad of Via Structure.$ H2 N# i$ F1 e) Z
1313239 CONSTRAINT_MGR CONCEPT_HDL Diff pair constraints disappear if xnet is created for them in Editor
: t9 {) S$ H. P3 G" m2 c1313850 ALLEGRO_EDITOR PLACEMENT Place Replicate ignores fillet at pins
5 w. Z+ t7 p0 g! F1 y* ?- T1314207 ALLEGRO_EDITOR OTHER PCB Editor crash when rotating IPF data# k( D+ g2 y& b- f5 v3 m, z$ d
1314467 ALLEGRO_EDITOR INTERACTIV With high_speed option selected, PCB Editor crashes on move operation! e" I7 e2 E5 E2 u
1314921 ALLEGRO_EDITOR PLACEMENT RATS are wrongly displayed.
+ K$ x. {) i9 G3 J' ^5 `0 V- `( D1314973 CAPTURE OTHER Cannot cross-probe all pins from Capture
8 d' I5 P( s2 q# r& u* l1 z1316295 ALLEGRO_EDITOR OTHER .brd extension is removed after running DB Doctor from PCB Editor Utilities./ u; i3 c: u4 P& n
1316757 ALLEGRO_EDITOR DRC_CONSTR Spacing constraint error on negative layer
8 X0 d7 H& f3 Z1316959 ALLEGRO_EDITOR PARTITION Exported soft boundary partition2 symbol still cannot move out of partition boundary
! ^& [7 f. P& G5 v3 S+ x- @1317157 SIP_LAYOUT DIE_STACK_EDITOR After moving the Dies to different layers a Wirebond has changed the connection from the pin to a shape.
7 E) A1 y/ l6 D. ]* x- M7 p1317480 ALLEGRO_EDITOR SYMBOL Allegro DB check "SPMHA1-247 Illegal mirror error"
! h- O5 t+ L, Q$ u$ e/ m- B1317614 ADW COMPONENT_BROWSE Datasheet_Url is not opening the file browser correctly
- C6 |: \; K0 m7 p1317876 APD COLOR APD crashes when executing Color Dialog for Nets
2 ]: g5 D+ {' h" D; g$ C8 v+ r) K1320028 FSP DE-HDL_SCHEMATIC Error (10002: Cannot find a ppt part that matches the instance properties
* W9 z; p; f8 K q) M. x6 W: h1320438 ALLEGRO_EDITOR GRAPHICS Could not save DFA spreadsheet
" T( S: E: q5 K/ @1322600 CONCEPT_HDL CONSTRAINT_MGR Cannot extract xnet topology due to missing model even if the model is present
; W0 j# \3 C# q6 K% v, L, y1323327 CONCEPT_HDL CONSTRAINT_MGR Deleting Ref Electrical CSet from Diff Pair removes it from a Matched Group in DE-HDL
/ c8 G" [4 B& a, q* t8 r9 W1325230 CONCEPT_HDL CORE DE-HDL crashes once the design is loaded.; z3 S* f- [4 |2 w7 S5 C( `3 r
1325644 F2B PACKAGERXL CDS_LOCATION/$PN not deleted from property file(dcf) backannotation warnings5 e8 c: p8 m& g
1325905 CONCEPT_HDL CORE Schematic page import causes re-sectioning of the pins.; A/ `9 H+ y' I
1326163 SIP_LAYOUT OTHER SiP Layout - Void Adjacent Layer - Include option to ignore same net object when voiding
L# I! n4 [, w9 B- d& x2 L) t1326696 CONCEPT_HDL CORE Cannot get concepthdl -product to invoke with the high speed already available; b! v+ F1 m5 u9 T' x- W; O
1327367 CONCEPT_HDL CORE Crash when saving after adding block pin0 {7 V" I3 q2 ~+ k6 a t
1327569 ADW LRM LRM does not update the headers if the part number is also changed
. B& y$ }$ g' I0 e9 P( d ^1329271 ALLEGRO_EDITOR DRC_CONSTR Multithreading DRC check is flagging a DRC on the TOP Layer for Route Keepout that has the property ?SHAPES_ALLOWED? ON.
q, x5 h5 n8 k! I1329587 CONCEPT_HDL CORE Using the GROUP command does NOT place all objects in the group back on grid; ?' W6 P( t9 j/ c5 E4 u
1330913 CONCEPT_HDL COMP_BROWSER Empty value in PTF file
- t5 p0 Z3 s! v; S4 H1332728 SIG_INTEGRITY OTHER Signal model assignment form returning SYNTAX ERROR on Linux 5.0 5.7 and 5.9 with hotfix s036 and s037.' G- ?9 m! F5 J; }& W7 u* @- H; X
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发表于 2014-11-14 17:14
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