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ddr3 的时序训练过程：
6 N2 C8 {7 T$ _: b$ kmemory training过程如下
- f6 L- C r% [ L1 Pre-training init: DDR3 Reset and Initialization Procedure (per JEDEC spec)
6 y5 I# ^- G P* s# R5 ? V2 Receiver Enable Fine - Align DQS receiver enable signal to center of read DQS preamble at the DDRIO and set the MC round trip latency register. This training step is further broken into two substeps: RCVEN fine and RCVEN coarse training.
+ W. Z* C# w9 K3 Read DQ/DQS – Aligns DQ and DQS signals returned from DDR
: L6 o6 X' p. O7 m4 Write Leveling - Aligns write DQS to CLK at the DRAM / E j, t: s2 S/ v9 Q
5 Write DQ/DQS - Center aligns DQ to DQS at the DRAM M2 I4 B- U) V( i5 ?$ c6 P
6 Fly-by (Write Leveling Coarse) - Adjusts write DQ/DQS latency
- T) t. r9 E1 a7 Command-Clock Training - Centers the rising clock edge within the Command eye. This step uses both a simple 1010 pattern, and a more advanced LFSR address pattern for training.
+ v1 n1 r; j, ?' I# Z3 w8 Advanced Strobe Centering – Uses LFSR victim-aggressor patterns on the DQ bus in order to place the strobe timings such that both timing margin and voltage margin are maximized.
/ Y8 Y0 c% P% z* O( J8 {1 k9 Post-training init. (i.e. set the MC to normal mode from IOSAV mode)
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楼主: icy88
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发表于 2012-6-25 17:51
