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DATE: 04-23-2010 HOTFIX VERSION: 007
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721859 ALLEGRO_EDITOR OTHER update shape to smooth creates tmp file on remote file server working dir why?, z7 I6 ^! c2 `7 X9 K6 s5 h
740201 SPECCTRA_MENT_ IMPORT Wrong stackup order after translating from mbs2sp7 r2 |4 q8 k" i s, Q, C. r' U
744797 SIP_LAYOUT OTHER Cannot Copy a connector (IO) symbol in APD and SiP tools
$ G n- b5 w' W: }+ q& k747831 CIS CONFIGURATION There is a delay of 5 to 10 mins in opening SQL database in V16.2 and V16.3. It is fine in V16.0.
$ I9 `1 v% l9 p747848 CIS CONFIGURATION Unable to configure CIS with Oracle database due to Capture crash.% ^! K: z) |/ R* \1 V8 g9 \
751372 CAPTURE OTHER Copy / Paste Issue in capture 16.3
9 k5 B9 j+ j5 i' m/ }$ q$ d9 H757434 ALLEGRO_EDITOR MODULES Allegro hangs the board file after creating Placement Replicate circuit.
* ^7 p( P+ N; J$ ]! ?759906 CIS PART_MANAGER Property copy from one to several parts doesn't work, i5 L, f( e6 a3 |
760154 PSPICE NETLISTER Model parameter (Tj) is not affecting Smoke Analysis result
3 L) H0 ?& t8 R& J! U9 p0 e761177 CIS OTHER Error Message - Memory exhausted
5 E) n% Q& H2 b9 W- a762602 CIS EXPLORE_DATABASE CIS doesn't open datasheet for parts if it is not stored at default Capture location.
% Z( Q3 Y+ T+ f( U4 ?3 C" O763677 APD EDIT_ETCH The "Via to Via Line Fattening" tool is inconsistent in which clines are changed.+ I& D; ?$ l2 X/ m1 `& d
763715 CAPTURE NETLIST_OTHER A long pin name gets truncated upto 31 characters when the wirelist is created.! H8 x/ {% G4 L" Z! @ k* m1 Q) j, }
763878 CONSTRAINT_MGR DATABASE Why Pinpairs disappear after closing Constraint Manager?9 l4 l+ f) l+ G* W+ j, H
764020 CAPTURE NETLISTS Usernetl.dll has changed between 16.2 and 16.3 H# N8 [; n1 X! @$ j! A9 D
764101 APD EDIT_ETCH Perpendicular routing through a Region does not work when the region segment is drawn at an angle.& A! o2 ?; t6 U
764200 ALLEGRO_EDITOR DRC_CONSTR Via at smd fit drc on a via that is placed fully inside the padstack having custom pad
; a. Q3 P4 Z+ |. c6 ^) C1 U764903 PSPICE ENVIRONMENT 'Run in Resume Mode' does not work in SPB 16.3
. s3 Q1 J [8 v% O; a9 C7 u765206 F2B PACKAGERXL Unable to feedback subsequent pin swaps from Allegro2 p T5 u# ?% C/ K! ^$ r! _- x
765319 APD DRC_CONSTRAINTS Identical Constraints in Performance Advisor question- c p+ |- g0 p4 B
765541 SIP_LAYOUT SHAPE Set via oversize value to 3 in dynamic shape instance parameters will make overlap shape.$ _2 o$ V* W$ K2 U9 w0 Z3 ~
766147 APD EDIT_ETCH Resize/Respace Diff Pairs does not work on 45 and off angle4 n7 v, T0 ^+ ~0 O
766337 SIG_INTEGRITY GEOMETRY_EXTRACT Geometry of Via model Extracted from board file is not identical to Original Via geometry design
3 p! D7 Z- G3 {! P- h* I0 m766443 ALLEGRO_EDITOR PADS_IN unable to translate PADS ascii to brd in 16.3
* ]1 {) v% V% D: s766581 CIS CONFIGURATION In 16.3 capture.exe remains memory-resident after exit) G# b( ? g" K
767161 ALLEGRO_EDITOR SHAPE The behavior of Add Fillet command is different by Hotfix version.
" X m6 s3 F f1 j$ O767217 SIP_LAYOUT IMPORT_DATA The Die-Text In wizard and it is crashing on the "Finish" step.
( R( J) r! X* C, J* |767598 SIP_LAYOUT WIREBOND Can't wirebond SIP designs as it just hangs.+ z- y0 |7 t: [( t) j: J. u
767832 ALLEGRO_EDITOR DRC_CONSTR Reducing Design Accuracy updates Physical Diffpair constraints wrongly- v7 m, D) Z0 V6 `% W* c
768822 ALLEGRO_EDITOR SKILL axlSetParam return value is divided by 10 to the power of the design accuracy.% U' N4 f$ N7 G) Z" N
769150 CIS PART_MANAGER Update All part Status on a group changes 揇o Not Stuff?status to 揝tuffed?in V61.3_ISR_5.
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楼主: Lot
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发表于 2010-4-20 19:50
