pcie AC耦合电容放置位置请教

超級狗

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( _6 i% c4 [; U3 t$ T9 q5 R樓主的洋文兒還不錯吧？

4 P" S' j  ~) E/ K$ S- g8 C有個洋人在花旗國網站上，問了同樣的問題。

結果………

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Where should I put AC coupled capacitors?

# I- {" d* d* y8 f8 S/ J4 a6 j$ JThe coupling capacitors are usually placed close tothe transmitter source.
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Going along with Dr. Johnson, we need to figure out the distance. The propagation velocity of signals on most FR4 types of board isabout c/2. This equates to around 170ps per inch for internal layers and morelike 160 ps per inch for external layers.
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Using a standard interface running at 2.5Gb/sec, the unit interval is 400ps, so according to that, we should be much less than 200ps away from the transmitter. If this interface has been implemented in an IC,then you need to remember that the bond wires are part of this distance. Belowis a slightly more in-depth look at the issue.
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In practice, coupling devices are placed as close as possible to the transmitter device. This location naturally varies depending onthe device.
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: k7 e% [! |+ t3 E- D3 ^% J" WNow the capacitors. This is an RLC device at these speeds, and most devices are well above self-resonance in multi-gigabit applications. This means you may well have a significant impedance that ishigher than the transmission line.

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- B" k5 j  n. O) ]For reference, the self inductance for a few devicesizes: 0402 ~ 0.7nH 0603 ~ 0.9nH 0805 ~ 1.2nH


) F. y* ^* u, T; E" jTo get around high impedance device problems (a majorissue in PCI express due to the nature of link training), we sometimes useso-called reverse geometry devices because the self inductance of the parts issignificantly lower. Reverse geometry is just what it says: An 0402 device hasthe contacts 04 apart, where an 0204 device uses the 02 as the distance betweenthe contacts. An 0204 part has a typical self inductance value of 0.3nH, significantly reducing the effective impedance of the device.


Now to that discontinuity: it will produce reflections. The further away that reflection, the larger the impact on thesource (and energy loss, see below) within the distance range of 1/2 of the transition time of the signal; beyond that makes little difference.

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& P' [+ S# T- ?" ~% ^At a distance of 1/2 the transition time or furtherfrom the source, the reflection can be calculated using the reflection coefficient equation ([Zl - Zs]/[Zl + Zs]). If the reflection is generated closer such that the effective reflection is lower than this, we have effectively reduced the reflection coefficient and reduced lost energy. Thecloser any known reflection may be situated with respect to the transmitter,the less effect on the system it will have. This is the reason that break-outvias under BGA devices with high speed interfaces is done as close to the ballas possible. It is all about reducing the effect of reflections.

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  U7 W' z( N, W$ ^As an example, if I place the coupling capacitor (forthe 2.5Gb/sec link) at 0.1 inch from the source, then the distance equates to a time of 17ps. As the transition time of these signals is usually limited to no faster than 100 picoseconds, the reflection coefficient is therefore 17%. Note that this transition time equates to 5GHz signaling artifacts. If we place thedevice further away (beyond the transition time / 2 limit), and use the typical values for 0402 100nH, we have Z(cap) = 22 ohms, Z(track) about 50 ohms, and wetherefore have a reflection coefficient of about 40%. The actual reflection will be worse due to the device pads.

xiaoyu19890210

超級狗 发表于 2016-3-10 21:20
& p4 U. U& `: CPCIe Return Loss

. U) d: Y& C! M5 y4 D- v: n0 n: X狗版主啊，这个和您之前说的信号反射、相位啥的有啥关系吗？？？
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* f* z" b& O2 x' z3 \+ YPS：要是不爽了就当没看到，，，求别埋。。。拜谢。。。

xiaoyu19890210

超級狗 发表于 2016-3-10 21:26
* K' p1 t! u, J0 T樓主的洋文兒還不錯吧？
3 F4 ^0 B. I1 K
/ g2 T5 a* d$ @有個洋人在花旗國網站上，問了同樣的問題。

sorry，这么大段，才看到。。。
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xiaoyu19890210

超級狗 发表于 2016-3-10 21:26
樓主的洋文兒還不錯吧？

  R0 Y! r- L! o+ r3 V6 M有個洋人在花旗國網站上，問了同樣的問題。

- `, M/ _* }: n8 {' m1 a" v8 K狗版主，看了这么大段，彻底惊呆了，，，实在不能狗同啊。。。
' g8 q  w/ L' n1 bAs the transition time of these signals is usually limited to nofaster than 100 picoseconds, the reflection coefficient is therefore 17%，，，这怎么得出来了

荒村战士

超級狗 发表于 2016-3-10 21:26
樓主的洋文兒還不錯吧？
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6 q3 _- b  y9 a0 Q' a7 L) y. R有個洋人在花旗國網站上，問了同樣的問題。

我也请教个问题，PCIE gen1,2的AC耦合电容值推荐为0.1uf,而PCIE3.0以后推荐的AC耦合电容为0.22uf，有如下问题，期待大神解答：
问题1：Gen1,2的速率比Gen3低，为啥耦合电容Gen3的要大呢？电容越大，边沿会越缓，个人理解。
问题2：Gen3向后兼容Gen1,2，那当用0.22uf的耦合电容时，在Gen3的链路上跑Gen1,2，是不是就不符合规范推荐的AC耦合电容值啦？
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超級狗

问题 1：Gen1,2 的速率比 Gen3 低，为啥耦合电容 Gen3 的要大呢？电容越大，边沿会越缓，个人理解。
電容並聯l落地（GND），充放電效應的確會造成此結果，但 AC 耦合電容式串接在訊號線上。

" c& z4 c% T. {7 X; O问题 2：Gen3 后兼容 Gen1,2，那当用 0.22uF 的耦合电容时，在 Gen3 的链路上跑 Gen1,2，是不是就不符合规范推荐的 AC 耦合电容值啦？
根據容抗計算公式 Xc = 1 / jwC，電容越大容抗越小。高頻減少一些容抗，讓相差、衰減及反射都小一些，似乎也沒什麼不對。

僅為小弟淺見！

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diff

听说是有座子就在连接器，没有在tx段