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本帖最后由 紫菁 于 2017-9-14 11:21 编辑
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$ v/ s2 j* [$ t0 _4 v+ z) u下面链接是Cadence SPB16.3及最新Hotfix下载地址，需要的可以下载！
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% H0 W! Q1 ~/ m6 BHotfix057更新的内容如下所示：- ^0 _% d2 S( N
DATE: 12-19-2012 HOTFIX VERSION: 057
y2 s2 O6 J0 |! O===================================================================================================================================
6 v3 F$ A! m3 `CCRID PRODUCT PRODUCTLEVEL2 TITLE
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1080193 SIG_INTEGRITY ASSIGN_TOPOLOGY View Topology freeze during the extraction of the net connected to resistor network.
9 |7 y4 |5 L, C$ J$ e4 c1082509 ALLEGRO_EDITOR INTERFACES Export DXF in the 16.3 S056 roatate some pins.
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DATE: 12-7-2012 HOTFIX VERSION: 056
+ }7 n3 g5 O( R% Y' J8 p/ x===================================================================================================================================: V7 }2 o3 z+ ~# Q: z. G( I
CCRID PRODUCT PRODUCTLEVEL2 TITLE
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825813 CONCEPT_HDL CORE HDL crashes when copying a property from one H block to other
9 D4 d! t# u( p: T* ~" e8 i871886 CONCEPT_HDL CORE Browse button in Signal Integrity window of DE-HDL option causes program crash/ R. ]. T# r5 ^* r9 a# X
871899 CONCEPT_HDL CORE 'Multiple:' column of Grid window in DE-HDL option is too wide
5 Q7 X. [* r: A, ?! y873917 CONCEPT_HDL CORE Markers dialog is not refreshed. {2 z; K' u! i9 j4 {1 S
887887 CONCEPT_HDL CORE Option to find unconnected Pins/Nets with DEHDL L License
5 S7 ^1 M; K& v* S. U* j892857 CONCEPT_HDL CORE packager treats R? as a unique reference designator
9 g% M* d8 G! _! Y; S1075587 CONCEPT_HDL PAGE_MGMT Unable to insert page in schematic0 N o! c7 m! s
1078682 ALLEGRO_EDITOR DRC_CONSTR Unaccetable slowness with Slide |
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发表于 2013-1-14 11:49
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