焊盘知识！

cffdfg45

請問有誰知道PCB007樓主發的那張圖最上面黃色圓圈是甚麼?
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PlayEDA

這樣一篇好文章，一定要推薦一下的，謝謝樓主

hustyangjun

主要还是为了过锡时散热均匀

pcb007

我也来贴个图：
# J+ e7 H4 k- E- F! x; a3 }' OLayer Structure of a Padstack


Solder Mask  - A green layer of Solder Resist is coated on the external layers of a PCB to prevent the copper from oxidizing when exposed to air for a long period of time. The Solder Mask is the opening that exposes the Pad for Soldering, preventing the solder from flooding the adjoining copper.
( @: L; W% @' B7 i; w. j3 a Pad - Through Hole Pad has large hole and is used for mounting and soldering Leaded Components to the board. Via pad is usually smaller as it is only used for inter-layer connection. Surface Mount Devices, the pad does not have a hole in it.  
Solder Paste Mask - Solder Paste are used only on Surface Mount Devices, the paste is made up of tin and silver alloy which is printed on Component Pads by pressing it over the Solder     Paste Mask. It melts into liquid form when passing through a Reflow Machine and solidifies as it cools attaching the pins of the component on to the pads.
3 }0 j) a9 @- c2 v6 H$ C" }Plated Through  - The Plated Through Hole is used for inter-layer connections, linking the electrical  Hole  signals from one layer to another by plating the walls of the hole with metallic alloy. The Through Hole Pads and Vias in multiple layer designs have plated through holes. The plating also serves to improve mounting strength for Leaded Component.  
Relief Connection - To prevent the heat from leaking too fast from the pad to the plane, creating Cold Joints, Air Gaps are introduced. The resulting Relief Connections are used for connecting the copper plane to the pad or via having the same Net.   Plane Clearance - As a Plane is almost all copper, any Via or Through Hole Pad introduced that belongs to a different Net will certainly be shorted to it. To prevent this, an Anti-Pad or a cut out must be made to allow clearance for the hole to go through without touching any part of the Plane.

tianhao

一步到位！！！

superlish

顶！没啥好说的！

309007

顶l

coco

俺也顶一下,因为焊盘描述的太形象啦!

droden

好帖！！太形象生动了，我一直都在琢磨这个问题

killerljj

good！
以上两位老兄能否提供下资料来源以供兄弟们参考？
. N5 x. G4 a' p6 B, K8 t谢谢！！！！

4 k! _' M) [/ w[ 本帖最后由 killerljj 于 2007-11-21 20:55 编辑 ]

killerljj

偶也跟一贴！
以下内容来自《high speed digital system design》。

A via is a small hole drilled through a PCB that is used to make connections between various
layers of the PCB or to connect components to traces. It consists of the barrel, the pad, and
" z- v- W3 V5 L$ s' Pthe antipad. The barrel is a conductive material that fills the hole to allow an electrical
connection between layers, the pad is used to connect the barrel to the component or trace,
and the antipad is a clearance hole between the pad and the metal on a layer to which no
/ i) o( `- Y* Q1 Oconnection is required. The most common type of via is called a through-hole via because it
is made by drilling a hole through the board, filling it with solder, and making connections on
appropriate layers via the pad. Other, less common types of vias, used primarily in multichip
  @9 p& O5 k) s( V) T$ zmodules (MCMs) and advanced PCBs, are blind, buried, and micro-vias. Figure 5.1 depicts
a typical through-hole via and its equivalent circuit. Notice that the pads used to connect the
  Y4 J9 T% b) o( F1 E; r- ?8 _8 l( c: rtraces on layers 1 and 2 make contact with the barrel and that there is no connection on
# F# t7 [8 c1 A8 h8 \layer 3. Blind and buried vias have a slightly different construction. Since through-hole vias
/ q" `8 w& |% k2 e- Dare by far the most common used in industry, they are the focus of this discussion.

0 @* T. H, [4 g# s9 y' sNotice that the via model is simply a pi network. The capacitors represent the via pad
  l( Q; D3 K- h: u/ M$ Kcapacitance on layers 1 and 2. The series inductance represents the barrel. Since the via
5 _, J& h3 }' F+ P& ?. |  A2 ~9 u; sstructures are so small, they can be modeled as lumped elements. This assumption, of
course, will break down when the delay of the via is larger than one-tenth of the edge rate.
9 e  l. L% W# CThe main effect that via capacitance has on a signal is that it will slow down the signal edge
; I5 i" S  I& @8 arate, especially after several transitions. The amount that the signal edge rate will be slowed
can be estimated by examining the degradation of a signal transmitted through a capacitive
- p8 K' ~) h5 u2 R9 R& L4 A) u* vload, as shown later in this chapter in equation (5.21). Furthermore, if several consecutive
vias are placed in close proximity to one another, it will lower the effective characteristic
; i) ~; ?) W  ?5 K! \+ }impedance, as explained in Section 5.3.3. The approximate value of the pad capacitance is
& \( m% m) F! I4 M1 ~[Johnson and Graham, 1993]

% ?& [+ {; S1 M! |$ V2 S4 Y; S: K" c8 D[ 本帖最后由 killerljj 于 2007-11-21 20:51 编辑 ]

admin

这下完美了，连计算都给出来了，主题可以改成史上最全焊盘介绍了！

surz168

{96FC0D4C-0660-4EAF-997D-86052CF147EC}.gif (30.82 KB)
2007-11-12 11:07

7 ?1 q' r: Q2 `& t1 ?好贴，支持！

forevercgh

受教了

tianhao

我刚看见一个这样的孔,,不知道设成这样的原因,,借个地儿请教一下


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原文地址:
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https://www.eda365.com/thread-1010-1-1.html