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偶也跟一贴！3 Y8 p1 o. Z( O; ?, y
以下内容来自《high speed digital system design》。
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A via is a small hole drilled through a PCB that is used to make connections between various3 X0 u7 g ~- G: V# D
layers of the PCB or to connect components to traces. It consists of the barrel, the pad, and" L1 U& ~& b% b5 D- \
the antipad. The barrel is a conductive material that fills the hole to allow an electrical; A! A1 z- r1 E
connection between layers, the pad is used to connect the barrel to the component or trace,
2 H% R3 r: A' K& B- _; r* sand the antipad is a clearance hole between the pad and the metal on a layer to which no
3 [0 e0 ~/ ]4 }! J7 Qconnection is required. The most common type of via is called a through-hole via because it U& ^) V# b/ X: n
is made by drilling a hole through the board, filling it with solder, and making connections on
( Z4 S8 t* {# P& ^8 @+ _appropriate layers via the pad. Other, less common types of vias, used primarily in multichip4 r+ d+ E5 [9 C: T+ X8 l
modules (MCMs) and advanced PCBs, are blind, buried, and micro-vias. Figure 5.1 depicts' g, g6 B+ M. V! |- o
a typical through-hole via and its equivalent circuit. Notice that the pads used to connect the
p. @3 v, I6 C2 { c7 @traces on layers 1 and 2 make contact with the barrel and that there is no connection on5 @# {% ~& T7 R* _
layer 3. Blind and buried vias have a slightly different construction. Since through-hole vias5 M9 `2 F5 f" s% L/ d- S
are by far the most common used in industry, they are the focus of this discussion.' P, M. }7 f0 A+ A. t6 A+ D
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Notice that the via model is simply a pi network. The capacitors represent the via pad
# T; ^4 X* ]1 X% c i9 ~; c2 Scapacitance on layers 1 and 2. The series inductance represents the barrel. Since the via8 ~( w% s. I& ]) l7 l( H5 [
structures are so small, they can be modeled as lumped elements. This assumption, of
/ C2 C7 f2 `, l. ^course, will break down when the delay of the via is larger than one-tenth of the edge rate.8 e Y. G- s: m8 H# o4 K9 J
The main effect that via capacitance has on a signal is that it will slow down the signal edge
- F( c$ A2 P+ T4 e ]- ^0 Drate, especially after several transitions. The amount that the signal edge rate will be slowed0 L# u5 J3 m1 O0 P6 n
can be estimated by examining the degradation of a signal transmitted through a capacitive
/ q- A3 i' [4 s/ r& f/ Q e2 xload, as shown later in this chapter in equation (5.21). Furthermore, if several consecutive
! C. J M2 u- ?3 H$ Vvias are placed in close proximity to one another, it will lower the effective characteristic/ ?4 i5 g% a" Y, G+ f1 f
impedance, as explained in Section 5.3.3. The approximate value of the pad capacitance is
: d1 s! o# I" \) c' }[Johnson and Graham, 1993]
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0 o/ X1 u) Y2 i[ 本帖最后由 killerljj 于 2007-11-21 20:51 编辑 ] |
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发表于 2007-9-11 14:20
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反对！
发表于 2007-9-15 15:34
俺也顶一下,因为焊盘描述的太形象啦!
发表于 2007-12-19 08:39