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偶也跟一贴！
3 b j( g& X$ s/ c" Z% s以下内容来自《high speed digital system design》。8 K1 q8 T. a( f1 H, C. x1 ^5 f
1 h2 U* X+ u& ~) U" B
A via is a small hole drilled through a PCB that is used to make connections between various
; ^ e1 i6 x% Q! W6 g0 p: {2 slayers of the PCB or to connect components to traces. It consists of the barrel, the pad, and4 p% Z+ F& l; a( d4 N" S
the antipad. The barrel is a conductive material that fills the hole to allow an electrical( a4 I* {$ u- h3 l$ \* n1 Z
connection between layers, the pad is used to connect the barrel to the component or trace,# W8 S3 `) J! M2 x1 `# j4 s
and the antipad is a clearance hole between the pad and the metal on a layer to which no5 ^4 C- x* \1 b1 }+ h) P' A
connection is required. The most common type of via is called a through-hole via because it
- m/ s! B( t9 N0 b; Z Iis made by drilling a hole through the board, filling it with solder, and making connections on$ O' W0 G. Y. U7 ^$ V
appropriate layers via the pad. Other, less common types of vias, used primarily in multichip
/ @7 x' b) p( {- W. J' i+ e; U& m6 m! mmodules (MCMs) and advanced PCBs, are blind, buried, and micro-vias. Figure 5.1 depicts
6 R2 s `" ?" u: }a typical through-hole via and its equivalent circuit. Notice that the pads used to connect the
" C+ P( m" g' c: Itraces on layers 1 and 2 make contact with the barrel and that there is no connection on
0 T. g/ e3 S% j% O. t9 alayer 3. Blind and buried vias have a slightly different construction. Since through-hole vias
7 T/ Z9 T+ W M) eare by far the most common used in industry, they are the focus of this discussion.
8 f# x4 J0 z2 e2 M V1 N3 b6 ?9 ~- @
Notice that the via model is simply a pi network. The capacitors represent the via pad
0 J) r! L( W: D3 k- p# {$ Scapacitance on layers 1 and 2. The series inductance represents the barrel. Since the via$ A4 V) ~1 Z* k+ n' ]( ?( q- \( H
structures are so small, they can be modeled as lumped elements. This assumption, of% ? G" `6 u, r4 `1 ]1 G- Q- W
course, will break down when the delay of the via is larger than one-tenth of the edge rate.' [. q4 V1 a h; j
The main effect that via capacitance has on a signal is that it will slow down the signal edge" v$ _+ R; q# Q* u9 z
rate, especially after several transitions. The amount that the signal edge rate will be slowed
5 w8 p. j) g. e$ B8 A: } dcan be estimated by examining the degradation of a signal transmitted through a capacitive, {2 @ d# o; K5 c7 u& ^ E
load, as shown later in this chapter in equation (5.21). Furthermore, if several consecutive
) u( n' N& k- k; z5 Dvias are placed in close proximity to one another, it will lower the effective characteristic
, w) o2 v( R" J0 {% t* Cimpedance, as explained in Section 5.3.3. The approximate value of the pad capacitance is
2 U) V* L5 W+ @* \, T[Johnson and Graham, 1993]
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' Y1 c+ ]( C" F: y; p. F" e[ 本帖最后由 killerljj 于 2007-11-21 20:51 编辑 ] |
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发表于 2007-9-11 14:20
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3 i; ^6 y8 o5 ]1 O1 M
发表于 2007-9-15 15:34
俺也顶一下,因为焊盘描述的太形象啦!
发表于 2007-12-19 08:39