求助-QUARTUS II版本：13.0编译程序出现的问题

XIAOXIAOYUWU

QUARTUS II版本：13.0
FPGA型号：EP2C8Q208
% k7 n) e6 d0 [% U在编译的过程中出现了如下的警告：
4 v/ w! w4 P5 N! |2 r' Y（1）Critical Warning (332012): Synopsys Design Constraints File file not found: 'exp08_demo.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
: W6 x9 i0 S, @1 x6 E4 TCritical Warning (332012): Synopsys Design Constraints File file not found: 'exp08_demo.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
9 w- o  y& t/ W8 _: YCritical Warning (332148): Timing requirements not met
- T$ D* `+ r6 Z$ q( TCritical Warning (332148): Timing requirements not met

9 a; B, g. Y; s2 L3 D3 L（2）Warning (306006): Found 4 output pins without output pin load capacitance assignment
( `: L; X4 S$ \" Q2 }- E        Info (306007): Pin "Data_Out[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
        Info (306007): Pin "Data_Out[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ {7 N, u, P# c        Info (306007): Pin "Data_Out[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
/ z5 v! P6 ]) O) a4 U9 Y        Info (306007): Pin "Data_Out[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
. B( E6 k9 B3 V$ \( z( u程序是黑金开发板提供的程序：PS2解码 ，仔细检查了下，程序没有问题。

求助大侠，有没有什么好的方法来解决上述两个问题。。。谢谢

zgq800712

有种东西叫衣来伸手饭来张口

dspdesigner

这时说，你的电路没有时序约束文件。在13.0和之后的版本，软件都默认要求开发者提供时序约束文件，如果没有提供，就会给出 “332012” 警告。再者，如果没有提供，软件会自动按照1GHz的要求来进行编译，时序要求当然就达不到了，就会得到“332148”警告。后面几条警告，是说输出引脚没有分配电容负载

eda366_murphy

这个 E 文 说，要用 TimeQuest Timing Analyzer 去产生时序约束文件。没有这个，编译器无法工作