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本帖最后由 dsws 于 2013-7-1 20:32 编辑 : O/ K, w. T) O$ I |' L0 A% y
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CCRID PRODUCT PRODUCTLEVEL2 TITLE J; _/ |, Z% ~
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, I1 k1 J' g5 l$ d0 i914562 ALLEGRO_EDITOR GRAPHICS 3D viewer, PCB Symbol view in DRA needs to be same as in BRD* y- a; T$ k& ]3 |- ]; o
1120397 CONCEPT_HDL CREFER CreferHDL attempts to create missing vlog004u.sir files# K6 H( W, M! h" n( v7 x. `% k
1136449 ALLEGRO_EDITOR GRAPHICS about previous shape fill display
/ a8 k" W7 H# }% E: o$ `0 ^1145635 ALLEGRO_EDITOR SHAPE Auto Voding on the same net shapes with other parameter.6 g3 ^% j5 G7 F9 i; i
1150334 ALLEGRO_EDITOR EDIT_ETCH AiDT deletes the clines and turns it back to PLAN line
5 X$ e; r! ^& z, f8 F2 M1151100 APD VIA_STRUCTURE Net filter not working in replace via structure command.) j5 Y) ?7 |/ U6 f$ j
1151126 APD VIA_STRUCTURE Getting "group is not appropriate at this time" message when using Temp Group.& c9 {! n7 J z
1151458 GRE CORE GRE crashes on Plan Spatial8 i0 `! Z m7 j' D3 E% O4 s- `
1151932 F2B PACKAGERXL PXL error when case is wrong at differen levels in hierarchy
* M2 w" Y# _- r- [* a( a! B, V1152151 ALLEGRO_EDITOR INTERFACES dxf2a gives error [SPMHGE-268]7 k/ \1 F/ o( L* u* G% z8 C, @1 N' i
1152475 PSPICE SIMULATOR RPC server unavailable error while simulating the attached design
; F8 r( E G3 z( \1152737 ALLEGRO_EDITOR SKILL dbids are removed because highlighted objects in setting the xprobe trigger. c7 [0 I# G. T1 a8 I. u
1153006 ALLEGRO_EDITOR SKILL axlUIWPrint dose no work correctly in allegro PCB Editor 16.6.
& k; y7 A8 R2 `2 U1153279 CONSTRAINT_MGR OTHER Netrev changing design accuracy from 3 to 2 dec places
; H/ | L3 U. v1 y1153461 SIP_LAYOUT DIE_EDITOR Regression problem in 16.6 ISR: Dia Abstract ECO is causing Die Editor Finish to fail
2 n# Q' g8 X2 }$ ]6 ~1154973 APD EDIT_ETCH Same Net "Line to Line" violation occurs even with "Allow DRC's" turned off.
& x, i1 o. H4 y, i1155227 ALLEGRO_EDITOR DRC_CONSTR via to shape check on the negative layer
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http://pan.baidu.com/share/link? ... 0&uk=3826038294
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发表于 2013-7-1 12:00
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