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Cadence SPB16.6已经推出，需要的朋友可以点击下面的链接下载：
& ^( j/ I0 e: i) Y7 ddl.vmall.com/c0pxuzug1s
1 k: t H9 R, D% w% @3 p) t& K里面有补丁Hotfix_SPB16.60.001_wint_1of1.exe$ K( ] }% \- K! Y
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DATE: 03-7-2013 HOTFIX VERSION: 005/ p/ D0 Y1 X0 ~- k
===================================================================================================================================
! x+ @) T( Y* fCCRID PRODUCT PRODUCTLEVEL2 TITLE& O/ H' k5 \) O4 L
===================================================================================================================================1 {2 }1 r2 e* o+ g2 `2 q6 g
1067770 IXCOM-COMPILE COVERAGE Assertion failed: file ../covToggleCoverageXform.cpp, line 1102
& v$ m2 O, j3 g/ k( F% x) P1100442 ALLEGRO_EDITOR PLACEMENT Placement queue shows components whichs are already placed1 s# I$ J: j" L @* `) Y* @
1101555 ALLEGRO_EDITOR DATABASE Allegro Crash frequently6 z* ^- U, E8 n* U8 c. X1 X
1104011 ALLEGRO_EDITOR DATABASE Place replicate move group of a modules leaves traces behind
- T9 |% G, |: a% Q5 ]- @1104065 SCM NETLISTER SCM 16.6 has problem generating Verilog with existing sym_1 view
$ w% Z9 r g9 d/ J4 c1 D- Z! i1104605 F2B PACKAGERXL Pins of function swapped part in block not displayed7 c6 m: U7 g# y- u" J6 u
1104790 SCM IMPORTS Corrupt data once SiP file is imported into SCM- w9 l$ N5 B% d( n, L8 U" o- Y
1105066 APD IMPORT_DATA Import NA2 worked in 16.5 "035" but fails in 037 and 16.6
. ^2 l, x7 p: i5 ?2 k1106323 ALLEGRO_EDITOR PLACEMENT Unable to locate specific placed symbol on this board as it becomes invisible after placement.7 \5 _% ?4 J: x2 ^( T% _! }! |. y, S' r
1108032 CONCEPT_HDL CORE 'Find' option does not list all Components in the Design, ~ u1 J1 h) ?' E) _$ F
1109080 ALLEGRO_EDITOR OTHER Window DRC is not working in OrCAD PCB Editor Professional |
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发表于 2013-3-15 15:12
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发表于 2013-6-29 13:29