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DATE: 02-17-2012 HOTFIX VERSION: 016, l+ B- t' Y- e9 S
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1 @1 ?8 p4 z/ ]' V: ?CCRID PRODUCT PRODUCTLEVEL2 TITLE% d0 i: p3 |: E* j5 Q$ m
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840105 PCB_LIBRARIAN USABILITY PTF subtype is getting changed when Save As option is used in PDV
3 p( s$ {, }9 o. F7 b873075 PSPICE PROBE Decibel of FFT results are incorrect.4 P) q; p+ a- P
938744 ADW COMPONENT_BROWSE Need ability to customize shopping cart columns to include any Part property
5 K+ K! x7 S* j943003 SCM REPORTS The dsreportgen command fails with network located project9 ^( K, W7 K% ~9 U
961530 ALLEGRO_EDITOR INTERACTIV The problem of Display measure command
( ]1 E8 G; q2 G; `( g: F4 n962157 CONCEPT_HDL CORE Where is the setting for enabling the Enable PSpice Simulator menu?, P4 t9 A; d& F7 l# Q& p
962206 CONSTRAINT_MGR CONCEPT_HDL Import physical not passing all constraints from the board to frontend
: A/ N% g/ |% M1 b; R968205 PSPICE DEHDL_NETLISTER Change SPLIT_INST property to PSICE_SPLIT_INST for Quad Switch type of design.6 d& o8 s) [0 Y4 e' v
968509 PCB_LIBRARIAN METADATA Incorrect pinlist.txt was generated if DIFF_PAIR_PINS_POS/NEG was set.
8 [* Z ]2 \6 _1 O8 [969450 LAYOUT TRANSLATORS OrCAD Layout to Allegro Translator crashes
3 @" C j: g5 ? \969997 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance pro~
+ R3 @+ _$ @+ a7 ]8 u971193 CONSTRAINT_MGR UI_FORMS Copy and pasting a formula causes the application to crash on windows.7 H6 |6 B* [# N) S3 A5 }
971601 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053) and WARNING(SPCODD-66) because of directory structure
# b3 r/ M( |$ S3 [* f5 e v8 ~973398 CONCEPT_HDL OTHER It should be not packaged with error while working the packaging process if the design has a ERROR; X$ A9 t7 U# h' |
973859 PSPICE ENCRYPTION Pspice crashes with encrypted model* Q& X% [, n' f6 _- [1 m$ t
973938 PCB_LIBRARIAN VERIFICATION pc.db is missing( b0 {! J, v) T/ K
974540 CONCEPT_HDL CORE Graphics updates are real slow
" i* n) o7 P1 O. }974791 F2B DESIGNVARI Variants are not back-annotating to schematic and turning to ?
2 D) E0 @: k. S2 P; F( l$ s974818 ALLEGRO_EDITOR NC Backdrilling produces 0 plunges yet no errors reported.8 T3 b' S h+ F: R( X9 d, B
974945 ALLEGRO_EDITOR SKILL Why is axlPolyOperation is giving different result and not working3 P: o( P- P3 o7 W! f
974946 MODEL_INTEGRIT TRANSLATION ibis2signoise returns the error - Delay measurement fixture must contain V for ECL technology
* u7 \" B1 ?9 B5 H2 q' y! Q; d; D6 w975396 CONCEPT_HDL CONSTRAINT_MGR Constraints are dropped after migrating from 16.3 to 16.5
5 }* L4 y) Y: ^0 ]' \( w975633 ALLEGRO_EDITOR GRAPHICS 'dynamic_layer_visibility' option in 3D Viewer when checked or unchecked should not change (until next change)
& \+ C! T+ L" J' ], g6 p. e5 b/ B4 G( j975720 ALLEGRO_EDITOR DRAFTING Datum dimension lines not adjusting to text move" v$ N4 M0 }2 H1 |& N @
975745 ALLEGRO_EDITOR SKILL cdsServIpc different 16.2 vs 16.5 when Allegro exits; H* A: M* @. H3 k( E
976013 CONCEPT_HDL INFRA Power pin connection of FPGA symbol is missing in netlist.# ]! A& G* ^: F' G9 L# F# s+ G
976058 CONCEPT_HDL COPY_PROJECT SCM Copy project does not create the con and dcf files in tbl_1 views& z8 [4 E1 w0 U# ^
976073 CONCEPT_HDL COPY_PROJECT All the constraint data is lost in the SCM copied design7 T' y- O+ z6 {2 u- @4 Y
976160 CONCEPT_HDL CREFER Cref fails due to some Caeviews error in the design
) ^( _4 {/ Z; E; _! m0 ]3 `976204 ALLEGRO_EDITOR DRC_CONSTR Application falsely reporting Mechanical Pin Antipad to Shape Spacing DRC
0 ]8 h7 A" @0 ~976448 F2B PACKAGERXL ERROR(SPCOPK-1069): Invalid POWER_GROUP property value: m& F9 r& {% M) D" [& Y6 U
976521 ALLEGRO_EDITOR DRC_CONSTR multi-thread update DRC causes the application to crash6 k6 D* M( d5 D% N& ^- }+ P3 Y9 m
976838 SIG_INTEGRITY OTHER Unable to create XNET for highlighted nets on attached database even after assigning proper Signal Models.# q. E+ L; O* V* _7 @! p; N
977517 F2B PACKAGERXL Export physical fails after update to 16.5 from 16.3
9 u1 x) s4 L A: K" m977902 ALLEGRO_EDITOR DATABASE generate module is crashing allegro
0 [$ s+ Y9 r8 \9 H3 H' ~8 I; m978652 ALLEGRO_EDITOR PADS_IN PADS_IN fails with ERROR: Finished with errors.4 X: M9 l J( V$ H4 A8 F0 j$ v, Q
978744 APD DEGASSING Some shapes will not DeGas on this design
6 W5 J0 N5 u' _, l) |! e979940 SIP_LAYOUT OTHER SiP Layout Leadframe autobonding with profile selection: o% V; k& V1 |6 s. g
981699 CAPTURE HELP Start Page still shows Hotfix 14 after installing Hotfix 15( @$ F5 L+ E3 g+ f
/ ]' j" c! A; j
DATE: 02-03-2012 HOTFIX VERSION: 015
/ x: g8 k) F7 A. s) o$ Y( Z' N+ U===================================================================================================================================4 m. A2 {) V0 f6 o9 I% v1 z
CCRID PRODUCT PRODUCTLEVEL2 TITLE
, v3 ^: _9 A3 l; h" L( }===================================================================================================================================3 s/ Z/ ^' N; ?4 w
871567 CONSTRAINT_MGR SCHEM_FTB Ability to filter out Single Node Nets from Constraint Manager4 Y/ j8 w1 \% U$ g0 P5 Y! n0 T
921436 ALLEGRO_EDITOR MANUFACT Change in 'decimal place' for new dimension changes the already placed dimension
# L& f$ w2 G5 r. t F941433 CONCEPT_HDL COPY_PROJECT 16.5 Copy Project should warn if trying to copy a 16.3 design( n; d4 q( s0 x2 T4 @ M
954375 ALLEGRO_EDITOR MANUFACT Change dimension accuracy for few instaces of associative dimensioning
6 q$ i& ]( G3 M; |4 @0 p9 K1 U961646 PDN_ANALYSIS EMVIEWER EMViewer Help > About shows wrong version
~* l0 {6 W8 } l8 ^0 v964912 CONCEPT_HDL COPY_PROJECT ASA project crash after using copy project
: b l/ _* V8 l' P2 |- B+ ^967223 ALLEGRO_EDITOR MANUFACT Bug:Oval slots orientation in one direction only
! o& h: g! s4 ^% x8 A C968865 SIP_LAYOUT DIE_ABSTRACT_IF load of die abstract fails due to differences between component and symbol
. f: b- L( O+ r" h: Y: Q969485 ALLEGRO_EDITOR SHAPE Shape does not update correctly in 16.5
) d# z1 N. O5 w4 R970331 CONSTRAINT_MGR ANALYSIS Impedance worksheet shows a zero value for impedance
7 J! `3 L2 \. h3 B/ m970600 SIP_LAYOUT SYMB_EDIT_APPMOD Option in Die Editor to be able to "physically swap" pins" ~: ?. h& a- M' z) r2 T' J
970910 F2B PACKAGERXL Our customer has problem with pin color after pxl 16.5.5 b1 E& M. K6 v
970970 SPECCTRA FANOUT Fanout Vias is placed far away from decaps and does not change the Fanout length even when max_length is reduced.
6 k6 y) A% J4 N1 R V970985 SIP_LAYOUT OTHER Importing a .spd2 database file using NA2 will cause the APD/SiP tool crash
8 n" e7 e/ e- Z' K7 C6 F! v971757 CONCEPT_HDL INFRA Crash while Saving/Packaging the Design) s; J5 d7 j# W
971923 ALLEGRO_EDITOR MANUFACT Allow to change decimal accuracy for dimension instances
: p8 |, K! n+ g" V972568 CONSTRAINT_MGR UI_FORMS Tools >Excel missing from CM
$ O) _1 r z6 E. d$ d3 m5 ^% Q972821 CONSTRAINT_MGR CONCEPT_HDL connectivity server warning: Unable to add property WEIGHT
9 K5 _/ }+ q! u5 }973185 SCM CONSTRAINT_MGR ASA2 block not seeing all instances in a package.0 J. @/ f0 a n4 Q0 K& }1 B
973211 ALLEGRO_EDITOR INTERFACES IDX Object Type Change not recognized
6 j# a& M0 F/ y" ~- S8 b4 h% x* h9 v973214 ALLEGRO_EDITOR INTERFACES IDX import package keepout height value change assigns incorrect value
% f8 ]& ]: t0 f/ s j973384 CONCEPT_HDL CHECKPLUS The multiple SIG_NAME has to be occurred an ERROR at the SPB16.5.
2 {. D1 o) a% o( D973514 SIG_INTEGRITY OTHER Mapping error when Ecset is updated to constraint manager from extracted net
$ ]( r8 q4 i i4 H' ^973950 ALLEGRO_EDITOR SHAPE Update to smooth crashes application, z+ y. a6 `, p1 h* v! `. t; t
974533 SIP_LAYOUT OTHER Crashes in Edit > Die Properties and obviously has a setup problem.
3 H9 [& c+ F. L* o! V974809 ALLEGRO_EDITOR SKILL argument available for hiding a property with function axlDBCreatePropDictEntry is not working9 D/ M; y% L* q3 N/ b! H7 X A
976179 INSTALLATION ISR Installation of ISR S014 to 16.5 on windows is breaking the documentation index
% F" A4 r1 W( V* i. R& H8 r' k5 U+ Q3 H/ g: f' z* `
DATE: 01-20-2012 HOTFIX VERSION: 014
$ A, i- z! s5 k6 n2 S" _===================================================================================================================================5 i" M2 g6 G* ^6 ?/ Y) d5 B0 x
CCRID PRODUCT PRODUCTLEVEL2 TITLE3 V9 k! ^, D; ~; R) j/ C C
===================================================================================================================================
- e/ Z' A3 P+ a K# y% O! p% O733285 PSPICE SIMULATOR Enhancement:In server-client installation use existing index file from server4 h; U8 q/ n( q# t/ H
941020 SIP_LAYOUT OTHER Soldermask enhancement6 K5 H5 o/ }% q
946407 CONSTRAINT_MGR TDD When is it safe to open a 16.5 design in 16.3?/ G7 x) a# Y. B% A) d [9 R
953067 CONCEPT_HDL OTHER Variant Editor "Error/Warning messages" form is unusable; p; m- j$ e* z' [" V
954818 CONCEPT_HDL COMP_BROWSER Replace button turns to Add in component browser when a component replace is done on the schematic
( K4 A: [: U9 M956450 ALLEGRO_EDITOR DRC_CONSTR Analysis always shows analysis failed in uncoupled length in some diffpairs
# Y5 S+ Y& T' V4 n; b+ j958259 F2B DESIGNSYNC ds.exe crashes on a big design when accessing the design from network drive( F4 i p* U4 `/ V7 _/ z
958395 ALLEGRO_EDITOR SHAPE shape voids won't merge+ z/ S2 u5 s' a: I- _2 d; n1 R
959212 MODEL_INTEGRIT PARSE Attempting to use "Mark qualified" option on DML File results in dmlcheck and Modelsim wanrings., A% [4 R P2 P
959940 APD AUTOVOID Void all command gets result as no voids being generated.! ]" d, \' c( N# q% G5 k
960252 PCB_LIBRARIAN CORE Splash screen in PDV prevents showing error message
9 |. j: ~9 k7 U961634 PDN_ANALYSIS EMVIEWER Cannot launch PDN EMViewer from withing PCB SI
4 G( k; z5 D7 \ o1 X$ o( m961645 PDN_ANALYSIS EMVIEWER Standalone EMViewer will crash when opening any result file in the form of *.emv file.6 D; ~' A) [# ]- f: A' G" ~
961700 ALLEGRO_EDITOR SHAPE dbdoctor reports ERROR(SPMHUT-144): Illegal arc specification
9 L, t1 G3 \2 \9 t- p m961733 ALLEGRO_EDITOR SKILL Allegro crashes. Appears to have a memory leak.
0 R# Q( \9 j6 s. n$ p; F961758 ALLEGRO_EDITOR DRC_CONSTR DFA check produces no DRC when the dfa bounds are not a rectangle.; c c& _ w5 Z/ C5 e5 E1 B9 G
961887 CONCEPT_HDL CONSTRAINT_MGR Match Group created from ECSet cannot be deleted in the same session of CM
4 V* y/ y# J" ~9 k( A% o# e0 F962552 APD EDIT_ETCH BUG:APD crashing when we try to slideget information but move works fine
3 d! T. k8 C' z3 W962869 CAPTURE STABILITY Capture crashes after RMB click on rotated parallel wires$ z# q) n; P1 X4 P; f/ m, A
963232 CAPTURE MACRO Macros not being played in Windows7& h- D! B0 e3 V
963300 ALLEGRO_EDITOR DATABASE Create > Module crashes in 16.5 but not in 16.33 O$ f! x1 D- d/ J- o+ i" D t
963651 CONSTRAINT_MGR CONCEPT_HDL ECsets are renamed after packaging on linux8 d+ e. ]1 y2 M! n: I
963663 CONSTRAINT_MGR ANALYSIS Q- Why the customized worsheet for Diff pair Impedance not analysing at all for this SIP design R& ~5 ~' Y; n
963715 SIG_INTEGRITY OTHER Application only adds the bottom conductor thickness for the via z-axis length
, g. K4 b# t0 Q$ E964068 ALLEGRO_EDITOR INTERACTIV Allegro crash when using move alt sym mirror alt sym..., w9 Z% ?3 K! ?0 w1 I3 v
964267 CIS PART_MANAGER Capture become non-responsive, working on Part Manager and creating CIS BOM, for large designs, ?# Q5 P. I, {3 [
964597 ADW LRM Issue of LRM license checkout after renewal license by 16.5 (ADW15.5_S23+SPB16.3), J! `4 t5 M! q1 C
966148 APD INTERFACES Character Limit for DIE Files (*.die) Import1 n+ X/ ^- {4 \! F
966416 F2B PACKAGERXL Cannot package this design9 [; s ~; E' |8 x9 F
966421 CONCEPT_HDL CORE DEHDL Crash when applying property on components in duplicated blocks2 ?* H% u* |0 x" R" N- v( c$ a0 _" e
966693 CONCEPT_HDL CORE DEHDL crashes when doing model assignment if CM is open- \5 i& U% V# o( R$ i7 ]( W3 X/ I
966795 ADW ROLLBACK rollback utility does not honor -product option from command line6 H. y F) P5 }7 l# ]% q/ x8 d
967089 SIG_INTEGRITY OTHER Matchgroups created by ECSet not deleted when ECset is removed from object.
* i4 \6 t r7 B3 t. ?, I+ s$ G! }2 X967222 ALLEGRO_EDITOR OTHER PDF export is leaving data off the drawing
* H, _: O9 k* w/ e, R( {" d/ Y967240 SIP_LAYOUT WIREBOND Change default bond fingers selected on multi-site leads during "bond to leads" program
3 a3 Q( ^* k1 R$ {6 Q$ {967297 ALLEGRO_EDITOR OTHER Dynamic Fillet&Eliminate unused stacked vias cannot be used as the Miniaturization option.
: a0 v3 ?! y3 Q8 k3 D/ M% O6 ^967576 CONCEPT_HDL CREFER Occurrence location property values do not appear in flattened schematic generated by CreferHDL- q3 |0 K6 L; T9 ^: f3 U9 I
968096 ALLEGRO_EDITOR DRC_CONSTR Mechanical Pin to conductor spacing is not followed.
& X) ]- h5 ~. }" K( Y/ F4 {968222 SIP_LAYOUT DIE_EDITOR die pin loses IC net for a co-design die with multiple ports within IO-cell4 E. f+ p4 b5 N5 t4 M1 U
968358 CIS PART_MANAGER Capture crash on removing a part from subgroup in part manager
/ s2 }$ ]* e$ `969594 CONCEPT_HDL CORE The dcf file is not updated with schematic changes
2 ]( E" t- @. A0 }0 o
, O1 d1 \1 R2 jDATE: 12-16-2011 HOTFIX VERSION: 0132 D5 J2 x6 U, T9 d* ?1 o' R
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CCRID PRODUCT PRODUCTLEVEL2 TITLE# ~6 N7 z* c7 e
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875695 SIG_EXPLORER INTERACTIV Enforce Causality check box doesn't work.
1 R$ Y2 `6 Z: a! {927148 CAPTURE PROJECT_MANAGER Capture crashes on creating scehmatic folder with name which already exists in design
0 G8 H# m9 ~- `! A5 {8 H: z938013 CAPTURE NETLIST_OTHER The netlist in RINF Format contained two identical lines for PCB FOOTPRINT
9 [: L3 q% N% t8 I6 W) q% V941409 PSPICE PROBE BUG : Search accuracy wrong in new cursor window
t$ J: D5 R/ N* q/ H945242 SIG_INTEGRITY SIMULATION Unable to select "shapes" in find filter for 'show parasitic ' command) h0 g( H3 |2 d; t* W7 T* u; a# X M
946293 CONCEPT_HDL ARCHIVER Archiver hangs if there is a whitespace at the end of the path of cref.dat
" S4 X( O$ i4 [6 v946770 CONCEPT_HDL CORE 揤iew Design� function is missing in Windows Mode after reseting the menus.
+ L" @# m& ]+ o+ k8 u8 q950994 CAPTURE NETGROUPS Problem in expanding the netgroup in Auto Connect to Bus function
3 D$ D3 Q4 Z& C% ~2 T! ]953530 SIG_INTEGRITY GEOMETRY_EXTRACT Display Parasitics is displaying wrong results for EMS2D Field Solver compared to topology extraction using Probe.4 l% Y9 S( \1 G* Z
953713 CONCEPT_HDL PAGE_MGMT Random page replacement/duplication in block! W+ l0 f1 f* l+ C" `* ~5 m
953917 CONCEPT_HDL ARCHIVER archcore should handle errors correctly
& a: U4 `. X% o& o953971 ALLEGRO_EDITOR MANUFACT NC Drill files not generated correctly when using the option "搒eparate files for plated/nonplatedholes�: C* B) d" o+ G. u" ~; R
954400 CAPTURE NETGROUPS BUS members of NetGroup are getting converted to Scalars in Export-Import NetGroup.& a( A# r! q# ?% e3 x3 {3 P
954498 SCM B2F SCM crashes when importing physical
- e) q5 |# j& g' o3 F954623 ALLEGRO_EDITOR EDIT_ETCH Unable to complete connection with Add Connect - related to soldermask to cline check?
0 h" ^' }1 g( X954894 ALLEGRO_EDITOR MANUFACT Dimensions disappear when opening database in v16.5 from v16.3# g, ?" G+ f( _$ A4 f5 f6 s
955029 CONCEPT_HDL CORE custom text font size not recognized in symbol view
2 H' b) C& a6 R5 A955133 SIG_INTEGRITY FIELD_SOLVERS The Field solver creates the differential trace model which is reversed T(D1) and T(D2) of bottom side.
! C* P7 p8 S3 j& y; T6 D955290 CAPTURE DRC Description for UPD0014 missing in the Browse DRC markers window
& R) @* h" ?" C" @3 f q$ ?955299 ALLEGRO_EDITOR DRC_CONSTR drc text to smd pin does not work any more on this database in 16.3 S039
4 E3 ~1 v( X8 e% B! [955338 CONCEPT_HDL CHECKPLUS Need to change PART_NAME' Q$ p& S' g4 ~- N
955447 SIG_EXPLORER OTHER Model path set in DE HDL Model Assignment not used by SigXP from CM in DE HDL' C7 Y. c2 ? k' [
955740 SIG_INTEGRITY GEOMETRY_EXTRACT Crosstalk with Timing Windows does not work correctly
2 m' {; N: ?0 g3 q1 P955749 ALLEGRO_EDITOR MANUFACT show element Info shows symbol dimensions on incorrect subclass
) Z7 z3 }6 ?* x! f0 l4 p; f: w2 M955912 ALLEGRO_EDITOR OTHER Shapes with voids that are exported to PDF have gray filled area over the void
, c, d0 h+ N/ @7 m2 M# [- _. `! f6 K956129 CONCEPT_HDL INFRA DEHDL uprev hierachical design from 16.2 to 16.5 packaging failure.( A" z- d: p6 c+ T( E% R1 Y
956373 ALLEGRO_EDITOR NC drawing name doesn't display in the log file
2 l! _: n+ [( r7 N9 B, d956393 CAPTURE PROJECT_MANAGER "GENERAL" and "TYPE" tabs are missing from " roperties" dialogue box.+ {+ } Y1 P- u( ^, d; L7 p
956448 PSPICE MODELEDITOR Can not generate a DEHDL symbol from Model Editor, because no Capture license found; p9 W! K) l, ^8 p# y( g8 v) a
956456 CAPTURE NETLIST_OTHER OrTelesis netlist not transferring user properties defined under combined5 W% v) i% N3 C: D9 g& U# V
956489 ALLEGRO_EDITOR MANUFACT dimensions lost when symbol with diemnsions attached to symbol origin placed on board
, T; u$ V+ a! i. z0 q5 s" a956603 CONCEPT_HDL OTHER Part Manager "has stopped working" after changing a component& Q: S& T0 N8 c6 `$ Q' B- i
956751 ALLEGRO_EDITOR ARTWORK Import Gerber command does not work correctly
4 T9 S1 P& j' D8 w* k9 l) o956847 PCB_LIBRARIAN METADATA PDV - Partdeveloper symbol to function linkage broken/changed in 16.5
G/ A1 C" {; f- @4 j956987 CAPTURE OTHER Find from "Search toolbar" doesn't gives complete results
- d2 ~, k8 K) j$ t* k956996 CONCEPT_HDL INFRA Correction to ERROR(SPCODD-7): Following Primitive instance causes CM to empty* q2 }5 p$ Y9 U& s
957009 CAPTURE NETLIST_OTHER Problem getting database property in Mentor PADS PCB netlist
Z$ y: W2 \2 z957137 APD DXF_IF DXF out command dose not work correctly.
% G. j: i( P1 O) e4 ^ ?957167 APD GRAPHICS Highlighting for Static shape with display_nohilitefont environment variable.% N- D, I4 Z; |+ q7 G9 G
957232 SIG_INTEGRITY OTHER Allegro crash during Model Assignment.! q) @ k: U' ?
957267 CONCEPT_HDL INFRA Packager Error after Import Design
' m8 N+ R( v0 b. Z' b$ G! ?! s/ @957866 SIP_LAYOUT DATABASE Cavity outline is not getting deleted from symbol file
/ {3 _( q" E; [' b* B1 p! q958010 ALLEGRO_EDITOR REPORTS Wants the ability to extract "Batch" reports from Partition ".dpf" files.: D. i5 Q u7 y
958252 ALLEGRO_EDITOR TESTPREP Resequence testprep with the option - Delete probes too close crashes the design
5 B1 p$ s+ {- ?- J7 e; J; ^958253 ALLEGRO_EDITOR REPORTS Shape did not have thermal relief connected to pin but unrouted nets still shows zero.5 c/ Y1 O5 v7 p9 G# _# \
958433 ALLEGRO_EDITOR DRC_CONSTR False embedded component DRCs
: |# C( f6 p9 Q& I7 N5 c! ? W3 x# d958753 ALLEGRO_EDITOR SHAPE Dynamic shape is getting corrupted in 16.5
- ]0 q6 y4 o M( a* e959011 ALLEGRO_EDITOR OTHER copy problem of via and cline) r6 J$ y6 b8 |8 K
959101 ALLEGRO_EDITOR EXTRACT Using extracta with excluding Thermal reliefs9 ^9 X& o7 A) M' x$ @( N6 ^2 D
959253 CONCEPT_HDL INFRA Design will not open
+ |& M6 ^4 s# [2 g959299 APD MODULES Getting ERROR(SPMHDB-279) when trying to update modules placed on the Top side
7 \* ~- S2 r* L6 @959884 CONCEPT_HDL INFRA Design Uprev/concept2cm crashes with Application Error/Out of Memory Error.
1 ^0 y# t4 W" \! t9 t6 f% J959909 ALLEGRO_EDITOR SCHEM_FTB Site level propflow.txt file is ignored property is transferred
" W% u, @0 d! ^) G! s% q960067 SIP_LAYOUT PLATING_BAR Creation of plating bar removes "NODRC_ETCH_OUTSIDE_KEEPIN" property from the clines." |. D& f! J3 v7 E1 d9 s
960126 SIG_EXPLORER EXTRACTTOP Allegro PCB SI license is used automatically at Topology Extraction of Allegro Physical Viewer.) |/ c1 ]$ N) \! N, n. N- l- _
960143 SIG_INTEGRITY GEOMETRY_EXTRACT Running simulation in Bus sim happened crash while enable Coulpled Via model to S parameter+ P: D6 j3 U/ H
961349 CONCEPT_HDL HDLDIRECT Motorola designs have broken connectivity compared to 16.3
! S- p& a0 ^1 x' P% n- P961816 ALLEGRO_EDITOR INTERFACES Normal Export > DXF fails and offsets the pins of the BGA symbol
+ `/ Z) i; a# ?. l! E( f962519 SIP_LAYOUT WIREBOND Align option doesn't work for wb_tackpoint fingers
8 W' v# O# h- W! U+ L; a2 }5 Q- G7 L( p4 F/ ^: p
DATE: 11-30-2011 HOTFIX VERSION: 012# a8 v2 K3 p( r6 j
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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) h& Q" ]5 ~8 D- X% W0 _# h959581 CAPTURE NETLIST_OTHER PCB Footprint is getting replaced by VALUE in OTHER netlist formats
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9 _$ L% l) ~' \2 I6 Y; `% N+ Z" m7 zDATE: 11-18-2011 HOTFIX VERSION: 011" e, P9 J0 ?; b+ b
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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735439 PCB_LIBRARIAN CORE PDV Moving line-dot pinshapes by arrow keys breaks the pinshape, c* I0 m1 Q$ }5 H5 u1 I9 |- B! h
894815 CONCEPT_HDL COMP_BROWSER Why does genlibmetadata command give 'Aborted $PROG' Message?
% _* ~4 G, ~% S903073 ADW COMPONENT_BROWSE datasheetl_url directive should support a display string for URL
, _; U8 |+ g/ }5 @909919 CONCEPT_HDL OTHER Why is the PublishPDF UNIX command line looking for "true" script?
% g$ E! N. |. s( B911561 CAPTURE CORRUPT_DESIGN Capture crashes on trying to save the design.
, P* \; Z) R9 x- h+ h$ z919579 CAPTURE PRINT/PLOT/OUTPU Print mode be selected based on schematic mode; A5 \0 {. D) }1 Z, y
921247 CONCEPT_HDL COMP_BROWSER genlibmetadata.bat file does not have err defined. T q/ \& _* v; J7 e
925182 CAPTURE PROJECT_MANAGER ENH: Feature to run update cache on all the parts in design cache at once.. U8 _1 ~% F9 r+ @# S
926858 CONCEPT_HDL CORE Usability- Modify Component dialog forces user to do 'Reset Filters' to see other ppt rows
' b+ t9 ]1 ^7 w& ]2 O* f# E927657 CAPTURE NETGROUPS Enhancement: Placement of netgroup definitions under design cache list
$ S3 K) _' B) }# N X# ?( L9 @934684 ALLEGRO_EDITOR MANUFACT The relation between the linear dimension and the symbol breaks.. c* } R$ `# S+ U& Y; y# L
935836 SCM SCHGEN ASA crashes when generating Flat Document Schematic. r" N- r0 T2 N2 K: u
937165 SCM SCHGEN Can't generate Schematic
$ o4 B. O, Y/ Q: X* t7 ^: B$ F937292 CAPTURE GENERAL Memory usage keeps on growing and finally gets exhausted while search
8 N2 v' ?1 f+ M/ o937322 CONCEPT_HDL CORE Master.tag file alters the sequence of the files and Genview fails- F8 |; f6 z$ I7 R
939135 CONCEPT_HDL CORE Unable to uprev a 16.3 Design to 16.5 with DEHDL-L License
. R% H% l- f# O/ O. M% Q940373 CAPTURE TCL_INTERFACE Enhancement: TCL command to add nets to Netgroup/ B4 U2 q) M; h H- x. S
940547 TDA CORE ERROR(SPDWSD-69): highspeed cannot be checked in# }; k- Q* J1 G3 X7 [& F% r
940607 SIG_EXPLORER OTHER Inconsistancy in License usage for opening sigxp -orcad K' Y6 e5 x( h0 j$ U' {
940790 F2B PACKAGERXL User doesn't want to display pin numbers after Export Physical 16.5.
7 s) m( l/ }- r9 W( v6 Q940944 SIG_EXPLORER OTHER Inconsistant license usage while opening Orcad PCB SI using allegro -sq -orcad and allegro -sq) ^1 R1 v. J7 Y! p6 @' ]) T) I
941354 CAPTURE NETGROUPS Enhancement: Option to rename the unnamed NetGroups% l7 [& h6 p* _1 p& o5 S' H* J
941455 ALLEGRO_EDITOR MANUFACT The Dimensioned mechanical symbol when placed in the board does not show all the dimensions.( Q6 M( X s0 J6 V
941863 ALLEGRO_EDITOR EDIT_ETCH Different behavior of design in v16_3 & v16_5 when add connect is executed on a segment thru script8 H& l4 F5 B% _' S x" q# B
941881 CONCEPT_HDL COMP_BROWSER How can I suppress the dialog from universalbrowser -genlibindex?4 Z, k8 x( f; t; R- H2 j9 [
942474 CAPTURE NETGROUPS NetGroup member type of last added member must be remembered by Capture3 F0 k, i( _- ~
942522 CAPTURE GEN_BOM Export in excel check mark doesn't invoked BOM in Excel* ^8 z9 s" {* D) B! X
942557 PCB_LIBRARIAN EXPORT_OTHER PDV Export to Capture crash
+ W3 `' |8 z e# O: ]; e% A942569 ALLEGRO_EDITOR MANUFACT Dimension move and change text deletes leaderless balloon! \8 D" j- i: s& e
942573 ALLEGRO_EDITOR MANUFACT Balloon type parameter has no effect on leaderless balloon.7 W8 q1 B: p% C6 x5 _
942613 CONCEPT_HDL CORE Genview supports only SCHEMATIC/SYMBOL/VERILOG/VHDL views as input type. .xcon not recongnised, T$ i4 X7 u( _( M% i8 o7 }# m
943032 SCM OTHER ASA is not passing the correct reuse_module name to Allegro PCB layout.* ^) A" y( k5 u- i ~
943401 CAPTURE NETGROUPS Alphabetical ordering of NetGroups in Place NetGroup
+ w: p6 _& _* J/ C8 z: |2 x944006 ALLEGRO_EDITOR EDIT_ETCH Vias added to shapes behave differently% S- I2 y0 G& A! r
944367 CONCEPT_HDL OTHER Too late to do Model Assingment in conceptHDL 16.5, L, n0 S+ [7 L
944788 ALLEGRO_EDITOR GRAPHICS Oblong Pad shows unexpected lines
+ T$ n t% a4 p' t- K$ S945221 CONSTRAINT_MGR RETAIN_CNS CM Conflict Resolution fails on more complex designs using ECSets and constraints
; H& k. D( ~" `" @4 c$ i+ Q946270 ALLEGRO_EDITOR PLACEMENT The Rotation Type was changed to "Absoute" if the "iangle 90" use at placementedit mode of spb16.5- q7 {/ c0 A6 A
946350 F2B DESIGNVARI Variant Editor rename function removes all components
9 M6 d$ A. B6 q$ \. a946380 F2B DESIGNVARI Some VARIANTX properties are hard some soft - why?
) `* w1 T9 O2 t9 b! L( i1 X- D* ]946419 SIG_INTEGRITY SIMULATION Cannot select component on BoardModel for controller in bus setup form1 w j& M, f1 a7 S
946458 SCM SCHGEN Schematic generator adding an unnecessary page
, P0 |9 \6 O( t/ M7 b N947667 ALLEGRO_EDITOR PADS_IN Need support for PADS-POWERPCB-V9.3-BASIC* G6 Z1 I1 k4 i: {# g# B& j
947789 ALLEGRO_EDITOR MENTOR mbs2brd crashes during translation on the attached design.
! v8 t0 m" Y* _/ W948110 CONCEPT_HDL CONSTRAINT_MGR Concept HDL craches when opening SigXP from CM7 M( ^4 d# ?5 {/ V# @; b* W, U7 N
950970 ALLEGRO_EDITOR MANUFACT Unable to generate artwork, dbdoctor fails to fix errors.
0 ]- q5 Q9 }/ D( p* I9 X! d/ L951901 ALLEGRO_EDITOR EDIT_ETCH In 16.5 add connect to same net is shoved, V6 c0 @& \* X2 D1 r9 z9 j J+ `
951919 ALLEGRO_EDITOR OTHER Exported package symbol soldermask and pastemask padstack locations not the same as original/ u1 Q/ ~4 ?7 T' I( f
951926 CONSTRAINT_MGR OTHER What is MaestroNotifyNotSetReport.txt file?: @% C5 N4 K, z
951939 F2B PACKAGERXL Uprev to 16.5 is changing refdes for some pages2 q4 z) @. Y: o5 N9 `
951983 CONCEPT_HDL INFRA Problems converting an Allegro design from 16.3 to 16.5
) ?/ G; g% Z6 l* H! R952057 SCM PACKAGER Export Physical does not works correctly from SCM7 o4 P [( h0 g9 t _1 _1 [- Q
952217 ALLEGRO_EDITOR GRAPHICS crash when opening 3d viewer in PCB Editor
9 y/ ^2 q% a1 y+ o952634 CONCEPT_HDL CHECKPLUS Checkplus logical rule fails on a design which packages fine in 16.5
$ T6 \+ l3 B6 _4 K953018 APD REPORTS Shape affects Package Report result.$ |# F p& |2 G$ ]+ F& \* l1 {
953337 ALLEGRO_EDITOR OTHER Allow netname and padstack names to be visible for testpoint vias when viewed in Allegro PDF Publisher.% P* M6 Q+ H) j/ e; s1 M
953827 ALLEGRO_EDITOR EDIT_ETCH Snake Breakout function crashed Allegro
% K) r0 e* m5 X4 s% n/ W953918 GRE CORE GRE cannot route second and third row of pad in die symbol.. d& i4 _6 @: T- O: B6 L! Z
954055 CONCEPT_HDL CREFER Crefer fails with UNC install path/ `' t& v, g: [5 G3 C: z, x' G
954920 SIG_INTEGRITY CIRCUIT_BUILDER Each neighbor crosstalk simulation crashes or returns blank report
# V5 c) p- ?$ E& j+ \# y) i$ ~" B6 g' s
DATE: 11-7-2011 HOTFIX VERSION: 010
& w' `4 f1 j z: J& F& U===================================================================================================================================
4 U6 Y/ X1 N! Q7 [+ Z, r8 V( k2 z* DCCRID PRODUCT PRODUCTLEVEL2 TITLE7 p7 ]" s+ P; ^3 j& |4 O
===================================================================================================================================2 z/ S0 z" N& W* X* I& z* r F
658866 ALLEGRO_EDITOR EDIT_ETCH enhancement option - so that Sliding a via inside a pad does not create a cline( y. x- ]# y |- r: u$ D
928624 ALLEGRO_EDITOR GRAPHICS Layer visibility control for 3D Viewer
K3 a6 G7 T8 S. d7 ~% E934991 SPECCTRA LICENSING Specctra_adv option is not working correctly for PA3100 plus PS3500 license in v16.5 tiering profile
, e& J. B$ }$ o$ v6 m* f# n938073 ALLEGRO_EDITOR PLOTTING Plot Page size A0 and A1 with problem
/ ?: N0 B$ R. P' j( U& E938128 ALLEGRO_EDITOR DRC_CONSTR DRC changes when do update DRC.8 l; v3 w( l4 i" h2 w
938648 ALLEGRO_EDITOR GRAPHICS Enh - Requesting a way such that Package keepout appears transparent in 3D Viewer4 ?9 O2 L/ i6 K) j
940518 SIP_LAYOUT SYMB_EDIT_APPMOD Swap pins command doesn't complete& C4 A$ ]: X q+ t6 m' D
941426 CONCEPT_HDL COPY_PROJECT Copy Project fails - Updating opf view This can't happen!
% Y+ o; {9 Y2 B1 x1 j941499 ALLEGRO_EDITOR DRAFTING BUG imit Tolerance isnot working for Dimensioning
# k g- c* J; \* ]941814 CONCEPT_HDL CREFER CreferHDL crashes during ScheGen
! C& W8 h! D& p p- w942914 SIG_INTEGRITY OTHER ZAxis delay calculation! W. Y7 p, W: q7 f8 a
943053 ALLEGRO_EDITOR SHAPE Modifying the Board Outline shape will cause the tool to crash+ a4 A8 b# o4 o
945321 SIP_LAYOUT EXPORT_DATA generation of a xml file from cdnsip for shrunken die
: D$ U* k4 w- v945350 ALLEGRO_EDITOR SHAPE iPick does not work on shape boundary edit.8 F8 g8 k; s( n9 m/ _; u) v# \
945449 APD SKILL When they create a new menu entry with skill APD crashes with next menu selection.
; s9 f- B; A6 X, U! z( c$ h946390 ALLEGRO_EDITOR DRAFTING refresh_symbol crash when trying to refresh mech sym that has dimensions
! I- `- H; y! ?9 g% C4 ~+ B946401 APD EXPORT_DATA stream out gdsII results in shorting of PWR/GND nets due to elongated etch' E% o( |7 Z& K7 I# b! R
946819 SIP_LAYOUT DEGASSING Shape degass command
3 `+ U" p# ]( T6 e e946869 ALLEGRO_EDITOR OTHER Allegro PDF arc representation needs cleaned up
' e0 y2 Q, A" p0 L; e947230 ALLEGRO_EDITOR SKILL Skill execution crash Allegro 16.5 but work correctly with Allegro 16.3# B; g5 K% O* w t
947603 ALLEGRO_EDITOR OTHER Component Properties (Default or User Defined) not transferred to PDF file
u: G: _& R) ?+ R- M% Q950995 SIG_INTEGRITY OTHER Netrev fatal error when importing logic* @( Q, ~& x) f |9 b/ N7 F( m7 g
951123 ALLEGRO_EDITOR INTERFACES IPC fails to output drill hole info in columns 33-37
' |! g4 B& F" K0 W) r5 I951557 CONCEPT_HDL CORE Cannot create the entity folder for old plumbing symbol7 X& d, ~8 @3 o! p6 f5 E
% ?! }2 o8 j- f0 L y: E# F
DATE: 10-26-2011 HOTFIX VERSION: 009$ B/ a* l; q$ g! C
=================================================================================================================================== c8 s8 P4 e; T/ y2 @
CCRID PRODUCT PRODUCTLEVEL2 TITLE3 A: |. C, v9 H( B$ O2 i0 }
=================================================================================================================================== g' n; G( N6 q& D, l' B- ^2 J
945788 CONCEPT_HDL CORE Some component properties on the parts are incorrectly changed after Import Sheet
; k8 ?# L! y( {) I945789 ADW LRM Some component instances are not updated by LRM even though cache ptf is updated from reference
' E9 [+ j0 |. N3 S+ G
W U% N# _- l8 i8 TDATE: 10-21-2011 HOTFIX VERSION: 008
- {! {/ k% g, u& E" t ]4 a===================================================================================================================================
" E; \: n' i6 }' b3 RCCRID PRODUCT PRODUCTLEVEL2 TITLE
; X8 U! V, p* n& e===================================================================================================================================
( X1 ?$ Y7 v8 }906827 ALLEGRO_EDITOR DATABASE Logic > Parts logic does not work correctly.+ u3 k8 P) A1 C2 j6 E+ _, u$ q
923346 CONCEPT_HDL CORE Not able to move the reference designators inside hierarchal blocks after uprev to 16.59 `6 O# `. r. \
926347 ADW COMPONENT_BROWSE Usability- Libflow Part check in comment should end up in Comments attribute for UCB/Designer to see it. r4 d) J2 x, h) s5 I+ v4 f* w9 {
929348 F2B BOM Warning 007: Invalid output file path name* o- s! J* m; D: m$ l6 d2 r% [1 [, _
929777 CONCEPT_HDL OTHER Component Revision Manager gives internal error
5 s6 H+ e' r* r+ ` ?930783 CONCEPT_HDL CORE Painting with groups with default colors3 o) x1 K" l2 g1 I8 W
936748 ALLEGRO_EDITOR INTERACTIV "Unplace Component" menu inconsistent between General Edit and Placement Edit Mode.0 J/ a! b; R9 H. B0 S$ q, c
938143 ALLEGRO_EDITOR CREATE_SYM Why is this Extra Property 'ECSET_MAPPING_ERROR& o, v" ?2 O3 z( S0 }6 |; w4 ]
938281 SIP_RF OTHER export_chips creating bad data when symbol is split and contains V- V+ pins
0 g* R; q) t( X938812 ALLEGRO_EDITOR SYMBOL Cannot create a BSM with this DRA, errors out but does not state a reason.
l; o; e+ Z/ C939075 CAPTURE TCL_INTERFACE Texts are getting garbled in command window
0 u& Q5 J+ ~5 @1 _( |. j939193 F2B PACKAGERXL ERROR(SPCODD-439): Connectivity server is unable to load the design.
+ j7 L1 e7 [) E$ E939199 CONCEPT_HDL DOC "Retain electrical constraint on net" mismatch between schematic (YES) and design (NO)
' }; A- d! J& ?3 {' ]939346 ALLEGRO_EDITOR SHAPE Shape disappears when updating with variable shape_rki_autoclip set.
7 ^# x! o) i8 \3 D( X2 @939901 CONCEPT_HDL INFRA NET_SPACING_TYPE shows �?� on lower hierarchy level nets after Upreving to 16.5 version., a. [+ k& i' X. | ]% j
939918 PSPICE PROBE Print > Preview for output file causes Pspice crash.8 v: k/ [9 h* Z) u% ~, _
940217 CONCEPT_HDL COMP_BROWSER UCB reports 'No Symbol found for the part'" _5 y. J- B; ?% O) E$ a `
940835 CONCEPT_HDL INFRA Desing package different after uprev to 16.5 where comp instance propeties are lost lost" Z8 v( L+ d9 N8 I
941125 ALLEGRO_EDITOR DATABASE Performance advisor doesn't skip non plated slot padstacks
; B5 X/ l, x. U* u941876 SIG_INTEGRITY OTHER Illegal model name cause pxl fail in 16.3
0 }' _ p* d4 e1 @' i; ~942210 SCM OTHER Is the Project File argument is being correctly passed?
* X' W& C5 n# e/ S# n0 |( K+ O942274 CAPTURE PROJECT_MANAGER Crash on renaming a Design Cache part in Project Manage after doing replace cache
6 _; P% y7 ?% ?9 @ Y942839 ALLEGRO_EDITOR GRAPHICS Graphics Issue- Pads are not visible) w9 P# L* r1 O0 D/ [
943055 ALLEGRO_EDITOR SKILL axlDBCreatePropDictEntry causes application to crash, Q0 r8 }5 @: Z- _
6 G, m9 v7 I$ u8 l' E! Q: G5 t) \
DATE: 10-21-2011 HOTFIX VERSION: 007
% a" I Y( E* ~+ |, c2 @===================================================================================================================================& O, V- a8 g. y. x1 U i$ D
CCRID PRODUCT PRODUCTLEVEL2 TITLE5 Z5 |2 t/ |/ E; M
===================================================================================================================================0 S. q: Z7 ?0 V
841096 APD WIREBOND Function required which to check wire not in die pad center.2 U5 L9 d4 P2 u0 ]; h
903263 CAPTURE SCHEMATIC_EDITOR ENH: Selecting parent netgroup must select the underlying netgroup bits.) _) u& q* }) K
906692 ADW LRM LRM window is always in front when opening a project! I1 w" s- a" [) P6 B+ F6 R
912942 APD WIREBOND constraint driven wire bonding
) k3 f! r8 x) T: c912951 CONCEPT_HDL CONSTRAINT_MGR Need to manage temporary files on Linux systems
H/ f7 E+ g! ^5 z' G' p915178 SIP_LAYOUT DIE_STACK_EDITOR Die Pad names changing when updating Die in a design# P# a: a- K6 |$ a
917887 PCB_LIBRARIAN VERIFICATION Part should not be released if the alt_symbols has errors
: E; q; ?; \! ]! Y$ v7 }2 j923315 SIG_INTEGRITY GEOMETRY_EXTRACT crosstalk simulation fails with TMP popup failure
/ S6 t6 \" M; F( H3 ~. X; L927382 CONCEPT_HDL CHECKPLUS 'Verify Symbol' forces the use of 'Concept_HDL_Studio' license
! z3 M/ u7 R5 I' `2 e. H% u927664 CONCEPT_HDL CONSTRAINT_MGR Internal Error disposeipsp8 i! a! J2 Y; v. U5 d# i
930152 CAPTURE NETGROUPS Scalar net names when being connected to net group overlap when connections are made one by one% m8 K) N. M8 ?: M
930180 CIS LINK_DATABASE_PA Visible property position on schematic get reset on "link database part" operation
' E8 Z5 q; s3 g0 K8 b5 Y930188 CAPTURE DATABASE Capture 16.5 crashes in being re-invoked.2 [% C( P" V3 Y) [5 Z
930541 CAPTURE NETGROUPS NETGROUP element renaming doesn' renames the associated net ?
) M2 J* Y) o- z+ w" E930866 PDN_ANALYSIS SETUP OrCAD PCB SI Session crashes when we open PDN Analysis with "OrCAD PCB SI" license. n% b+ g3 ?8 P! j" F+ k! ]; [
930926 ALLEGRO_EDITOR GRAPHICS Via and Holes not visible eventhough set to Visible in Color form
. I8 B% @# u0 m9 T j931274 ALLEGRO_EDITOR DRC_CONSTR Negative Plane Islands waived DRCs reappear after performing update DRC.2 g% L+ A- w/ u
932091 CONCEPT_HDL CORE Prop attached to SIG_NAME property
5 b9 k+ \( w: ?# U8 {932255 ALLEGRO_EDITOR GRAPHICS Change in Zoom level makes arc segment to disappear
$ h( C- l. j+ \932292 ADW LRM LRM crashes during Update operation on a customer design0 G T5 _" w8 A2 \
932639 SIG_INTEGRITY OTHER Add Connect command hangs for about 14 seconds and then returns.
5 I6 e) Y/ f! q932704 APD DEGASSING Shape > Degass never finishes on large GND plane! N- N" D0 I# P0 ^9 m" i
932871 APD GRAPHICS could not see cursor as infinite
' ^' v9 y3 U, j5 c3 _932882 CAPTURE SCHEMATIC_EDITOR Capture crash with FIND command - ISR05
, f. d" B: O3 x7 z+ C4 H+ ]. R932969 CONCEPT_HDL CORE ConceptHDL crashes when you save the design in 165 > hotfix #05
: t/ G4 A" e) c# d. _# O" D933024 CAPTURE NETGROUPS Naming restrictions for NetGroup members6 \/ A ~5 x1 {- o1 T6 a+ \
933145 F2B PACKAGERXL Add Subdesign list is truncated in Force SubDesign Design Name pulldown
/ E' l6 \) ?6 p0 f+ N8 `! `933214 APD ARTWORK Film area report is larger when fillets are removed
6 v7 ~3 J* T" C( _, O# `- O# R933356 CONCEPT_HDL CORE Net prop display size become 0 if it was attached to SIG_NAME prop.- j; Q2 Z; C+ ^9 {! |8 A* y
933532 ALLEGRO_EDITOR COLOR Bad color assign and initialisation during creation of new subclass
3 E* p9 O7 Z- @ @933549 ALLEGRO_EDITOR OTHER Chart text missing in export PDF file.! W! C( q; |/ J* Q: b
934008 ALLEGRO_EDITOR REFRESH refresh symbol updates symbol text to some unexpected values
5 z: d# V/ y% {; H934031 ALLEGRO_EDITOR DRC_CONSTR Bug : Update DRC removes Waived status for some DRCs
% d3 z6 R3 d9 x: f. G1 W8 c+ D" Y934087 CONCEPT_HDL CORE Opening DEHDL and Model Assignment before design loads causes crash F* r0 j% o: j; ]: \
934396 CAPTURE SCHEMATIC_EDITOR Find operation is not searching power symbols with + or - signs.$ \% h4 l( J `* K" g) _+ h; w/ P, z
934533 F2B DESIGNVARI The Variant Editor errors are not written to the variants.lst file
9 N6 O: v; N. k" i8 ]" j934811 SIP_LAYOUT UI_FORMS CDNSIP should not hang if contraction value in z-copy command is out-of-bound7 P* A) |+ o3 s* y% Z' P2 F- {0 N* e
934909 SCM UI Require support for running script on loading a design in SCM
* |- ?/ s* M5 G; D935632 CAPTURE SCHEMATIC_EDITOR SHIFT+Mouse wheel scroll(horizontal) of page is not working in Auto Wire Mode.
4 P- d7 j/ g0 W9 n; ^935794 ALLEGRO_EDITOR SHAPE BUG:Shape not filled in 16.5 but it does in 16.3( e. S- s, @6 E+ l% ~9 b
935988 ALLEGRO_EDITOR INTERFACES When attempting to downrev this 16.5 design to 16.3 the tool will crash c; S8 H$ q) Q1 H, v7 I# u
936056 ALLEGRO_EDITOR DRC_CONSTR place_manual crash while moving mirrrored symbol
& E2 P0 R- [+ h1 x& k( G+ p" ?936098 ALLEGRO_EDITOR SKILL axlDBCreateCloseShape does not work correctly.% ~5 m* D8 @ f& C; c
936212 ALLEGRO_EDITOR INTERFACES DXF not created if Blocks created for Symbol and padstack
) _5 i3 j. \" O' }2 d/ L936797 CONCEPT_HDL COPY_PROJECT Copy Project crash
" E) y8 h) A, |0 e& w" @8 I5 X" Y936808 ALLEGRO_EDITOR DATABASE Allegro crash replace mechanical symbol! c$ ?% r& ^/ ?0 b. Y: H
936853 CONCEPT_HDL CONSTRAINT_MGR DEHDL crashes when trying to extract net from CM
$ I% ?. F) B3 b0 r+ D3 b6 t6 {937087 CIS DESIGN_VARIANT Upreved design becomes very slow in Variant view mode. DELEET THE DESIGN AFTER RESOLVING THE ISSUE3 n! T9 P' T5 k7 G, T& [0 [" y- x
937173 CAPTURE OTHER Wrong license information "UNLICENSED" in Capture >> Help >> About3 c7 A6 E k% s5 S
937290 APD PLATING_BAR Plating Bar checks does not recognize connection made through etchback through shape.
E' S! f/ [4 u! b: z6 L937411 ALLEGRO_EDITOR DATABASE downrev_library reading from one directory and writing to another hangs the command.' ^0 M+ _/ K) k, o( f/ T
938235 SIP_LAYOUT STREAM_IF Die Orientation is not correct after importing a stream file.
! U) t: ~: |" e5 \; z8 a2 l938273 ALLEGRO_EDITOR OTHER PDF export is is not opening viewer with ads_sdlog variable set
O- E- E( H% G1 c1 b- \8 e/ [) X8 v) x- |
DATE: 09-16-2011 HOTFIX VERSION: 006
! S; h9 {8 ^, h q ]===================================================================================================================================1 t: U% J& ?' L: r7 t0 B9 g+ s
CCRID PRODUCT PRODUCTLEVEL2 TITLE( Y' U3 U# S* |$ L9 ?, b# J6 g
===================================================================================================================================, z" ~2 q7 ^4 p& U
820131 CONCEPT_HDL OTHER Moving symbols to other page will make Allegro components unplaced because logical_path changed.
$ b4 t6 Y. \) {9 z6 H863860 CONSTRAINT_MGR SCHEM_FTB CM should display or Local Interface and Global nets to help defining low level constraints
! ^2 m& F9 M: a9 h2 t, j Z& k: ^8 t919822 TDA CORE Cannot configure LDAP to only list the login name
) `' _+ S5 X( V1 k1 ~' a7 X922907 ADW TDA 搇ast_callout_file� directive in the BOM section is empty causes tda for show Access Denied error I5 A% a; K p4 F3 N* k
924322 ADW COMPONENT_BROWSE Random - No instance properties are added on Add To Design (RMB or double click) from Search Results
) g- B7 p3 A, e( R% }- u: X924448 F2B DESIGNVARI Design does not complete variant annotation
$ m" {2 G0 P" s- |925584 CONSTRAINT_MGR SCHEM_FTB 16.3 upreved Design passes the SLOT/Function Properties to PCB
. G1 R' ]' J! f- K927102 ALLEGRO_EDITOR OTHER Question of Conductor Detailed Length Report
; b7 n: t' O" y1 H( X8 F927104 F2B DESIGNVARI Tools > Annotate variants crashes when there are ASCII characters in the property values
! k8 ?2 @8 W5 R& }9 [927142 F2B DESIGNVARI Incorrect pop up asking while executing variant editor from the command line
) A# [* t- f b* B( r; p( B& H927166 CAPTURE NETLIST_ALLEGRO ENH: Feature like NET_SHORT in Capture Allegro flow which allows user to short 2 or more power nets
$ q" Y3 J) L4 s% q2 \3 K927410 ALLEGRO_EDITOR DATABASE ERROR(SPMHUT-144): Illegal arc specification error when Run DBDoctor
4 i: a8 C8 r- @3 W! P927475 CONCEPT_HDL CORE About forcereset command of nconcepthdl: w K, N7 s* e. v# m. [& `3 O
927498 CONCEPT_HDL CORE Pin_Name starting with minus causes incorrect behavior for $PN display, _! c' _. T4 F0 x1 E8 d7 ^/ z
927608 ALLEGRO_EDITOR PADS_IN Import PADs fails with error message: Failed to close the Allegro database
4 B3 q" g0 a, @" B0 e# l9 l927637 SCM CONSTRAINT_MGR ASA crashes on change root and also performance is too slow.+ W* L) C8 z- z' k" ?
928429 SIG_INTEGRITY OTHER Request - Package Wizard to work in PCB SI.
X* ^2 S6 y$ `0 z* o, ~928483 ALLEGRO_EDITOR DRC_CONSTR Running Update DRC removes Via List DRC Error when via is actually not in the list( z7 j1 k4 A0 d' Y9 J B
928738 PSPICE PROBE Y-axis grid settings for multiple plots
: t, H/ j4 o/ {9 C4 Q6 u% V6 p7 Z y B928748 PSPICE PROBE Cursor width settings not saved
8 q e M9 \9 H! N3 y928779 CONCEPT_HDL CORE Error (1053) occurs on a copied part in SPB165 release
* _8 F! Y0 ?' }" l+ U4 q& f$ f7 {: @928838 CONCEPT_HDL CONSTRAINT_MGR ECSets not migrated in 16.5, \. [7 Z# v0 h0 I
928885 SIG_EXPLORER EXTRACTTOP PCB SI crashes when extracting a net from Probe9 \5 a( C6 k* w! }( @; P
929284 CONCEPT_HDL ARCHIVER archive does not create a zip file
9 Z4 ]) E3 d+ q929542 SIP_LAYOUT DIE_ABSTRACT_IF net issue of multiple ports of co-design die in SiP
5 B, @3 z4 h5 q5 ~* _0 {: A- J ^929656 ALLEGRO_EDITOR PADS_IN PADS translation fails with Microsoft Visual C++ Runtime Library error! ]) _, f8 H1 K, E$ Q" S
930063 ALLEGRO_EDITOR TESTPREP Test prep crash Allego when it can not create pin escape
; [& ]# v) Q0 l% X3 d: g r+ u930217 CAPTURE NETGROUPS Net aliases doen't gets assigend to bus bits if bus name is checked in NETGROUP.0 l( z2 z, w8 x; L
930355 SIP_LAYOUT WIREBOND about "wirebond add nonstandard" command
0 _3 A3 I: }5 [8 k& w! l& S930607 APD OTHER Layer mapping information is reomved from Layer conversion file upon exporting DXF from board file.5 f7 S: h: ]+ L0 _! ?4 M" O2 ^8 S
930646 ALLEGRO_EDITOR DRAFTING Bug - Adding Linear Dimenstion for ISO standard add the Angle information as well8 L% p, ^( ~6 a+ p1 c0 S
930894 CAPTURE TCL_INTERFACE PDF export doesn't creates property file if some symbols are used in page name/folder name
1 } J' R/ Y( d6 N4 l1 ]& d) g% n930944 ALLEGRO_EDITOR OTHER Setting variable 'appmode' equal to 'none' is not changing the Application Mode when reinvoked
* n* B- o5 g' v# @9 g$ |1 y930978 ALLEGRO_EDITOR SCHEM_FTB 3rd party netin error - Pin is connected to net <netname> not reconnected no longer happens2 ~% _4 L6 s) Q% Z
931248 ALLEGRO_EDITOR DRC_CONSTR Match Group was removed if member nets became xnets.. M* Y& O- [" W) z' ?5 m4 x
931278 CONCEPT_HDL INFRA $PN gets copied when upreving design from 16.2 to 16.5 version1 |$ E0 X6 v' d. I% Q& @9 i% _5 j
931349 CONCEPT_HDL COMP_BROWSER DEHDL craches and corrupts connectivity file when using Modify command extensivly.
4 y8 g5 d2 G/ I4 A% l# ~
9 ?2 P, k# ?9 y8 k) Z& \( rDATE: 08-31-2011 HOTFIX VERSION: 005
+ `5 \ ^, T& I, j6 i/ [===================================================================================================================================, R& v" p/ d M N) f+ `+ {7 I
CCRID PRODUCT PRODUCTLEVEL2 TITLE
# x W6 d* P- }+ G) `( P; }===================================================================================================================================
# [' ]8 l) X& j/ j825848 ALLEGRO_EDITOR SHAPE Shape not filled when edges from 2 RKO shapes touch around mouting hole
% q% t+ m% ]' I4 R% L a837723 CAPTURE PROPERTY_EDITOR Occurrences of external design not related to current root should not show
# H/ k+ f, o( R o: V: p7 H891079 CONCEPT_HDL CORE DEHDL crashes with large number of commands in Winodws mode
6 o7 t, O. K1 I8 C5 b910908 SIG_EXPLORER OTHER Cannot open top if Tx AMI dll name contain more than 2 dot.& o0 d' Q2 k' b6 A8 Y* e
914036 CAPTURE LIBRARY ENH: Option to delete a corrupted part from a library and leaving other parts intact in the library.
9 `- D! D f5 q7 N914679 ALLEGRO_EDITOR INTERACTIV Custom toolbars are not retained when switching between brd to dra and back to brd file using the File > Recent Designs
1 c" I& C1 S; z" y! L ?914870 MODEL_INTEGRIT OTHER mergedml fails to merger 2 DML files from the model integrity
$ j) e9 @: C- g, \9 d2 a7 r( y& Z915645 ALLEGRO_EDITOR MANUFACT Allow the user to place the cross-section chart at a desired location; r* T& C6 B% a8 O
915653 ALLEGRO_EDITOR INTERACTIV unable to delete non-etch shape* G# u: C+ H4 }- c* v0 X ]. c
915711 ALLEGRO_EDITOR MANUFACT dimensioning tolerancing by limit not working
+ x: a4 F6 n6 U: @916321 CAPTURE GEN_BOM letter limitation in include file
& o) T' H9 y( w6 P9 l6 `6 f& z916907 CAPTURE SCHEMATICS 揂uto Connect to Bus� should place the wire through non-connectivity objects
0 o- f7 E. m; H# g$ a# j920327 CONSTRAINT_MGR ANALYSIS The TotalEtchLength predicate in Constraint Manager does not work for a netclass with a bus.. \5 G [/ r4 x4 S' Q0 o
920753 ALLEGRO_EDITOR GRAPHICS If I confirm to padshape with zoom-in after install the s002 It was changed to wrong shape.* L+ D0 Z* b y* p% m7 S' n) b8 A. E
921097 ALLEGRO_EDITOR GRAPHICS Padstack seen partail filled when Zoomed in even "static_shapes_fill_solid" is set
* A4 h% S9 M9 g* F8 j1 B921226 ALLEGRO_EDITOR DRAFTING Unable to select Package Geometry class when dimensioning in the symbol editor.
. T9 G; ]* K& L, L. O# d921623 ALLEGRO_EDITOR GRAPHICS Bug : Symbol not visible when zoomed in 16.5 S002, w- X2 {5 ~: C- W' q2 ^( ~6 U
921891 ALLEGRO_EDITOR DRAFTING dimensions are lost after downrev(ing) a SPB 16.5 design with associative dimensions
% G* _6 Q# T2 x/ A, L; G7 C921937 ALLEGRO_EDITOR COLOR Padstacks with shape symbol are not showing correctly# d$ v/ l- w+ ^7 g V l
922066 CONSTRAINT_MGR ANALYSIS Custom measurement Actual not being cleared when layout changes.3 D/ i5 x! K' |3 w
922117 PSPICE PROBE Label colors are not correct in Probe
$ {8 g1 S$ n, l1 _, _9 P3 S# |922519 ALLEGRO_EDITOR SKILL add_bviaarray command fails for some clines but not all
- f; {) n/ l) n7 y; I$ y0 ~923224 ALLEGRO_EDITOR GRAPHICS Thermal flash Display problem in Allegro v16.5 Hotfix S002
e5 @* b8 G& I3 i923286 CAPTURE DRC DRC markers not reported for undefined RefDes7 W9 z# u9 P% |4 W
923362 ALLEGRO_EDITOR PLOTTING Print to Postscript file not correct in 16.5) n7 r1 [& U" y! Y! h* w& }
923416 ALLEGRO_EDITOR PAD_EDITOR Pad Designer crash on clicking on the Arrow before Soldermask_top, P" p L( H- q
923507 CONCEPT_HDL CONCEPT-PCBDW The function of Import Design in the SPB16.5 Design Entry HDL (for data of ADW15.5_S23 + SPB16.3)
2 b. x3 H. _8 E- P* a# {923910 CIS PART_MANAGER Copy & Paste operation from Part Manager copies properties only to first section of the part.) F% }" {% ~0 t9 \9 n
923913 CAPTURE PROJECT_MANAGER Capture runs slow on attached design
8 |4 \$ l' @/ H: x: k, K( F+ Q6 D+ X923937 CONCEPT_HDL CORE Back annotation time significantly increased with the metadata generation on
5 i: y! i7 o) p) W+ f3 [923949 ALLEGRO_EDITOR INTERFACES Incremental DXF_IN gives 'Invalid subclass' error L. R4 W8 ~" K7 p( h! B6 @
924458 SCM OTHER Project > Export > Schematics crashes
, y# o5 ]6 l* k+ V924621 ALLEGRO_EDITOR SHAPE Dynamic shapes are disappearing upon updating them to smooth.
7 h: e% m) L9 i8 _1 |+ q925193 SIG_INTEGRITY FIELD_SOLVERS Diffential Impedance (DiffZ0) values computed in the layer stack-up is incorrect) {+ W" Z( B1 H
925195 ALLEGRO_EDITOR DRC_CONSTR Incorrect pin to shape DRC error
- @# X8 D0 p: H2 k8 O. h/ M( a925338 CONCEPT_HDL CORE This application has requested the Runtime to terminate it in an unusual way
( N7 _2 ^" p, y" h1 @925435 CAPTURE TCL_INTERFACE Capture crashes if 揝ave design as UPPERCASE� option is disabled.
; Z7 D2 k+ C% S2 n925530 SIG_INTEGRITY OTHER Why the single line impedance value for Top and Bottom layers are different for this design?
% d Y) D. P( h' z2 r8 s925864 ALLEGRO_EDITOR DRAFTING Ability to add dimensioning to different CLASS/SUBCLASS
/ h3 M p9 N+ C2 z: I925976 ALLEGRO_EDITOR MENTOR mbs2brd fails to import data
& m+ P" \8 {) ?, |926409 SIP_LAYOUT DRAFTING Exporting a 16.5 design to 16.3 will cause the leader/dimesion lines to be removed.
, U% h! R8 o A" C1 A3 J1 D926443 CONCEPT_HDL CONSTRAINT_MGR In new 16.3 "035" ISR Concept2cm will crash with error.
, ~/ E) |6 _6 M9 ~ |+ J- T926503 CAPTURE GENERAL Memory leak Capture/Pspice
& A" h2 @/ l! }% a1 a926553 CONCEPT_HDL CONSTRAINT_MGR CMGR ERROR There is no net in the Cset that has pins matching those in net 1 in the Xnet" E7 T) S9 [' T6 N! C
926691 ALLEGRO_EDITOR OTHER Crash while Importing Technology File in CM, with Overwrite Constraints.3 N k/ g% d+ C4 ?6 H; B: Z
926887 CONSTRAINT_MGR CONCEPT_HDL Pin pairs lost after Export Physical0 M% x) \8 ?2 i# @( L
927159 CONCEPT_HDL CONSTRAINT_MGR Export Physical fails due to errors in ConCM.log when SIGNAL_MODEL injected property is ''+ v6 k! c& k, a8 E
4 x$ ~% J: q4 lDATE: 08-19-2011 HOTFIX VERSION: 004
) Y; A( p# S" I8 A. B, n: m===================================================================================================================================' I; H8 e/ H" c* x o- l
CCRID PRODUCT PRODUCTLEVEL2 TITLE
; y/ p& n4 j* T2 ?===================================================================================================================================7 b. X2 h$ l: s7 C) p6 w
785417 CONCEPT_HDL COPY_PROJECT copyprojectui crashes with a Windows runtime error
8 a8 b) A' F. F( D5 v# N3 {1 X851044 CAPTURE GEN_BOM "Export BOM report to Excel" does not appear in the Standard Bill of Material Window.- m! T5 K- V G3 H
868216 PSPICE MODELEDITOR Encryption of subckt names, internal nodes, comments
3 O) {* `, p' T- N# d0 s K870247 PSPICE SIMULATOR Encrypt a model and simulate it, info about inside nodes being dumped in the probe file
9 D0 _5 m+ z/ d: U/ z! S5 H- L! h0 h877091 CAPTURE SCHEMATICS Save JPEG, GIF, PNG and other image formats in the database in its compressed form4 y$ H" Z( p9 |! |" w
894059 CAPTURE OTHER Enhancement: Adding column in edit>browse>parts window9 G& O/ [$ P* ^
895902 RF_PCB OTHER Alphanumerical allegro pin numbers are unusable in ADS 2009 Update 1
2 g* o9 E, t$ H4 }. }; J895919 RF_PCB OTHER Round trip Allegro to ADS to Allegro requirement
2 v/ S* Z, g; b5 r0 D+ F4 ?) f903102 ALLEGRO_EDITOR OTHER Zcopy shape command for cline seems not to work correctly.
/ u5 u c4 h) v7 ^+ j8 T905562 SIG_INTEGRITY SIGWAVE Noise margin seems not to be measured correctly with Eye Measure function.9 Z5 @2 e2 }& `/ C* r1 G1 V0 |
909469 SCM TABLE ASA crashes when opening project' n; t+ n% N- D3 b7 }: c
909595 APD LOGIC Inconsistency between export die text out and show element after pin swap5 K/ Q9 _: S9 N) B+ V6 Z% V( t9 J
911123 CONCEPT_HDL CORE 16.2 Design uprev to 16.5 fails with ERROR SPCOCD-152& M! v4 {8 Z/ v/ x( o
911569 CAPTURE EE_INTERSHEET_RE Q: Why is capture assigning incorrect Irefs in attacehd design ?6 U* a- c2 [3 G) c5 t
915657 ALLEGRO_EDITOR OTHER Allegro PDF Publisher Mirror capability
# z: I( k. N2 R( ~9 c- q915755 CONCEPT_HDL CONSTRAINT_MGR Cannot view net in SigXP M; K; m6 a" m3 o+ q8 T! Z
916062 CAPTURE GENERAL Auto Wire Crashes Capture+ B' N2 Q$ {+ S' x0 D5 h
916820 F2B OTHER RF create netlist with problem
- }' ^0 M4 d' d# c3 S1 R917967 ALLEGRO_EDITOR REFRESH Update symbol resets refdes location for bottom side components only.5 `: e4 ?9 |7 x5 D: e0 ^
919343 ALLEGRO_EDITOR PLACEMENT Place Manual is crashing the board file- `2 J* q: Z6 ~. j
919481 CONCEPT_HDL CHECKPLUS CheckPlus isGlobal function is not working+ Y" c1 X; {) s/ v8 j- `( X
919510 CONCEPT_HDL PAGE_MGMT takes 10 min to insert page in DE HDL9 W- U: R2 k, {* e7 [0 t! T, x- @
919976 APD DATABASE Update Padstack to design crashed APD." x' v8 b" b5 w* [/ ^
920418 SIP_LAYOUT OTHER SiP enhancement to Auto Assign Pin Use to add ability to change the pin use definition
$ _7 S7 Z+ z0 \+ |920420 SIP_LAYOUT LOGIC SiP enhancement to Logic Auto Assign Net to display a dialouge Auto Pin Use assignment should be run8 ]5 x7 |1 ^2 g4 e$ b2 `
920712 ALLEGRO_EDITOR ARTWORK Program has encountered a problem ... error when creating artwork
% m+ G0 C' g, b0 j0 E* t920763 ALLEGRO_EDITOR ARTWORK Soldermask gerber missing thru-hole pins8 G+ T6 W3 G2 d/ ~, _) M
920976 ALLEGRO_EDITOR GRAPHICS Question regarding the difference in the behavior of 3D Viewer w.r.t. height_min
/ K$ w- L/ P" D; v# q$ G& R920993 ALLEGRO_EDITOR DRC_CONSTR Minimum Metal Spacing Error is detected on Same Net/ Q* E* S2 d2 Q9 c! D' _
921727 ALLEGRO_EDITOR DRC_CONSTR Pad Boundary causing P/P drc to adjacent symbol.( v; [' j# q3 i9 y( |
922579 CONCEPT_HDL CORE Xcon file gets corrupted upon Save of Hierarchical design with Global nets tied to interface nets
" f8 X: `- w1 l$ W6 W922592 CONCEPT_HDL CORE DE-HDL does not report illegal connection when Global Net tied to interface net using an Port symbol and named
) Y8 D+ H& B" P/ l- }& s; u922758 ALLEGRO_EDITOR DATABASE Allegro crashes while placing second mechanical symbol with route keepin6 h( w3 V# K! j4 z# b
922839 ALLEGRO_EDITOR DFA The DFA drc display is unstable.. M/ v# f" Y6 `5 e, e
923293 ALLEGRO_EDITOR INTERFACES File> Export> IDX is failing for this design while creating an empty error log.9 s" ~& v& s+ f' T
924772 ADW PCBCACHE Import Sheet is not bringing in Parts used in the source pages into target cache ptf- \* Y* S4 [# c& \8 v( ^
2 }8 ^ l& k9 [8 @( y
DATE: 08-4-2011 HOTFIX VERSION: 003# O6 e" U! j! L& a# ~
===================================================================================================================================
& o. r8 m/ x: S- x# g/ x0 zCCRID PRODUCT PRODUCTLEVEL2 TITLE2 I* ~; d- D0 y7 ?
===================================================================================================================================% V0 t6 m/ p; u# L9 x% a% r: V
787414 CAPTURE PROPERTY_EDITOR Part value can抰 be moved on schematic if a part has been copied to a new design and not saved yet.
$ \6 z7 c+ n8 v6 ?4 Z903898 PCB_LIBRARIAN GRAPHICAL_EDITOR PDV move symbol graphics and Undo causes corruption in graphics
. V- ~1 Z1 M6 r# y904287 ALLEGRO_EDITOR ARTWORK some cline with arc is missed, when creating artwork.+ i5 z. v4 h+ T* C0 |4 v( Z- i
904418 CHANNEL_ANALYS SIMULATION channel analysis sim does not give valid result$ j; c' }- u2 r+ r( E2 K O7 o) n
905777 SIG_INTEGRITY SIMULATION User gets popup message that halts an analysis until it is acknowledged* L5 h7 t6 ^3 i/ t9 ]; A
906139 SIG_INTEGRITY OTHER Bus sim result were cleared at the next run even if no preference changed.
; Y/ B9 s" i: v( r908680 SIG_INTEGRITY OTHER Extra prop delay due to resistance/ u' I8 {% q$ Y+ N+ m4 \
909583 ALLEGRO_EDITOR SKILL axlPolyOperation AND operation is not working correctly., G: ]' ~6 _) H) j' H
910315 ADW LRM Import Design with ADW causes partmgr and pxl errors7 Q, m$ R4 A8 d& E" H# m5 Z
910689 CONCEPT_HDL CONSTRAINT_MGR NO_SWAP_COMP warning after uprev to 16.56 m% x* m) }0 x" ]; Y1 D7 c
911684 CONCEPT_HDL CONSTRAINT_MGR Attribute Definitions are incompatible for attribute 'HEADER'. when attempting to place in 16.5- K3 P9 G1 T# v0 c8 h- r. o
912343 APD OTHER APD crash on trying to modify the padstack
+ p+ d! @2 w7 |+ v( P912384 PCB_LIBRARIAN CORE PDV Symbol Editor often freezes when moving groups objects by arrow keys* A4 f; H1 T1 \0 h z
912853 APD OTHER Fillets lost when open in 16.3.
7 ]3 D, v' T" |0 i* M913586 ALLEGRO_EDITOR ARTWORK Cannot create the drill figures in this design.2 q: y) l; i5 }7 V, H
914009 ALLEGRO_EDITOR DRC_CONSTR Diff impedance worksheet showing almost zero impedance for differential pair in attached testcase.
3 y V, L! [6 G; l0 d1 o: i$ x$ W914110 CONCEPT_HDL OTHER DEHDL 16.5 Uprev overides property values on hierachical blocks) _' t4 o# A# ?/ x2 [7 `
914264 F2B OTHER Cross Probing from DEHDL for global nets present inside block doesn抰 highlight in PCB Editor.3 D- Y9 j0 X s. b% K# ?7 ?
914309 CONCEPT_HDL CORE 16.5 DEHDL crash on saving the user design+ Y" s% f% [, Y7 D: L; u$ l
914558 ALLEGRO_EDITOR ARTWORK Gerber6x00 output creates unpainted niche in a shape
( s) U/ y: @2 Z2 b$ }914633 ALLEGRO_EDITOR ARTWORK Artwork failing in v16.5 while the same design when downrev'd to 16.3 is working fine.9 v6 C: v/ ?4 w( c% L1 u
914634 ALLEGRO_EDITOR SKILL IsThrough flag for a padstack is reset* Y. b( |2 {; `( J' P
914746 ALLEGRO_EDITOR DRC_CONSTR DRC Update repeats takes longer on each successive pass.
2 q, f5 e/ c Z9 E914962 ALLEGRO_EDITOR SHAPE Corruption with Shape filling
8 t: V% `6 t# g6 {) Z7 z- L. c915583 CONCEPT_HDL CORE performance issues in 16.5 compared to 16.3
; ?1 q) X4 ~3 Q i) i" I915630 PCB_LIBRARIAN OTHER Error when running SI Model Interface Comparison using IBIS models
9 t/ R. R1 j: S% L, ]/ r$ ]915742 CONCEPT_HDL HDLDIRECT I get a newgenasym error and crash when trying to save the symbol
; J0 q+ Q2 L9 b, }916154 SCM NETLISTER scm crashes when exporting physical database to allegro
4 \9 m4 f; X0 h916448 CAPTURE NETLIST_LAYOUT Capture 16.5 Layout netlist contains errors
" [) s2 w5 }0 F# d8 z2 s6 l2 g H916462 ALLEGRO_EDITOR DATABASE Edit>Split_plane>create hangs Allgro PCB Editor( G# ~! M+ k! ?
916469 ALLEGRO_EDITOR REPORTS One Unrouted pin does not show in Unconnected Pins Report
- N) F$ t/ p8 [/ ]+ t' V$ M916495 ALLEGRO_EDITOR INTERACTIV Pick selects components from invisible (Off ) layer( x& S" F& n# r
916889 CAPTURE NETGROUPS How to change unnamed net group name?) y& N7 [- v1 X$ ?' L+ H' b
917002 ALLEGRO_EDITOR OTHER Allegro PDF Publisher creates extra circles not available on film) o$ |# M5 o0 c7 c2 [" I' V
917434 APD OTHER Stream out GDSII has more pads in output data.5 M$ X5 v7 x0 n7 M9 w/ g' L" \
917739 CONCEPT_HDL INFRA Global Net tied to port is getting split into 2 nets in 16.5, in 16.3 it is treated as a single net
7 v7 j# P3 p3 [918187 CONSTRAINT_MGR OTHER Missing acGetTotalEtchLength predicate.
" ~( l: Y" S# Z! X/ M+ u! i: P& h918576 CAPTURE DRC Incorrect DRC is reported for visible power pins which are connected to power symbol! F2 L1 c& ~) h% V% M
" w: i, J# L0 K H$ H& R
DATE: 07-24-2011 HOTFIX VERSION: 002
* r; G; T% u( e0 T( W& j) s. Q; m===================================================================================================================================5 [9 v Q: `. k8 b. J
CCRID PRODUCT PRODUCTLEVEL2 TITLE8 b1 ^$ p+ @3 ?. b
===================================================================================================================================4 g, w+ q( {: R: I) H. e
527444 ALLEGRO_EDITOR EDIT_ETCH Slide command needs to be enhanced for same net spacings# o' v& I( X, k6 x
583257 ALLEGRO_EDITOR EDIT_ETCH Add Connect and slide command needs to be enhanced for same net spacings.2 C/ B8 U: J) b* ~) S) \
592956 ALLEGRO_EDITOR EDIT_ETCH Same net traces will not push and/or shove each other.6 y; a) }/ `1 |
745285 ALLEGRO_EDITOR EDIT_ETCH Requesting a true "shove" in Route > Slide for Same net routing.
2 \$ O8 m3 X2 O4 w9 d773503 CAPTURE OTHER Doing "Mirror Horizontally" creates extra un-connects or extra junction dots in Capture V16.3.
/ Y) L7 c- b) y S$ _- x" h1 e7 H3 p774270 F2B PACKAGERXL Require to ignore space in Pattern setting to prevent duplicated Refdes.0 V. G, E. ?+ }! U8 a0 Z
799984 ALLEGRO_EDITOR INTERACTIV Enhance the Fix command to select just cline segs1 c1 c2 G+ e% u' C* f% H
809008 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".) \% ?0 h0 p j+ |! m! l! `
810058 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".
/ ]9 {+ c2 s1 L+ M* ?, e9 f821133 ALLEGRO_EDITOR MANUFACT Output artwork for pad data that are suppressed unconnected pads with Gerber 6x00 format& v5 ~* ~2 z- i3 t. w6 x
831710 CAPTURE SCHEMATIC_EDITOR Capture adds extra junctions to design by itself. F) K0 P- Q( `. Q) J; @
842410 ALLEGRO_EDITOR EDIT_ETCH Ability to slide with "Shove" for "Same Net" segments/vias.# U, m$ I3 o9 a! r# V& \
854971 ALLEGRO_EDITOR INTERACTIV Capability to add cline segment in a temp group4 g# o# L; L. |9 _$ S3 |/ b
860772 ADW PCBCACHE Save Shopping Cart (pcbcache) is crashing component browser
1 E* L, O) ~2 R+ L. K8 f6 b867842 CAPTURE PROJECT_MANAGER Capture crash with 'Open File Location"
W& r% F) }6 d- w868306 CAPTURE CONNECTIVITY mirror vertically removes junction creates extra nets+ J* G8 g- s3 }: h1 G& s: x: j
882677 EMI RULE_CHECK bypass_plane_split fail if BYPASS_XXXX_EFFECT_DISTANCE
- g% u0 Q# h3 _: J891439 ALLEGRO_EDITOR INTERACTIV moving cline segments0 L! I/ L1 a( K3 I1 C9 `9 v$ D4 w
893544 ALLEGRO_EDITOR INTERFACES IPC-D-356A netlist issue with BB vias.
0 y" I2 Z' l% z, c893765 ALLEGRO_EDITOR PARTITION Mail command not sending out email on Linux platforms.- X" O& {$ `! V2 m$ K; G
894390 SIP_LAYOUT EXPORT_DATA Generate all balls in the xml file for export to EDI's readPackage command7 l! c, ~0 I+ x6 v
895933 APD DATABASE Update Symbol shifts the center of the Dynamic Fillet and creating DRCs
5 n- w% v/ q ?0 j" u9 `! P- Z896598 ALLEGRO_EDITOR PLACEMENT error message is misleading
6 \! m5 f9 n. C+ c$ a897196 CIS LINK_DATABASE_PA Schematic Contents are not shown in CIS window while link Dbase part for parts placed from library
# ?4 x, j6 ]# P' K+ ]; c0 y5 k898598 ALLEGRO_EDITOR MENTOR Negative planes from Mentor Board Station not being translated.
, @6 Y) E0 ~" {$ C) d9 E% i899556 ALLEGRO_EDITOR ARTWORK Import artwork seems not to work correctly.
! d$ i8 x: Y, a- ~: i; r( d900501 ALLEGRO_EDITOR PLACEMENT "lace Replicate Apply" is showing lot of DRC's during placement of replicated circuit in 16.5& x. n3 w3 X) W
901141 CIS EXPLORER Japanese character appear garbled in CIS explorer window. G) U, `. i8 y' x# M
901666 CAPTURE OTHER Home page of Flowcad-Switzerland and Flowcal-Poland is not preserved on captre restart on start page
g U6 @& j+ m& U. A9 ]902066 ALLEGRO_EDITOR DRC_CONSTR Shape in Region not follow the constrains
" `7 W' L6 j7 p; s& K6 A902349 CAPTURE LIBRARY Capture crashes while closing library4 r0 W1 R5 B1 D x8 v9 H# S0 m2 Y
902508 F2B PACKAGERXL SPB16.5 Packager-XL consumes much more memory than 16.30 G: W! f3 j6 R3 [1 D! O7 @" D
902841 CAPTURE GENERAL Capture Start page does not show5 F, R: q$ i0 S: V" c
902876 F2B PACKAGERXL Packager fails on the design upreved in 16.5
3 F- G; G4 i6 M' m! W902959 CONCEPT_HDL HDLDIRECT HDLDirect Error while saving design! }( ]0 e' o2 L9 R; s. r, e2 a! t
903171 PSPICE NETLISTER Why Capture is treating hierarchical power ports as floting nets in complex heirarchy designs?* S( t% \/ n7 z
903713 ALLEGRO_EDITOR PARTITION Placement Replication do not work fine in the Design Partition/ h J. O/ x" D) `
903799 SIP_LAYOUT DIE_EDITOR Disappear die pins after exiting co-design die editor
6 C: f9 N# v/ x. x. H& S2 M904021 ALLEGRO_EDITOR OTHER Export PDF from SPB 16.5 produces a file not text searchable
: G. c0 P4 X/ k" s. y X' |" k904339 CONCEPT_HDL CORE new design crashes using the attached CDS_SITE2 P8 p" H- t# Q$ g: ?! N
904522 F2B PACKAGERXL Part will not package in 16.5 but packages in 16.3
& \( \) {3 {- i- x) _904764 APD OTHER Enhance Scale Factor of Stream Out to support 4 decimal places/ A: n& K6 E9 M. h* G
904771 ALLEGRO_EDITOR MANUFACT Pin Number display issue.
! D9 @4 h/ B) n, z904853 ALLEGRO_EDITOR GRAPHICS Enhancement for showing Static shape as it was seen in 16.3* d2 c% q7 R8 {& U7 U
905144 CONSTRAINT_MGR ECS_APPLY Min Line Spacing is larger than Primary or Neck Gap less(-) Tolerance but No Warning in CM
2 }8 w8 \: h! c, D3 J0 T905314 F2B PACKAGERXL Import physical causes csb corruption: Y3 q9 b" f/ {; j* t
905337 CONCEPT_HDL CORE ConceptHDL crashes after Import Design process. i n. h1 L2 n7 B) p, B( Y
905533 ALLEGRO_EDITOR INTERACTIV Pin numbers for components on BOTTOM Side are moved in Preselect mode,when the BOTTOM layer is invisible
; {3 U- I A4 H; `8 F905796 CONCEPT_HDL CONSTRAINT_MGR Fujitsu CM issue inaccurate concept2cm diff pair issues& y$ X/ }1 T2 e
905811 CAPTURE EE_INTERSHEET_RE interesheet references in the form of grid grid page number instead of page number grid
: p; W$ t H/ }, ~4 i906118 CONCEPT_HDL CONSTRAINT_MGR Cannot open CM if SIGNAL_MODEL value was not assigned in ptf.
4 J5 @7 F5 S9 v906153 ALLEGRO_EDITOR SCRIPTS Unable to run allegro script in batch mode on the attached board.
9 K* V7 @; D& X2 @906182 APD EXPORT_DATA Modify Board Level Component Output format
3 _' B; r" T9 _" Y3 Y$ i+ r. y# S906200 ALLEGRO_EDITOR DFA Enh- DFA drc invoked in Batch mode returns false constraint value in Show Element
& ~: n9 T1 q( ~$ |906517 PSPICE PROBE PSpice new cursor window shows incorrect result.
# R" b& Y5 ?- S7 J- S& M1 r% v906627 ADW COMPONENT_BROWSE ppt options are not read if ucb is launched from FM. works fine if launched from dehdl.
( c; k! |1 Q9 Z( B. i( x `! |906647 SIG_INTEGRITY LIBRARY lib_dist creates a signoise.log in current directory (with backup files like ,1 ,2 etc.) on each run
5 p* O2 [& z6 h. j, s% `906673 F2B PACKAGERXL Ignore the signal model validity check during packaging2 H0 Z: Z$ T, |7 M
906688 ADW LRM A copy of source design gets created in worklib of target design after 'Import Design'
: {: X4 z9 E* h$ s3 {906750 ALLEGRO_EDITOR PARTITION Importing design partition removes the testpoint reference designation
, N7 E) U. c. n( B) M1 @906874 PSPICE NETLISTER Error less than 2 connections for unconnected hierarchical pin+ G3 w7 ?+ _; S1 V0 r" i8 C% l: E- D
907095 F2B OTHER Part Manager does not show Error as Undefined when directive ptf_mismatch_exclude_inj_prop is used; R) [: N1 f! d a4 F6 @! v
907424 ALLEGRO_EDITOR GRAPHICS Allegro add option for pre 16.5 shape display
[( ]. f" s" ^, e1 h; F4 a# s. K907490 CAPTURE NETLIST_LAYOUT 16.5 Layout netlist is not correct. It differs form 16.3 layout netlist.
3 h6 @6 G" \ `1 o' X907884 SIP_LAYOUT MANUFACTURING Need to add an "NC" pin text option for "Manufacturing Documentation Display Pin Text"
; m1 @( n/ M( d8 ^$ J! N; U907885 SIG_INTEGRITY OTHER Matchgroup targets lost when importing netlist to Allegro layout in HF31
- ?1 |/ C' x$ m0 M0 j4 W" T1 f907929 CAPTURE TCL_SAMPLE TCL command to delete a property from parts in a library is not working correctly! s7 @( K. f+ G1 {$ S. |! f
907933 SIG_INTEGRITY OTHER Single line impedence not working in OrCad PCB Professional. P3 Z; _& P! ^$ \2 Y @+ T
907963 CONCEPT_HDL CORE Design uprev issue when moving from 16.2 to 16.5
5 Q( Q5 Y8 H* ~" |. E908000 SIG_INTEGRITY OTHER Inconsistence z-axis delay reported on Tpoint when define at via location.3 _# x; m/ w# G7 x6 S7 U5 |% a3 ]
908057 CONCEPT_HDL CORE DE HDL crash with the cut and paste of a signal name
7 |5 w3 B* e( } o3 Z; d908060 CONCEPT_HDL CORE CTRL+LMB Option not working correctly in 16.3
1 p# h0 u4 E3 j* L; g1 w908210 CAPTURE CONNECTIVITY Connection is being lost while dragging a component
0 R0 F# O, j7 p908241 CAPTURE DRC DRC error column is blank in DRC markers window in 16.5. m/ N7 k8 c6 w0 T \
908339 RF_PCB BE_IFF_IMPORT mechanical holes VIAFC are not at the right place" v: }1 ^+ ?* N. k0 C, i
908534 SIP_LAYOUT SYMB_EDIT_APPMOD issues with symbol editor and copying pin arrays
4 l" E6 j2 G+ i. B% O908535 F2B DESIGNVARI When I try to view my variant file the variant editor crashes2 p# I/ s4 {5 n. i% {
908595 APD 3D_VIEWER Cadence Design 3D viewer" screen pops up and is all black because the colors have all converted to b# u! s6 W( F/ o2 H/ q" t+ E+ `
908849 CAPTURE ANNOTATE Getting crash while annotating the attached design" z Y) P1 k. ~# C' a
908874 CONCEPT_HDL CORE Part Manager - No Part Found error when using CCR# 775788 feature% P" g% H# J% \4 t+ O1 l" m: q- @1 V: G
909077 CONCEPT_HDL CORE After packaging pin numbers remains invisible even when $PN. m7 ~& U, C9 y' B: O
909104 ALLEGRO_EDITOR SYMBOL Warning message needs to be modified. It does not save the symbol and also not tell the actual problem.# w* m+ z- H2 ~
909417 ALLEGRO_EDITOR REPORTS "report -v upc" returns 'Segmentation fault' on Linux1 |4 W" e; e G$ n$ P1 u6 c' i
909635 SIP_LAYOUT DIE_STACK_EDITOR Add Interposer crashes in SiP Layout8 l) m# V0 z# i# O
909749 ALLEGRO_EDITOR MANUFACT Allegro Crash during dimensioning8 R7 S& t8 K. [% x1 [; _: |
909760 SIP_LAYOUT MANUFACTURING Create bond finger solder mask doesn't follow the mask opening as defined in the padstack
4 `0 ]" p# k" n, V8 |909861 F2B PACKAGERXL NetAssembler broken within the latest 16.30.0310 q: F" T, U/ C5 z
910006 CONCEPT_HDL INFRA Motorola design fails to uprev from 16.3 to 16.5, xcon file is getting corrupted.
9 `3 `6 V' A8 @, d2 r- m910141 CAPTURE NETGROUPS Modify NetGroup definition does not update Offpage Connector
) m* b! r" h. L$ [$ G p% q910340 ADW LRM Import design in schematic, only 1 page import, the entire block is getting imported.# B4 F0 ]+ Y& w' g( ?) K' g: k9 t
910678 SIG_INTEGRITY OTHER The Analyze> Model Assignment> Auto setup is not creating/assigning models to discrete components in 16.5
' n* ~& E- `- V910713 F2B DESIGNVARI Variant Editor crashes when you click web link under Physical Part Filter window.
: Z- W( Y( T! S910936 F2B PACKAGERXL ConceptHDL subdesign net name is inconsistent. ~! ]$ [# N; B! [7 B# W
911530 ALLEGRO_EDITOR SYMBOL Package Symbol Wizard does not create symbol with the name given
* j$ S8 ?/ K6 P4 `911631 CONCEPT_HDL CORE DEHDL crashes when opening a design" v9 |0 r; Q/ m/ P% ]
912001 ALLEGRO_EDITOR OTHER option_licenses entries are made in allegro.ini even when not set as default& }4 u8 T& e4 q' c; I0 [- ~( X, j2 e+ b
912459 F2B BOM BOMHDL crashes before getting to a menu2 A' A' T+ D3 L! }
913359 APD MANUFACTURING Package Report shows incorrect data: n5 [3 y8 v" o0 R& A" w
( o' j/ i# q, ]+ n+ F9 d( L2 W* I5 xDATE: 06-24-2011 HOTFIX VERSION: 001% _9 W7 B( e( j
===================================================================================================================================
" V$ o5 T4 A0 y+ i, G4 W2 WCCRID PRODUCT PRODUCTLEVEL2 TITLE
4 P, _. i6 Y' U3 K===================================================================================================================================
+ B9 a+ m1 D5 X7 E3 x. ]293005 ALLEGRO_EDITOR DATABASE Allegro crash when attempting to move mech. symbol
% J9 B- r% E7 ?6 Q298289 CIS EXPLORER CIS querry gives wrong results
! ` b( w- C! G" X% [" G% z366939 ALLEGRO_EDITOR OTHER Cannot attach refdes on silk subclass with add text# C4 w' l; h4 K
432200 ALLEGRO_EDITOR MANUFACT Fillets with an arc are required for Flexi designs
0 P+ e5 @ K3 f$ c443447 APD SHAPE Shapes not following the acute angle trim control setting.0 O$ G5 `3 j y3 s$ G' ~+ O
473308 PSPICE AA_SENS Passing variables to lower level blocks using subparam; x* D( d9 |# r6 b2 `
517556 PSPICE AA_SENS Advanced Analysis does not support variables being passed down the hierarchy l8 F5 U$ f$ {
548143 ALLEGRO_EDITOR SHAPE Dynamic shpe on Etch TOP will not void properly.
9 M* h' L8 U H* _) u2 L& O606959 ADW COMPONENT_BROWSE Key properties with blank values are not getting read in shooping cart* Y# T" J* `# ]6 G
616466 ALLEGRO_EDITOR SHAPE Solid shapes are not getting filled
$ w" x+ C b1 Z$ A9 k; K$ a0 W641358 SIP_LAYOUT DIE_STACK_EDITOR Request for Via and Multi Layer Pin support for DIE stack Area (blue region)
6 j- P3 M4 r* F, V8 D m* f644122 SIP_LAYOUT OTHER SiP Layout - xsection - ERROR Adjacent conductive layers are not allowed, but these are diestack layers not conductor% z4 V- i6 c3 `# T
645816 ALLEGRO_EDITOR SHAPE Slide a cline all removes gnd shapes on board
: m- K0 d( d+ @6 `% m4 s725355 ALLEGRO_EDITOR SHAPE User can not voided Logo correctly.+ ^2 Y' s7 _! I* I9 k* z7 S$ i: m
763569 CONCEPT_HDL CORE Display status of Hide/Show unconnected pins icon in DE HDL UI/ V1 \8 c1 G0 a2 ~% o# V' o. M, v
770021 CAPTURE BACKANNOTATE Changing pin group property after pin swap resets pin numbers
# E' O5 p* F- z0 d# A; A H792126 CAPTURE PROPERTY_EDITOR Attempt to change display for occ prop resets
+ A2 ^( L8 [' t3 q1 }799014 CONCEPT_HDL CONSTRAINT_MGR concept2cm errors not shown in export physical after hier_write+ r1 c( G& v& N) n5 e% G
803147 CIS LINK_DATABASE_PA Link DB part should not change RefDes of multi package part
$ _9 d1 V5 h4 M" c- o804240 PSPICE DEHDL Problem in simulation result for a multi-section split part.
! \+ x* D9 f+ @4 h809118 CAPTURE NETLISTS ENH to compare two schematic Capture designs
# [: w4 b u& w+ U p8 b f4 |816568 ALLEGRO_EDITOR SHAPE shape disappears when update to smooth.. State no etch
9 y$ {" f# ]5 ~830053 CAPTURE STABILITY DXF export fails if schematic folder name as /
1 d0 K' t) V, Q: i3 O2 ?832108 ALLEGRO_EDITOR SHAPE Shape void incorrectly.
" T3 n ~; W& V" F! I9 Q# v833542 CONCEPT_HDL CORE PDF publisher font is NOT WYSIWIG with respect to what seen in DE HDL2 A" _2 x p2 I- a5 U* p% T. o
835777 CIS DERIVE_NEW_DB_PA For XLS, donot display table as worksheetName$worksheetName to avoid 8012 error
! u+ R8 ]5 I& c# o5 m( E" b# n0 Y837640 CIS GEN_BOM date format of CIS BOM has broken macros of 16.2 in 16.3 version
0 p3 ]" i( f1 ~$ R) A3 f; S6 C844074 APD SPECCTRA_IF Export Router fails with memory errors.
! x2 ?1 b* s7 l1 X1 H% @5 c, q1 g851595 CONCEPT_HDL CORE Pin numbers overlap on the pin and increase in size
3 s8 z# M: i; X852832 CAPTURE BACKANNOTATE Why is Capture crashing with Mentor back annotation?- Q' \5 \1 A3 ?
855015 ALLEGRO_EDITOR OTHER The rats are NOT connecting to the ends of the clines like they should be.
( a0 ^( C5 N1 v) T# u9 N0 w( C859883 CAPTURE NETLISTS ENH to compare two schematic Capture designs3 |: \: {0 j$ b( ?
866009 SIG_INTEGRITY OTHER Net with Pull-up/down should not be used for Diff-pair.: Q3 k' q9 H" j
866830 SCM REPORTS Multiple lines added as separator between title block and report header instead of single line' M/ k+ J0 Y& M8 w4 E$ { B6 o
866833 SCM REPORTS Extra indentation is left in the left side of the report when the Line Numbers are set to OFF. @$ O O% \1 ~! C6 A1 P# W6 R
868618 SCM IMPORTS Block re-import does not update the docsch and sch view
* J- s4 D* M0 Z/ f J+ v3 f873402 SIP_LAYOUT LOGIC pin swap for co-design die in SiP% Z5 m: N( Y3 d* R: `
874010 SIG_INTEGRITY OTHER PCB SI crashes when the Xnet is extracted with VARIANT_TO_IGNORE property., Z/ u" N Y1 Y. V: q
874400 ALLEGRO_EDITOR INTERACTIV Flip mode issue with move command- R. I- G6 c5 B2 y
874966 ALLEGRO_EDITOR INTERFACES Placed mechanical component do not get Ref Des or part number in IDF file
& ^4 ?. f6 U! w7 \ f1 n/ V8 o875709 ALLEGRO_EDITOR REPORTS Film area report generated incorrect data at l1! l- b7 `' S" F* Q) p7 u/ {
876275 CONCEPT_HDL CONSTRAINT_MGR Constraint Manager not retaining target net9 P4 p3 p: H7 Q1 g- f
879361 SCM UI SCM crashes when opening project J' A3 F2 v1 `) q3 `4 s
879496 CONCEPT_HDL OTHER Customer wants to have the tabulation� key as separator in HDL BOM.! d2 Y8 U% N$ ?7 t0 {( s
879514 PSPICE AA_MC Monte Carlo to handle equation as comp VALUE.
) X& V8 [. }" {# H+ D4 Z0 t881845 ALLEGRO_EDITOR SHAPE Delete island deletes complete shape! f( l R/ V: O V- Y8 }: d
882413 PDN_ANALYSIS PCB_PI PDN Analysis should support routed power nets0 A$ }/ c" |5 W; h# M7 `
882427 PDN_ANALYSIS PCB_PI PDN Analysis target impedance should have a variable multiplier4 a6 z5 E h9 w4 u7 S' w" Q6 W- B
882567 SIG_INTEGRITY OTHER PCB SI crash if boolean type prop was specified to VARIANT env.' X0 e2 o( v |) w1 D5 L1 g
882644 ALLEGRO_EDITOR PLACEMENT PCB Place Replicate Function automatically match Enhancement
6 g& s x3 C1 n: c( Y( V9 Z+ m4 b& w883164 ALLEGRO_EDITOR INTERACTIV Vias marked fanout moves away from position when moving component
0 R) |; [" J. M8 x& y9 s0 C! d883224 SIG_INTEGRITY SIMULATION crash while reflection simulation from Constraint Manager. U1 _1 o* O% J0 e% O9 V
883760 PCB_LIBRARIAN METADATA Incorrectly formatted revision.dat file in the metadata folder. {! A' T/ L: I+ z* G
885391 SIG_INTEGRITY SIMULATION RLGC data sampling algorithm and w-element interpolation.
- m. f5 ]' M0 f! M3 q8 Y; n3 A885849 ALLEGRO_EDITOR MANUFACT Silkscreen Audit cannot find Solder mask for the text string
, p% ^; ~4 e' n$ U885996 SIG_INTEGRITY OTHER The effect of sn_maxwidthlimit user preference is not seen in cross section impedance calculations
- y6 r( F |) x1 B& s886090 ALLEGRO_EDITOR INTERACTIV Add Arc w/Radius does not snap to grid. w" y% y7 B! j2 D8 n+ {. V
887180 CAPTURE SCHEMATIC_EDITOR Signals Navigation window doesnt get updated for Buses0 V% j; M4 V& ~
887442 APD SHAPE Copper pour of Dynamic shapes on Top layer which contains many existing signal traces fails.
5 d5 {5 x& Z3 ^, W6 h887578 SCM AUTO_UI Component Replace pops-up the DSPANE-204 Message" Q: Q/ ^9 j/ v, ^
887926 SIG_INTEGRITY GEOMETRY_EXTRACT Field solution failed if diff trace on bottom doesn't have reference plane.
m! r' p5 i) M& t0 x# G9 g+ r8 l888414 SIG_EXPLORER OTHER View Trace Parameter display the thickness of dielectric incorrectly.8 f6 ~2 y E8 `8 @4 [3 H
888600 CONCEPT_HDL CREFER Cross References not added to Schegen schematic" K5 J) b7 X8 s. w8 V1 s
888679 SIP_LAYOUT SHAPE Can't create the Dynamic shape on layer M1_sig without unwanted horizontal openings appearing.
! V" R* l. c: q; ~, V888804 ALLEGRO_EDITOR OTHER Fillet will become static shape after import from partition board.3 s4 z2 j( W6 h- O/ k/ {/ D
888945 CONCEPT_HDL OTHER unplaced component after placing module' i: E; v; A$ }3 b
889222 ALLEGRO_EDITOR SHAPE Allegro freezes/hangs when adding shape as Polygon with OpenGL ON.8 k4 q' `7 P* r' A8 a
889365 SIG_INTEGRITY GEOMETRY_EXTRACT top/bottom trace impedances extracted to sigxp are wrong in 16.3; A- {: j. \5 D0 ?' `6 o
889404 ALLEGRO_EDITOR OTHER Incorrect pad size for Top conductor padstack written to column 59-62. T/ B2 S+ M# t1 G+ k8 i
889426 CONCEPT_HDL CHECKPLUS CheckPlus does not find single node net$ b! U: [4 W* ]! O# u# N
889636 ALLEGRO_EDITOR MANUFACT Incorrect spelling of "Visibility" in "Film Control" tab in the Artwork Control Form. c* l% S+ _. q. m' b7 i
891235 F2B PACKAGERXL Packager crashes without creating a pxl.log file
/ @* w1 V. S+ B0 |891292 ALLEGRO_EDITOR SHAPE arc routing causes weird undesireable shape fill performance# J. R: a' z2 p
891856 ALLEGRO_EDITOR EDIT_ETCH crash when sliding diff pairs
" {; V I- f. j4 z/ u892375 ALLEGRO_EDITOR PLACEMENT Place Replicate Update disband other groups, irrespective Fixed property added or not.5 x6 k5 T% b' k5 H2 W/ I, g
892455 ALLEGRO_EDITOR SYMBOL Why the overlapping pins are not reported with DRC?
5 Q3 K: d1 H' l3 y892541 SIG_EXPLORER OTHER Export/Import layerstack through the technology file is changing the layer thickness! f! o; [2 c' L' ]2 K: d+ t1 V
892766 APD WIREBOND Excuting Finger moving cannot push aside finger to move with together by shove all mode. X4 V9 h, C, k1 {7 g/ I
892907 ALLEGRO_EDITOR DRC_CONSTR DRC not reported for etch_turn_under_pin violations
9 C! b4 v& K4 N& f9 E6 }892963 ALLEGRO_EDITOR SKILL Bad shape boundary created after axlPolyOperation 'OR# a* J6 ^) j$ M5 I) T7 Y0 [6 _
892964 SIP_LAYOUT LOGIC Request that Edit Parts List use Dashes "-".
$ @. ?' H! c) x% q893295 APD WIREBOND Why move wirebond command does not shove wirebonds? This result in drcs.
) K# a3 `4 o" e6 y4 H1 i893706 CONSTRAINT_MGR OTHER On line DRC hangs on partitioned board
+ Y2 Y9 T. E. w6 Q2 I; X0 ~& c893743 APD EDIT_ETCH Route behavior when spanning pads not as expected.
) l# s. d. ]: B' ?$ t893783 SIP_LAYOUT OTHER Padstack Design Editing update File menu with a Update to Design and Close instead of 2 operation/ e/ u' B. N, k6 o" o; [5 w% o
894456 ALLEGRO_EDITOR REPORTS Request Net names be added to Propagation delay lines of the DRC report.
2 W/ ?# N' I' y8 o: _. o$ t: T894499 SIG_INTEGRITY LIBRARY Tool crashes when moving a cline or selecting the Info icon with OpenGL on.
' u+ O* D8 W+ H A/ C4 ?894582 APD SHAPE When making a dynamic xhatch Via shapes surrounding are abnormal.; T( n( s% y5 A- C
895542 SIP_LAYOUT WIREBOND SIP design crashing when moving bond finger using blur mode BLUR_BONDFINGER_PRESRV_CON6 ? S' }3 R, d% Y: m
895591 ALLEGRO_EDITOR PCAD_IN Importing PCAD file fails to get to the point where we can map layers
0 Y- g+ v- `, [7 `* e: }9 n895757 APD ARTWORK Import Gerber command could not be imported Gerber data
; o; R7 |6 K6 k895964 CONCEPT_HDL CHECKPLUS The CheckPlus command getFileSubstrings is not working correctly' R) x* A x. O* { ~
896428 SCM UI Changed Ref Des value not maintained in DEHDL block when part is replaced
, w% }$ t; H. @8 I* @: O% n896655 CAPTURE EDIF Import/Export Design of Hierarcy design with OrCAD Capture1 F6 i5 I" |3 ?. S4 }
896846 CAPTURE IMPORT/EXPORT Import edif2cap and capture is crashing( U! l& b. V. I+ K
897155 ALLEGRO_EDITOR REPORTS Copper coverage in L2 and L7 looks like the same but film area report had large gap.! t3 |1 i5 f! Q$ P
897654 CAPTURE EE_INTERSHEET_RE Capture crashes on adding intersheet refernces in abbreviated format on attached design.
, m. ?4 P$ Z8 A$ E1 l& a899344 RF_PCB BE_IFF_EXPORT dlibx2iff does not provide the component boundary drawing; I1 e+ ~7 w3 ]+ P
899629 CONSTRAINT_MGR OTHER ECset for Total Etch Lenght is not present in OrCAD Prof
}, L7 g }" v% T! O900175 CONCEPT_HDL CONSTRAINT_MGR Few Xnets are lost from Match Group after packaging and importing the netlist to board file. S o4 R- X5 }
900481 CONCEPT_HDL CORE Genview creates a larger symbol without taking the no. of pin in consideration
% F& l5 o. z8 s3 z8 ^! @% B900813 ALLEGRO_EDITOR DRC_CONSTR With rotated pads, pad (pin - via) soldermask spacing DRC is unreasonable.3 N6 z& j, G$ j6 t' W" ]
900905 PSPICE STABILITY Simsrvr crash and RPC Server unavailable error while running simulation.* G0 g3 C8 {0 \/ J
901783 CONCEPT_HDL CORE CDS_PART_NAME is annotated on the schematic canvas after running back annotation in 16.5
' ` u$ ~! b) ^; q0 M& e9 h901909 APD EXPORT_DATA The "package_pin_delay_length.rpt" with Z-axis delay turned on seems wrong. E. }9 k! }1 W1 v- S3 F6 a9 J3 p
901987 CONCEPT_HDL OTHER SPB16.5 zoom fit does not center the page while ploting the schematic page7 p1 \: I% s9 w# [5 b
902133 CIS OTHER The visible part property value are being shown very distant from part graphics on schematic
3 R$ E2 v* f( r; m902166 SPECCTRA ROUTE Specctra crashes when reading in "bestsave.w" file# Y3 x' f3 k; G" ?2 a
902170 ALLEGRO_EDITOR DATABASE Diffpair Issues with OrCad PCB Designer Professional; W. V: m+ k ]4 k6 Y }/ P# y
902177 CONSTRAINT_MGR CONCEPT_HDL Option to view the layer thickness in CM worksheet through worksheet customization
7 X0 `5 d$ ^% ]5 ]+ |4 X% I902463 ALLEGRO_EDITOR INTERACTIV APD crashes when we click ( show element ) on certain components
+ O) r, l: ?6 p' j* O902621 CONCEPT_HDL OTHER Design Differences (vdd) Crashes
+ J9 z* ]; V' D2 X O& m$ `902909 APD WIREBOND die to die wirebond crash
/ r. |+ E1 E) p- ?; J; e902933 ALLEGRO_EDITOR PADS_IN Pads_in fails while reading PADS ASCII file body! y; x. ]* h9 d4 z- b4 U ]/ H
903284 PDN_ANALYSIS PCB_STATICIRDROP IRDrop voltage gradients are plotted outside of the PCB outline! I. a# L7 b& ~# c1 j
903680 CONSTRAINT_MGR ECS_APPLY Constraint Manager not passing all hiearchical member objects to a custom measurement.5 ^0 ]6 g* @9 ]' j
904403 ALLEGRO_EDITOR DATABASE Allegro crashes when refreshing module |
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发表于 2012-2-21 14:58
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发表于 2012-3-8 15:09
