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DATE: 02-17-2012 HOTFIX VERSION: 016
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
: f& @2 R4 @% Q* t===================================================================================================================================
5 u+ O/ W2 F# i, u3 F840105 PCB_LIBRARIAN USABILITY PTF subtype is getting changed when Save As option is used in PDV6 e6 ?) N& t1 v1 K9 x$ Y
873075 PSPICE PROBE Decibel of FFT results are incorrect.
" r4 [8 l; N6 f) P- j* }+ k% B938744 ADW COMPONENT_BROWSE Need ability to customize shopping cart columns to include any Part property& M2 n+ e2 }# }# y4 \" E
943003 SCM REPORTS The dsreportgen command fails with network located project( G: a0 R! N6 Q+ b* y! p
961530 ALLEGRO_EDITOR INTERACTIV The problem of Display measure command3 ]+ g$ w( e; R/ [9 I& I! p
962157 CONCEPT_HDL CORE Where is the setting for enabling the Enable PSpice Simulator menu?/ o1 s& l! m3 `. U. @0 g
962206 CONSTRAINT_MGR CONCEPT_HDL Import physical not passing all constraints from the board to frontend
5 w0 a- n C" o0 s' c968205 PSPICE DEHDL_NETLISTER Change SPLIT_INST property to PSICE_SPLIT_INST for Quad Switch type of design.
) j% w' n( L: k5 ]" M& e968509 PCB_LIBRARIAN METADATA Incorrect pinlist.txt was generated if DIFF_PAIR_PINS_POS/NEG was set.
" p% Y! h. Y. y% J2 s- P969450 LAYOUT TRANSLATORS OrCAD Layout to Allegro Translator crashes
$ \; p+ z9 x$ r. F969997 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance pro~
+ p) F* v5 ]5 }971193 CONSTRAINT_MGR UI_FORMS Copy and pasting a formula causes the application to crash on windows.0 I! N! L* b; q
971601 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053) and WARNING(SPCODD-66) because of directory structure% n; P! v! T! C9 }
973398 CONCEPT_HDL OTHER It should be not packaged with error while working the packaging process if the design has a ERROR$ z5 }- m, c3 B; |* K0 p
973859 PSPICE ENCRYPTION Pspice crashes with encrypted model+ y" e/ X) P- X: C! N5 i' G
973938 PCB_LIBRARIAN VERIFICATION pc.db is missing
" E6 e8 g$ r6 t974540 CONCEPT_HDL CORE Graphics updates are real slow; k$ a T3 k/ n: l, s2 [0 p. E+ M
974791 F2B DESIGNVARI Variants are not back-annotating to schematic and turning to ?
: }8 h* `5 | E @% x" W4 s5 ^974818 ALLEGRO_EDITOR NC Backdrilling produces 0 plunges yet no errors reported., w" M9 Q4 D# }: p* P
974945 ALLEGRO_EDITOR SKILL Why is axlPolyOperation is giving different result and not working( J3 }; G5 `' ^8 a% r1 B2 M0 p
974946 MODEL_INTEGRIT TRANSLATION ibis2signoise returns the error - Delay measurement fixture must contain V for ECL technology+ S" {' H+ ~( c& ~6 A# `" x. r
975396 CONCEPT_HDL CONSTRAINT_MGR Constraints are dropped after migrating from 16.3 to 16.5
1 E; E$ {/ p0 t975633 ALLEGRO_EDITOR GRAPHICS 'dynamic_layer_visibility' option in 3D Viewer when checked or unchecked should not change (until next change)
# W/ ]$ J5 z3 u! M* q2 Q2 q' V975720 ALLEGRO_EDITOR DRAFTING Datum dimension lines not adjusting to text move
5 m/ I5 u8 B# ^. L( M975745 ALLEGRO_EDITOR SKILL cdsServIpc different 16.2 vs 16.5 when Allegro exits
1 I+ j( t: y/ X6 b# c976013 CONCEPT_HDL INFRA Power pin connection of FPGA symbol is missing in netlist.
6 c& j3 C' t H9 ?$ }976058 CONCEPT_HDL COPY_PROJECT SCM Copy project does not create the con and dcf files in tbl_1 views6 l2 o4 }7 `( k
976073 CONCEPT_HDL COPY_PROJECT All the constraint data is lost in the SCM copied design
# b8 Q+ ^ H& y Z0 y976160 CONCEPT_HDL CREFER Cref fails due to some Caeviews error in the design4 X7 c. L* ~* O
976204 ALLEGRO_EDITOR DRC_CONSTR Application falsely reporting Mechanical Pin Antipad to Shape Spacing DRC
6 y6 e+ t7 [3 s7 x+ |, i976448 F2B PACKAGERXL ERROR(SPCOPK-1069): Invalid POWER_GROUP property value0 m$ S9 L! K) }
976521 ALLEGRO_EDITOR DRC_CONSTR multi-thread update DRC causes the application to crash
/ g' @( m5 i- a* I5 ~5 s976838 SIG_INTEGRITY OTHER Unable to create XNET for highlighted nets on attached database even after assigning proper Signal Models.3 s* l- X- K4 h
977517 F2B PACKAGERXL Export physical fails after update to 16.5 from 16.3" m$ [% x6 \; m
977902 ALLEGRO_EDITOR DATABASE generate module is crashing allegro
8 U3 t2 n: ]7 _4 U2 F3 B978652 ALLEGRO_EDITOR PADS_IN PADS_IN fails with ERROR: Finished with errors.2 l6 X# b- `" E2 _- S1 F/ [
978744 APD DEGASSING Some shapes will not DeGas on this design0 p% y3 P1 H6 R$ M; t: Q) F0 `
979940 SIP_LAYOUT OTHER SiP Layout Leadframe autobonding with profile selection
' }4 z, L8 K3 G4 Z" n1 i981699 CAPTURE HELP Start Page still shows Hotfix 14 after installing Hotfix 156 H3 ~+ b$ a5 d. i* T, d
- d4 l' _/ E- M8 l. i0 }8 K' R; p! RDATE: 02-03-2012 HOTFIX VERSION: 015& j, }- r" Z9 x% [
===================================================================================================================================
2 e# P0 \$ c3 w! U0 OCCRID PRODUCT PRODUCTLEVEL2 TITLE
! b- P4 F7 m8 Y9 Y$ F===================================================================================================================================8 H+ _& W7 k% E6 W2 D
871567 CONSTRAINT_MGR SCHEM_FTB Ability to filter out Single Node Nets from Constraint Manager/ P1 ^3 r. e% B+ l
921436 ALLEGRO_EDITOR MANUFACT Change in 'decimal place' for new dimension changes the already placed dimension: @) X1 e8 [$ }' ~1 v: @) L
941433 CONCEPT_HDL COPY_PROJECT 16.5 Copy Project should warn if trying to copy a 16.3 design2 D0 m1 q: S; U$ m3 P- b! i% Z
954375 ALLEGRO_EDITOR MANUFACT Change dimension accuracy for few instaces of associative dimensioning! M* \! d3 x7 s# \9 d4 O
961646 PDN_ANALYSIS EMVIEWER EMViewer Help > About shows wrong version& W7 P+ `; I2 f$ `
964912 CONCEPT_HDL COPY_PROJECT ASA project crash after using copy project8 \( K& F5 X1 `/ N) T: \
967223 ALLEGRO_EDITOR MANUFACT Bug:Oval slots orientation in one direction only
- F8 n& o% K2 y: g& w9 C968865 SIP_LAYOUT DIE_ABSTRACT_IF load of die abstract fails due to differences between component and symbol
3 M; ]' ]) f8 I6 w% J969485 ALLEGRO_EDITOR SHAPE Shape does not update correctly in 16.58 Y/ c3 u0 j0 v) L1 s- G
970331 CONSTRAINT_MGR ANALYSIS Impedance worksheet shows a zero value for impedance
3 w5 }/ d9 E; I% a970600 SIP_LAYOUT SYMB_EDIT_APPMOD Option in Die Editor to be able to "physically swap" pins
7 o3 d& o a( ^+ N3 Q6 d970910 F2B PACKAGERXL Our customer has problem with pin color after pxl 16.5.3 W/ u! O2 a& X2 M# T
970970 SPECCTRA FANOUT Fanout Vias is placed far away from decaps and does not change the Fanout length even when max_length is reduced." D, I6 x. W s* G; f- r
970985 SIP_LAYOUT OTHER Importing a .spd2 database file using NA2 will cause the APD/SiP tool crash: n$ B4 q* ] J6 E& S
971757 CONCEPT_HDL INFRA Crash while Saving/Packaging the Design
3 g2 o4 ?. d: W971923 ALLEGRO_EDITOR MANUFACT Allow to change decimal accuracy for dimension instances, |7 t7 s p1 h* E
972568 CONSTRAINT_MGR UI_FORMS Tools >Excel missing from CM
! s6 }5 Y! Q6 h. C7 }6 s h8 {# l972821 CONSTRAINT_MGR CONCEPT_HDL connectivity server warning: Unable to add property WEIGHT
3 ?. F9 ?$ I/ i9 |! x9 r973185 SCM CONSTRAINT_MGR ASA2 block not seeing all instances in a package.6 F! L! Q- N* J% D
973211 ALLEGRO_EDITOR INTERFACES IDX Object Type Change not recognized: D+ f- X* N5 F; N
973214 ALLEGRO_EDITOR INTERFACES IDX import package keepout height value change assigns incorrect value
! F( D& }! X9 u, {+ g4 n: ^973384 CONCEPT_HDL CHECKPLUS The multiple SIG_NAME has to be occurred an ERROR at the SPB16.5.
# X( Z4 q1 u5 U: q. k+ F- r973514 SIG_INTEGRITY OTHER Mapping error when Ecset is updated to constraint manager from extracted net; Z& j# D, \' `6 z u
973950 ALLEGRO_EDITOR SHAPE Update to smooth crashes application
9 P+ j. [: H" }, T974533 SIP_LAYOUT OTHER Crashes in Edit > Die Properties and obviously has a setup problem.
4 A. q3 H5 k5 @( @# a974809 ALLEGRO_EDITOR SKILL argument available for hiding a property with function axlDBCreatePropDictEntry is not working4 C! `- q( w w4 ]( v
976179 INSTALLATION ISR Installation of ISR S014 to 16.5 on windows is breaking the documentation index
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DATE: 01-20-2012 HOTFIX VERSION: 014
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
8 `+ e+ K: g& e" I0 u& |6 p& \===================================================================================================================================
- n/ ~; ~. L2 i, u! y733285 PSPICE SIMULATOR Enhancement:In server-client installation use existing index file from server
1 q+ e( C0 s. ]& d941020 SIP_LAYOUT OTHER Soldermask enhancement! t9 \. y3 B1 B# G# q( E2 k4 @
946407 CONSTRAINT_MGR TDD When is it safe to open a 16.5 design in 16.3?
5 K8 o& C: P( A4 \953067 CONCEPT_HDL OTHER Variant Editor "Error/Warning messages" form is unusable! x- D. [7 R" ]1 l
954818 CONCEPT_HDL COMP_BROWSER Replace button turns to Add in component browser when a component replace is done on the schematic/ d* U% f$ F5 g) \( Y
956450 ALLEGRO_EDITOR DRC_CONSTR Analysis always shows analysis failed in uncoupled length in some diffpairs
- J% ]1 ]+ Q& S6 A/ }958259 F2B DESIGNSYNC ds.exe crashes on a big design when accessing the design from network drive
2 M- S& A/ L( t* e9 T958395 ALLEGRO_EDITOR SHAPE shape voids won't merge
; L0 h7 u" D6 W8 h+ a5 |959212 MODEL_INTEGRIT PARSE Attempting to use "Mark qualified" option on DML File results in dmlcheck and Modelsim wanrings. Y0 F5 p" p F3 M+ f S4 z5 C3 g
959940 APD AUTOVOID Void all command gets result as no voids being generated.
+ B+ C8 T: k6 o9 `! k$ v7 r960252 PCB_LIBRARIAN CORE Splash screen in PDV prevents showing error message) k' X" |# H. N$ Q0 _+ V8 `
961634 PDN_ANALYSIS EMVIEWER Cannot launch PDN EMViewer from withing PCB SI9 L- v$ L# s" U T, R, q
961645 PDN_ANALYSIS EMVIEWER Standalone EMViewer will crash when opening any result file in the form of *.emv file.
" J1 @$ P9 X, f. C7 j( E961700 ALLEGRO_EDITOR SHAPE dbdoctor reports ERROR(SPMHUT-144): Illegal arc specification
9 f+ x5 _) V: i: Q* x961733 ALLEGRO_EDITOR SKILL Allegro crashes. Appears to have a memory leak.$ e1 o" N% n, |% W& _' v* O
961758 ALLEGRO_EDITOR DRC_CONSTR DFA check produces no DRC when the dfa bounds are not a rectangle.
; ?1 c- w3 ]7 c$ w0 S961887 CONCEPT_HDL CONSTRAINT_MGR Match Group created from ECSet cannot be deleted in the same session of CM8 v" U7 r. T" j7 u2 O
962552 APD EDIT_ETCH BUG:APD crashing when we try to slideget information but move works fine0 e/ c- H) T! u3 `9 a) {) Y( v
962869 CAPTURE STABILITY Capture crashes after RMB click on rotated parallel wires5 ^& H# y" A/ p: X* X. f# a
963232 CAPTURE MACRO Macros not being played in Windows7+ x, m9 ?1 w U1 T$ W4 S/ x
963300 ALLEGRO_EDITOR DATABASE Create > Module crashes in 16.5 but not in 16.3
/ r, x: v, p. g8 ~; Y# L963651 CONSTRAINT_MGR CONCEPT_HDL ECsets are renamed after packaging on linux
! w) q+ v' J7 F! B9 }; h, h2 T+ H963663 CONSTRAINT_MGR ANALYSIS Q- Why the customized worsheet for Diff pair Impedance not analysing at all for this SIP design
' ?0 [3 a3 L# G# a! c0 a+ V: N( W963715 SIG_INTEGRITY OTHER Application only adds the bottom conductor thickness for the via z-axis length
9 V) X" P5 m1 A) J! L: @" u8 g& W964068 ALLEGRO_EDITOR INTERACTIV Allegro crash when using move alt sym mirror alt sym...( \* W: D2 H- f. z7 |0 T& D6 |6 \2 P' h
964267 CIS PART_MANAGER Capture become non-responsive, working on Part Manager and creating CIS BOM, for large designs
! d. |% G8 [) D% n- {964597 ADW LRM Issue of LRM license checkout after renewal license by 16.5 (ADW15.5_S23+SPB16.3)' P8 T- I6 w; X* R h4 m
966148 APD INTERFACES Character Limit for DIE Files (*.die) Import' ]) f. Y- p3 ~: f
966416 F2B PACKAGERXL Cannot package this design/ |: a1 p* F0 m6 x
966421 CONCEPT_HDL CORE DEHDL Crash when applying property on components in duplicated blocks
' d$ H# J7 F q) x6 R) B; L966693 CONCEPT_HDL CORE DEHDL crashes when doing model assignment if CM is open5 P! T/ x* D$ ]2 d) R
966795 ADW ROLLBACK rollback utility does not honor -product option from command line
4 Y1 H; V& S7 q2 m/ l967089 SIG_INTEGRITY OTHER Matchgroups created by ECSet not deleted when ECset is removed from object.4 q2 _+ i3 K4 Y( W
967222 ALLEGRO_EDITOR OTHER PDF export is leaving data off the drawing/ ~& d8 {0 } c r
967240 SIP_LAYOUT WIREBOND Change default bond fingers selected on multi-site leads during "bond to leads" program
* a+ J" l/ F1 K* ~2 n* r1 `967297 ALLEGRO_EDITOR OTHER Dynamic Fillet&Eliminate unused stacked vias cannot be used as the Miniaturization option.
; }/ @# `0 P5 ?( X% n5 C967576 CONCEPT_HDL CREFER Occurrence location property values do not appear in flattened schematic generated by CreferHDL6 B" c/ U8 T& W* D, c
968096 ALLEGRO_EDITOR DRC_CONSTR Mechanical Pin to conductor spacing is not followed.7 b1 n9 t7 \* e. r {) @
968222 SIP_LAYOUT DIE_EDITOR die pin loses IC net for a co-design die with multiple ports within IO-cell& `3 ]& K/ k; l5 K2 D3 m. _4 y/ @% `
968358 CIS PART_MANAGER Capture crash on removing a part from subgroup in part manager t1 I: ?0 |- \" [" S% x0 D) O" [, U
969594 CONCEPT_HDL CORE The dcf file is not updated with schematic changes
8 d" Z2 V) \# b& n8 d( j7 z
7 }+ j W+ l' ?% EDATE: 12-16-2011 HOTFIX VERSION: 013
7 t/ R9 l s" x8 ^$ J U===================================================================================================================================/ q B& \$ i8 v9 t& x
CCRID PRODUCT PRODUCTLEVEL2 TITLE9 u$ W1 c8 u1 S, n
===================================================================================================================================( Z% G" X4 F, f2 C
875695 SIG_EXPLORER INTERACTIV Enforce Causality check box doesn't work.0 \; w# A+ S: B5 J3 [2 ^" J* X) {
927148 CAPTURE PROJECT_MANAGER Capture crashes on creating scehmatic folder with name which already exists in design
, S6 C; x5 x# w M, G+ d0 z5 K938013 CAPTURE NETLIST_OTHER The netlist in RINF Format contained two identical lines for PCB FOOTPRINT6 Q' ?0 r% B% f1 h
941409 PSPICE PROBE BUG : Search accuracy wrong in new cursor window
0 ]5 \& R1 n/ f945242 SIG_INTEGRITY SIMULATION Unable to select "shapes" in find filter for 'show parasitic ' command
8 T( [1 J9 c8 |# K: I. k0 d946293 CONCEPT_HDL ARCHIVER Archiver hangs if there is a whitespace at the end of the path of cref.dat
1 E; g8 l$ h, S! C g# Q946770 CONCEPT_HDL CORE 揤iew Design� function is missing in Windows Mode after reseting the menus.1 @2 K* P" [) N
950994 CAPTURE NETGROUPS Problem in expanding the netgroup in Auto Connect to Bus function
! a! z+ X0 H- U. |+ @! ^953530 SIG_INTEGRITY GEOMETRY_EXTRACT Display Parasitics is displaying wrong results for EMS2D Field Solver compared to topology extraction using Probe.- E- s5 D2 \ T% j
953713 CONCEPT_HDL PAGE_MGMT Random page replacement/duplication in block
0 A5 M. j N9 s- N! x* p953917 CONCEPT_HDL ARCHIVER archcore should handle errors correctly
5 |3 ~; `. f% b- D0 l! \ }* L+ L7 z953971 ALLEGRO_EDITOR MANUFACT NC Drill files not generated correctly when using the option "搒eparate files for plated/nonplatedholes�
. Q" W" g, p# K' s8 Q1 w) j954400 CAPTURE NETGROUPS BUS members of NetGroup are getting converted to Scalars in Export-Import NetGroup.
8 m5 d/ n. ~% p! g954498 SCM B2F SCM crashes when importing physical
. J0 U5 _; @) U, C, C954623 ALLEGRO_EDITOR EDIT_ETCH Unable to complete connection with Add Connect - related to soldermask to cline check?. p- g& j( O2 K0 K# \3 h* |
954894 ALLEGRO_EDITOR MANUFACT Dimensions disappear when opening database in v16.5 from v16.3
|) K7 J( K. q# @9 i! E0 x |0 i5 P955029 CONCEPT_HDL CORE custom text font size not recognized in symbol view% Z# u1 F C/ O8 }7 P9 h( j
955133 SIG_INTEGRITY FIELD_SOLVERS The Field solver creates the differential trace model which is reversed T(D1) and T(D2) of bottom side.
. I4 d0 R9 t3 S5 P) t' i$ f# @. K955290 CAPTURE DRC Description for UPD0014 missing in the Browse DRC markers window+ v4 o0 K- b2 C* s) I7 v
955299 ALLEGRO_EDITOR DRC_CONSTR drc text to smd pin does not work any more on this database in 16.3 S039$ O& n$ s Q9 `
955338 CONCEPT_HDL CHECKPLUS Need to change PART_NAME; @4 e/ q' |/ m0 ` p& R; [
955447 SIG_EXPLORER OTHER Model path set in DE HDL Model Assignment not used by SigXP from CM in DE HDL2 q# x% M/ V7 }! q# f5 |
955740 SIG_INTEGRITY GEOMETRY_EXTRACT Crosstalk with Timing Windows does not work correctly
" E% n Y4 {% s955749 ALLEGRO_EDITOR MANUFACT show element Info shows symbol dimensions on incorrect subclass
/ e7 t5 M7 j4 i+ |' \955912 ALLEGRO_EDITOR OTHER Shapes with voids that are exported to PDF have gray filled area over the void/ L; w" F# C( a$ _9 Z+ s
956129 CONCEPT_HDL INFRA DEHDL uprev hierachical design from 16.2 to 16.5 packaging failure., Z. O; x% ?5 v" F- g
956373 ALLEGRO_EDITOR NC drawing name doesn't display in the log file% M6 U/ m5 Q- |2 e
956393 CAPTURE PROJECT_MANAGER "GENERAL" and "TYPE" tabs are missing from " roperties" dialogue box.& H9 n* W5 B$ `& v. J7 Q# K
956448 PSPICE MODELEDITOR Can not generate a DEHDL symbol from Model Editor, because no Capture license found8 X) I5 w/ l' Q" R2 h+ o
956456 CAPTURE NETLIST_OTHER OrTelesis netlist not transferring user properties defined under combined7 p' D$ }+ \# m1 x2 M7 i1 r
956489 ALLEGRO_EDITOR MANUFACT dimensions lost when symbol with diemnsions attached to symbol origin placed on board4 P+ n* `" Q5 x" |
956603 CONCEPT_HDL OTHER Part Manager "has stopped working" after changing a component# ^2 b" |* N9 K9 f
956751 ALLEGRO_EDITOR ARTWORK Import Gerber command does not work correctly5 u6 W0 b/ o; ?
956847 PCB_LIBRARIAN METADATA PDV - Partdeveloper symbol to function linkage broken/changed in 16.5
4 j$ g5 F4 ?+ O) z956987 CAPTURE OTHER Find from "Search toolbar" doesn't gives complete results
0 D" W+ h8 X- W. I956996 CONCEPT_HDL INFRA Correction to ERROR(SPCODD-7): Following Primitive instance causes CM to empty4 T; L8 i: W/ v, E, e
957009 CAPTURE NETLIST_OTHER Problem getting database property in Mentor PADS PCB netlist
F0 p, N1 {* B; x$ N2 Q. `# F5 |957137 APD DXF_IF DXF out command dose not work correctly.
# G' b2 E% r$ U8 B. N957167 APD GRAPHICS Highlighting for Static shape with display_nohilitefont environment variable.
- ~+ G2 Z- z, x957232 SIG_INTEGRITY OTHER Allegro crash during Model Assignment.
1 u( L8 F) Y! Q: g: G& d7 W# j5 G957267 CONCEPT_HDL INFRA Packager Error after Import Design# h% u8 n: l4 `" L0 Y. L O" `
957866 SIP_LAYOUT DATABASE Cavity outline is not getting deleted from symbol file z B, e! B; x( e# ]9 M0 Q
958010 ALLEGRO_EDITOR REPORTS Wants the ability to extract "Batch" reports from Partition ".dpf" files.. ~( k( U `# Z! D& a- g' @
958252 ALLEGRO_EDITOR TESTPREP Resequence testprep with the option - Delete probes too close crashes the design
& M. B7 _& i$ R8 W# a5 f9 T958253 ALLEGRO_EDITOR REPORTS Shape did not have thermal relief connected to pin but unrouted nets still shows zero.. z a: L" O- y* Y
958433 ALLEGRO_EDITOR DRC_CONSTR False embedded component DRCs
, V$ [3 U; f' O: j6 Q0 F) ^958753 ALLEGRO_EDITOR SHAPE Dynamic shape is getting corrupted in 16.5
. X! F% \% ?( a4 e% F0 I v m959011 ALLEGRO_EDITOR OTHER copy problem of via and cline j% J4 k7 f3 b! }( b1 Q3 E
959101 ALLEGRO_EDITOR EXTRACT Using extracta with excluding Thermal reliefs7 d S6 s7 a, i) b% T# Y+ g' R
959253 CONCEPT_HDL INFRA Design will not open. `' H3 Q& b" [8 @$ n0 ^
959299 APD MODULES Getting ERROR(SPMHDB-279) when trying to update modules placed on the Top side
F* B5 y3 t% w. {# s( l959884 CONCEPT_HDL INFRA Design Uprev/concept2cm crashes with Application Error/Out of Memory Error.
% j# D' `* R# J9 a+ F4 D# ]959909 ALLEGRO_EDITOR SCHEM_FTB Site level propflow.txt file is ignored property is transferred
5 f8 H1 P4 D1 k9 J; A9 |960067 SIP_LAYOUT PLATING_BAR Creation of plating bar removes "NODRC_ETCH_OUTSIDE_KEEPIN" property from the clines.$ C4 X- D0 m9 S7 X: _ a
960126 SIG_EXPLORER EXTRACTTOP Allegro PCB SI license is used automatically at Topology Extraction of Allegro Physical Viewer.
; N0 B: y6 `7 q& h, W960143 SIG_INTEGRITY GEOMETRY_EXTRACT Running simulation in Bus sim happened crash while enable Coulpled Via model to S parameter. m$ J+ \3 x( @2 W+ d: l- a
961349 CONCEPT_HDL HDLDIRECT Motorola designs have broken connectivity compared to 16.3
, M2 @7 b3 x2 h" h961816 ALLEGRO_EDITOR INTERFACES Normal Export > DXF fails and offsets the pins of the BGA symbol
( U3 T/ F# I) N5 I% G& Z962519 SIP_LAYOUT WIREBOND Align option doesn't work for wb_tackpoint fingers
( v* b7 P: C L9 U% H; ?: l) X& d% Z& V) s$ M3 h- H# T
DATE: 11-30-2011 HOTFIX VERSION: 012
+ j6 V: w5 o3 _0 u# v4 q; z/ I# ?& V===================================================================================================================================
" m. y# b: v% | wCCRID PRODUCT PRODUCTLEVEL2 TITLE
7 D1 r0 V/ ?* A! b0 r2 u9 V===================================================================================================================================( K" A/ F7 P! C/ L8 Y
959581 CAPTURE NETLIST_OTHER PCB Footprint is getting replaced by VALUE in OTHER netlist formats7 k2 `- i' ^- L1 D) W
: _/ M: Z. C$ \
DATE: 11-18-2011 HOTFIX VERSION: 011
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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$ w$ U: p0 X/ }9 r1 s735439 PCB_LIBRARIAN CORE PDV Moving line-dot pinshapes by arrow keys breaks the pinshape* h3 Y( i1 j* A7 r: E# G" A
894815 CONCEPT_HDL COMP_BROWSER Why does genlibmetadata command give 'Aborted $PROG' Message?
; h2 Y; `( k$ n1 B0 d( C903073 ADW COMPONENT_BROWSE datasheetl_url directive should support a display string for URL
$ \9 ?3 M5 f7 z. I7 }: _909919 CONCEPT_HDL OTHER Why is the PublishPDF UNIX command line looking for "true" script?
. T0 z9 Y4 a; v, x: D1 g# P6 L911561 CAPTURE CORRUPT_DESIGN Capture crashes on trying to save the design.% u P5 N+ O b1 c
919579 CAPTURE PRINT/PLOT/OUTPU Print mode be selected based on schematic mode! k# W' u- z3 c
921247 CONCEPT_HDL COMP_BROWSER genlibmetadata.bat file does not have err defined& r) B/ z$ g/ k! k7 ~& [
925182 CAPTURE PROJECT_MANAGER ENH: Feature to run update cache on all the parts in design cache at once.0 d R+ f& U9 x H- m
926858 CONCEPT_HDL CORE Usability- Modify Component dialog forces user to do 'Reset Filters' to see other ppt rows6 D/ g8 U8 q5 M5 `% B) a8 L; D" x
927657 CAPTURE NETGROUPS Enhancement: Placement of netgroup definitions under design cache list
; I- V) _+ b8 L934684 ALLEGRO_EDITOR MANUFACT The relation between the linear dimension and the symbol breaks.7 [/ ?( U5 l4 y8 D6 K$ R4 k
935836 SCM SCHGEN ASA crashes when generating Flat Document Schematic2 l+ n$ y I! s1 u
937165 SCM SCHGEN Can't generate Schematic% W3 I- w3 \; H# f
937292 CAPTURE GENERAL Memory usage keeps on growing and finally gets exhausted while search! {8 ~4 T h: b. o% J& Q) I
937322 CONCEPT_HDL CORE Master.tag file alters the sequence of the files and Genview fails6 a# z& |9 o; h5 X2 @
939135 CONCEPT_HDL CORE Unable to uprev a 16.3 Design to 16.5 with DEHDL-L License {5 J; o) b5 d" _4 s8 [& O# I0 u
940373 CAPTURE TCL_INTERFACE Enhancement: TCL command to add nets to Netgroup; b5 v, C H6 b" L- e
940547 TDA CORE ERROR(SPDWSD-69): highspeed cannot be checked in
0 b6 V, ] Q2 Y J% I940607 SIG_EXPLORER OTHER Inconsistancy in License usage for opening sigxp -orcad
. x) x; i' V/ l$ s1 J940790 F2B PACKAGERXL User doesn't want to display pin numbers after Export Physical 16.5.7 s" V( z9 a, \" `. }
940944 SIG_EXPLORER OTHER Inconsistant license usage while opening Orcad PCB SI using allegro -sq -orcad and allegro -sq2 b' s+ p' Y, J
941354 CAPTURE NETGROUPS Enhancement: Option to rename the unnamed NetGroups0 T3 R) U* v; V) A3 [4 |
941455 ALLEGRO_EDITOR MANUFACT The Dimensioned mechanical symbol when placed in the board does not show all the dimensions.9 \) C0 j; m* `/ [; T, q" a0 N
941863 ALLEGRO_EDITOR EDIT_ETCH Different behavior of design in v16_3 & v16_5 when add connect is executed on a segment thru script, R' @+ R+ n: ~# k" E: C
941881 CONCEPT_HDL COMP_BROWSER How can I suppress the dialog from universalbrowser -genlibindex?
' ~! x) W: V7 t/ W5 J" O942474 CAPTURE NETGROUPS NetGroup member type of last added member must be remembered by Capture0 ~$ u @' g! P
942522 CAPTURE GEN_BOM Export in excel check mark doesn't invoked BOM in Excel
; n6 F, w7 V! T* L3 l942557 PCB_LIBRARIAN EXPORT_OTHER PDV Export to Capture crash0 x( \# Q* N1 m! i* M. c [. k
942569 ALLEGRO_EDITOR MANUFACT Dimension move and change text deletes leaderless balloon% D! J+ N2 m- r
942573 ALLEGRO_EDITOR MANUFACT Balloon type parameter has no effect on leaderless balloon.- O+ I, Q5 D i. z9 g# j
942613 CONCEPT_HDL CORE Genview supports only SCHEMATIC/SYMBOL/VERILOG/VHDL views as input type. .xcon not recongnised
/ S7 @0 N& E9 O4 c o943032 SCM OTHER ASA is not passing the correct reuse_module name to Allegro PCB layout.1 W# F. p4 U1 w) H+ d- c
943401 CAPTURE NETGROUPS Alphabetical ordering of NetGroups in Place NetGroup
0 O/ u6 Y" K' D( J5 y: j944006 ALLEGRO_EDITOR EDIT_ETCH Vias added to shapes behave differently6 y) [3 `1 G3 {7 B0 y
944367 CONCEPT_HDL OTHER Too late to do Model Assingment in conceptHDL 16.5
2 c. \4 v4 v$ S5 s/ c944788 ALLEGRO_EDITOR GRAPHICS Oblong Pad shows unexpected lines9 O' j8 S! y( X) w% K9 ?
945221 CONSTRAINT_MGR RETAIN_CNS CM Conflict Resolution fails on more complex designs using ECSets and constraints3 Q( x# a4 E1 o( g
946270 ALLEGRO_EDITOR PLACEMENT The Rotation Type was changed to "Absoute" if the "iangle 90" use at placementedit mode of spb16.55 I9 n# y* `6 N8 Z& B+ F% Q3 o* `
946350 F2B DESIGNVARI Variant Editor rename function removes all components7 }: S! }! z* g% `% t3 e
946380 F2B DESIGNVARI Some VARIANTX properties are hard some soft - why?
# s3 `( a* E6 ~( g1 _946419 SIG_INTEGRITY SIMULATION Cannot select component on BoardModel for controller in bus setup form( a; A( n. E2 ~2 V& b$ `
946458 SCM SCHGEN Schematic generator adding an unnecessary page
9 H, k# _* J# y9 c% ?1 c/ L0 b0 s+ i947667 ALLEGRO_EDITOR PADS_IN Need support for PADS-POWERPCB-V9.3-BASIC9 i# s5 O1 Z+ t `) n# K) I
947789 ALLEGRO_EDITOR MENTOR mbs2brd crashes during translation on the attached design.0 M/ B# i2 |" ], l- ]
948110 CONCEPT_HDL CONSTRAINT_MGR Concept HDL craches when opening SigXP from CM7 z V1 l4 e8 u) |+ K6 f6 e
950970 ALLEGRO_EDITOR MANUFACT Unable to generate artwork, dbdoctor fails to fix errors.
! L4 @0 W: | [' n6 q! G- n3 e951901 ALLEGRO_EDITOR EDIT_ETCH In 16.5 add connect to same net is shoved
' Q+ d& t& B, H9 ]' U951919 ALLEGRO_EDITOR OTHER Exported package symbol soldermask and pastemask padstack locations not the same as original$ a! x6 X/ P# O+ q7 ]6 B
951926 CONSTRAINT_MGR OTHER What is MaestroNotifyNotSetReport.txt file?
$ {3 h, Q$ N6 H) U951939 F2B PACKAGERXL Uprev to 16.5 is changing refdes for some pages! @8 u5 x- `9 `
951983 CONCEPT_HDL INFRA Problems converting an Allegro design from 16.3 to 16.51 p, L( E" }/ o+ r; V- ]
952057 SCM PACKAGER Export Physical does not works correctly from SCM7 E, `+ B1 j+ ^' B8 N
952217 ALLEGRO_EDITOR GRAPHICS crash when opening 3d viewer in PCB Editor7 d8 Q* @) Q I# {1 ]
952634 CONCEPT_HDL CHECKPLUS Checkplus logical rule fails on a design which packages fine in 16.5& J" @/ p9 G; [; S5 k' ]( M6 N
953018 APD REPORTS Shape affects Package Report result.) g8 N' i0 N4 z1 L) h7 i
953337 ALLEGRO_EDITOR OTHER Allow netname and padstack names to be visible for testpoint vias when viewed in Allegro PDF Publisher.
3 C2 \; g" n7 g* q953827 ALLEGRO_EDITOR EDIT_ETCH Snake Breakout function crashed Allegro
7 l4 ?% p: o2 }4 O953918 GRE CORE GRE cannot route second and third row of pad in die symbol.! S+ ~& h) G& u1 I2 W
954055 CONCEPT_HDL CREFER Crefer fails with UNC install path
% E8 l- W7 F* Y! S8 B954920 SIG_INTEGRITY CIRCUIT_BUILDER Each neighbor crosstalk simulation crashes or returns blank report, t& D% I+ j* V
$ W5 B* D" t: h% P9 ?1 |, E3 \
DATE: 11-7-2011 HOTFIX VERSION: 010$ Z u: j8 m) M% y, M
===================================================================================================================================
) `/ ^" L4 \9 T" i1 }- }) v) U1 kCCRID PRODUCT PRODUCTLEVEL2 TITLE
5 O C) s# p, U" t% V X0 o===================================================================================================================================) k" b# ^! U1 e) n
658866 ALLEGRO_EDITOR EDIT_ETCH enhancement option - so that Sliding a via inside a pad does not create a cline0 Y/ P& n' L K$ E0 ^2 m5 |2 `( m
928624 ALLEGRO_EDITOR GRAPHICS Layer visibility control for 3D Viewer
, Q/ Q$ w0 p& m) ]934991 SPECCTRA LICENSING Specctra_adv option is not working correctly for PA3100 plus PS3500 license in v16.5 tiering profile7 Z' X0 Y; k; u$ R
938073 ALLEGRO_EDITOR PLOTTING Plot Page size A0 and A1 with problem
4 e; p! k& v. S3 c0 g* x938128 ALLEGRO_EDITOR DRC_CONSTR DRC changes when do update DRC.( {# J+ s6 B1 w$ }( y
938648 ALLEGRO_EDITOR GRAPHICS Enh - Requesting a way such that Package keepout appears transparent in 3D Viewer- [9 \9 f2 @$ n6 E( f. K, e
940518 SIP_LAYOUT SYMB_EDIT_APPMOD Swap pins command doesn't complete# p1 w# I9 Y3 y4 Z3 }
941426 CONCEPT_HDL COPY_PROJECT Copy Project fails - Updating opf view This can't happen!
. {; ?6 r ~3 {4 x( D941499 ALLEGRO_EDITOR DRAFTING BUG imit Tolerance isnot working for Dimensioning
$ l" i3 K G2 ]) H# E2 Y0 k941814 CONCEPT_HDL CREFER CreferHDL crashes during ScheGen
8 m9 p' @0 V, o6 F- c942914 SIG_INTEGRITY OTHER ZAxis delay calculation
, U" ~0 v3 W; I& S6 R! H943053 ALLEGRO_EDITOR SHAPE Modifying the Board Outline shape will cause the tool to crash; s1 g3 H( Z% I* j( G" o
945321 SIP_LAYOUT EXPORT_DATA generation of a xml file from cdnsip for shrunken die
- p* x+ W w b6 z945350 ALLEGRO_EDITOR SHAPE iPick does not work on shape boundary edit., s3 Y/ n" x/ g
945449 APD SKILL When they create a new menu entry with skill APD crashes with next menu selection.! k; K3 q# m. m9 D4 l% y/ y6 M/ a! J
946390 ALLEGRO_EDITOR DRAFTING refresh_symbol crash when trying to refresh mech sym that has dimensions: N# t" c* t0 Q
946401 APD EXPORT_DATA stream out gdsII results in shorting of PWR/GND nets due to elongated etch' h: [& C& L4 a
946819 SIP_LAYOUT DEGASSING Shape degass command, ?' ]& {( l9 j
946869 ALLEGRO_EDITOR OTHER Allegro PDF arc representation needs cleaned up
& ~8 h, q: R* U( F* d4 b, I7 _947230 ALLEGRO_EDITOR SKILL Skill execution crash Allegro 16.5 but work correctly with Allegro 16.3( I6 ^0 l+ {8 E' I: }
947603 ALLEGRO_EDITOR OTHER Component Properties (Default or User Defined) not transferred to PDF file* B0 H. X2 V- ?) ?, Y+ r. H$ W
950995 SIG_INTEGRITY OTHER Netrev fatal error when importing logic
1 Y3 T/ T$ j: r! g; w951123 ALLEGRO_EDITOR INTERFACES IPC fails to output drill hole info in columns 33-37
- g, j7 V6 p$ }9 h- Q2 E; M951557 CONCEPT_HDL CORE Cannot create the entity folder for old plumbing symbol% u/ ^% g& g+ r
5 L! e+ L' X6 b" z8 l/ m5 k
DATE: 10-26-2011 HOTFIX VERSION: 009! a# S: j; q3 N
===================================================================================================================================
; \7 [6 T* |; H5 I; n, ?CCRID PRODUCT PRODUCTLEVEL2 TITLE. d9 Q1 q% s& H/ E; p
===================================================================================================================================0 u% u: B6 g4 w3 F
945788 CONCEPT_HDL CORE Some component properties on the parts are incorrectly changed after Import Sheet/ n$ ~$ O5 f8 R
945789 ADW LRM Some component instances are not updated by LRM even though cache ptf is updated from reference6 c' T8 V, o! h# `& [
6 C6 V. w$ h* j7 k0 tDATE: 10-21-2011 HOTFIX VERSION: 008
6 J* _$ ^6 N8 \: J===================================================================================================================================/ ?9 ~/ G% X, i5 ^& R# t
CCRID PRODUCT PRODUCTLEVEL2 TITLE
1 d9 g0 F* q0 J* ~( [8 o( |===================================================================================================================================+ I4 W! L6 g/ z4 h; Z
906827 ALLEGRO_EDITOR DATABASE Logic > Parts logic does not work correctly.
* V# R5 X1 [$ f; j# ^3 c923346 CONCEPT_HDL CORE Not able to move the reference designators inside hierarchal blocks after uprev to 16.5
8 \2 l. H8 q5 ?3 U& i926347 ADW COMPONENT_BROWSE Usability- Libflow Part check in comment should end up in Comments attribute for UCB/Designer to see it
, Q) i- A( w/ ?929348 F2B BOM Warning 007: Invalid output file path name8 Z- ?9 y, u! I7 i$ A
929777 CONCEPT_HDL OTHER Component Revision Manager gives internal error
- c" F; ]6 v" m$ O, f930783 CONCEPT_HDL CORE Painting with groups with default colors9 a7 y8 m3 n. B s
936748 ALLEGRO_EDITOR INTERACTIV "Unplace Component" menu inconsistent between General Edit and Placement Edit Mode.
; z, R+ i4 e3 Q3 a1 x3 Q938143 ALLEGRO_EDITOR CREATE_SYM Why is this Extra Property 'ECSET_MAPPING_ERROR
4 R( U+ Q5 s# Y/ T938281 SIP_RF OTHER export_chips creating bad data when symbol is split and contains V- V+ pins
; I& B. g w# a. z5 n- v6 |+ ?938812 ALLEGRO_EDITOR SYMBOL Cannot create a BSM with this DRA, errors out but does not state a reason.% Y/ R+ z& }9 P: R7 n
939075 CAPTURE TCL_INTERFACE Texts are getting garbled in command window
% `, ^. j, J* c, k0 p# I939193 F2B PACKAGERXL ERROR(SPCODD-439): Connectivity server is unable to load the design.% Z, m; }: F$ L3 Q/ O A2 ~
939199 CONCEPT_HDL DOC "Retain electrical constraint on net" mismatch between schematic (YES) and design (NO)
8 B, Q, w+ L% l+ E* Z6 q; h939346 ALLEGRO_EDITOR SHAPE Shape disappears when updating with variable shape_rki_autoclip set.5 n8 m2 C! J& }- B3 M/ T2 A" A% t+ i
939901 CONCEPT_HDL INFRA NET_SPACING_TYPE shows �?� on lower hierarchy level nets after Upreving to 16.5 version.3 c5 \! g$ x+ \& y' W5 B
939918 PSPICE PROBE Print > Preview for output file causes Pspice crash.
+ {' g+ B( P$ A1 v/ Y1 b6 E940217 CONCEPT_HDL COMP_BROWSER UCB reports 'No Symbol found for the part'
% [; h/ q* M1 s9 ^940835 CONCEPT_HDL INFRA Desing package different after uprev to 16.5 where comp instance propeties are lost lost; {' b) W2 A0 K& B$ G- R
941125 ALLEGRO_EDITOR DATABASE Performance advisor doesn't skip non plated slot padstacks
3 u0 r) E; k- ]- p$ {941876 SIG_INTEGRITY OTHER Illegal model name cause pxl fail in 16.3
( N0 J) q9 }0 D1 x; X4 |& B942210 SCM OTHER Is the Project File argument is being correctly passed? J! q, r" X. c- W
942274 CAPTURE PROJECT_MANAGER Crash on renaming a Design Cache part in Project Manage after doing replace cache
7 S) h. U( }9 j8 h' e g$ r942839 ALLEGRO_EDITOR GRAPHICS Graphics Issue- Pads are not visible
, [5 \. a. J+ g, G/ d' ?943055 ALLEGRO_EDITOR SKILL axlDBCreatePropDictEntry causes application to crash- C& M" a1 \$ K) G
" P z7 I) ~! ^( z$ B4 t' LDATE: 10-21-2011 HOTFIX VERSION: 0073 P/ j$ v! o: a' Z) m6 P! n
===================================================================================================================================% v' x" N9 w- Z% C: e$ p5 r/ T5 I
CCRID PRODUCT PRODUCTLEVEL2 TITLE& w0 A q. D% |* S, \
===================================================================================================================================
# S, y; P5 J6 ^: D841096 APD WIREBOND Function required which to check wire not in die pad center.
3 y8 ]+ F* i2 W. e! Q* M+ b S903263 CAPTURE SCHEMATIC_EDITOR ENH: Selecting parent netgroup must select the underlying netgroup bits.
. g: y/ a6 o# h8 g, j2 u% ?1 p# k9 Y906692 ADW LRM LRM window is always in front when opening a project; _" O5 O$ S) C: j
912942 APD WIREBOND constraint driven wire bonding7 f. g( d# U% K1 C2 i+ \6 g0 ?
912951 CONCEPT_HDL CONSTRAINT_MGR Need to manage temporary files on Linux systems
1 w- K( o/ y3 Y4 W2 q915178 SIP_LAYOUT DIE_STACK_EDITOR Die Pad names changing when updating Die in a design, Y( Y) s7 K' s B. f' w
917887 PCB_LIBRARIAN VERIFICATION Part should not be released if the alt_symbols has errors
0 g. W9 J7 u6 V" T% Q; t* b923315 SIG_INTEGRITY GEOMETRY_EXTRACT crosstalk simulation fails with TMP popup failure0 w2 b3 }) h/ S. a
927382 CONCEPT_HDL CHECKPLUS 'Verify Symbol' forces the use of 'Concept_HDL_Studio' license
8 R! ~0 |! ^. N8 u: f927664 CONCEPT_HDL CONSTRAINT_MGR Internal Error disposeipsp
+ H( K, w# }5 Y* e. I" P930152 CAPTURE NETGROUPS Scalar net names when being connected to net group overlap when connections are made one by one1 {$ I! {2 R! {0 S9 q
930180 CIS LINK_DATABASE_PA Visible property position on schematic get reset on "link database part" operation
# Y; b7 o5 R; [- K/ |930188 CAPTURE DATABASE Capture 16.5 crashes in being re-invoked.
0 D% k/ E8 I) ?! ~930541 CAPTURE NETGROUPS NETGROUP element renaming doesn' renames the associated net ?
/ i" m+ v- |1 g1 Z2 n- x930866 PDN_ANALYSIS SETUP OrCAD PCB SI Session crashes when we open PDN Analysis with "OrCAD PCB SI" license.# y6 c6 F# m& B4 Y
930926 ALLEGRO_EDITOR GRAPHICS Via and Holes not visible eventhough set to Visible in Color form
: `+ U5 r) H8 s3 _$ N+ r9 S7 `931274 ALLEGRO_EDITOR DRC_CONSTR Negative Plane Islands waived DRCs reappear after performing update DRC.4 _. m2 D0 c7 h) v& `- g" K
932091 CONCEPT_HDL CORE Prop attached to SIG_NAME property
9 }+ T5 s6 e5 u! c932255 ALLEGRO_EDITOR GRAPHICS Change in Zoom level makes arc segment to disappear! l2 K/ {# J, B2 I
932292 ADW LRM LRM crashes during Update operation on a customer design$ o0 P. ]/ C" B0 `
932639 SIG_INTEGRITY OTHER Add Connect command hangs for about 14 seconds and then returns.. V3 c I$ ]* U0 k) X
932704 APD DEGASSING Shape > Degass never finishes on large GND plane
) J1 o0 t, v( Z8 h932871 APD GRAPHICS could not see cursor as infinite5 Q+ P# g) d/ ~% C' X- c1 Z( |
932882 CAPTURE SCHEMATIC_EDITOR Capture crash with FIND command - ISR05
; h0 Q7 {, Z1 R: j9 r k9 j932969 CONCEPT_HDL CORE ConceptHDL crashes when you save the design in 165 > hotfix #05/ Q Z) Q; F# o- J9 `8 _
933024 CAPTURE NETGROUPS Naming restrictions for NetGroup members% r2 V% ?9 d1 W8 N( T
933145 F2B PACKAGERXL Add Subdesign list is truncated in Force SubDesign Design Name pulldown
' @6 L' H+ }1 d$ O }0 J; L5 ]" c+ \933214 APD ARTWORK Film area report is larger when fillets are removed
' o5 O, U: o# I8 z' {933356 CONCEPT_HDL CORE Net prop display size become 0 if it was attached to SIG_NAME prop.
5 a* e' F8 l6 R3 e- g933532 ALLEGRO_EDITOR COLOR Bad color assign and initialisation during creation of new subclass
& `0 V5 k" U, P& H1 i9 I9 z933549 ALLEGRO_EDITOR OTHER Chart text missing in export PDF file.
* X! K+ A, h! V- O$ M/ W934008 ALLEGRO_EDITOR REFRESH refresh symbol updates symbol text to some unexpected values
& c* O; W% e: M: J934031 ALLEGRO_EDITOR DRC_CONSTR Bug : Update DRC removes Waived status for some DRCs7 O, v5 D+ V% O- w `* E
934087 CONCEPT_HDL CORE Opening DEHDL and Model Assignment before design loads causes crash
; l+ H& a9 }# ]- ?" |: _934396 CAPTURE SCHEMATIC_EDITOR Find operation is not searching power symbols with + or - signs.
Z( {+ T- Z- ?/ z4 g934533 F2B DESIGNVARI The Variant Editor errors are not written to the variants.lst file
6 u; y% S+ f1 \/ J- K( n934811 SIP_LAYOUT UI_FORMS CDNSIP should not hang if contraction value in z-copy command is out-of-bound
% \- V {& ?7 p9 H8 t0 W934909 SCM UI Require support for running script on loading a design in SCM
7 \0 W4 X& R% | Y R935632 CAPTURE SCHEMATIC_EDITOR SHIFT+Mouse wheel scroll(horizontal) of page is not working in Auto Wire Mode.
5 J W/ ~+ }5 ?1 J+ E8 x935794 ALLEGRO_EDITOR SHAPE BUG:Shape not filled in 16.5 but it does in 16.35 j! h& Q& m" {( c0 G
935988 ALLEGRO_EDITOR INTERFACES When attempting to downrev this 16.5 design to 16.3 the tool will crash
, t M( {" v7 o% I* b& x936056 ALLEGRO_EDITOR DRC_CONSTR place_manual crash while moving mirrrored symbol8 T* I$ H* I) L& H7 `$ Z) m
936098 ALLEGRO_EDITOR SKILL axlDBCreateCloseShape does not work correctly.- L. n) n! e8 M: v
936212 ALLEGRO_EDITOR INTERFACES DXF not created if Blocks created for Symbol and padstack2 \) R) u" e& N+ d" B: Z1 { z6 U
936797 CONCEPT_HDL COPY_PROJECT Copy Project crash
# }+ G2 o+ Q/ |2 \7 `1 c9 N! @$ c936808 ALLEGRO_EDITOR DATABASE Allegro crash replace mechanical symbol
$ T' I6 _; p# M& L' j936853 CONCEPT_HDL CONSTRAINT_MGR DEHDL crashes when trying to extract net from CM
0 {1 |" t6 g3 v" J* H' z Q2 A) A937087 CIS DESIGN_VARIANT Upreved design becomes very slow in Variant view mode. DELEET THE DESIGN AFTER RESOLVING THE ISSUE: n. s2 h3 H! z( w1 m
937173 CAPTURE OTHER Wrong license information "UNLICENSED" in Capture >> Help >> About
% m$ ^+ a& E5 _ |5 Y1 X937290 APD PLATING_BAR Plating Bar checks does not recognize connection made through etchback through shape.
+ [) J. L' V1 c( a9 a937411 ALLEGRO_EDITOR DATABASE downrev_library reading from one directory and writing to another hangs the command.0 D* ]2 `% @) o7 _
938235 SIP_LAYOUT STREAM_IF Die Orientation is not correct after importing a stream file.: A. _% N. e2 d2 o2 w8 ]" ^ ?! M
938273 ALLEGRO_EDITOR OTHER PDF export is is not opening viewer with ads_sdlog variable set
[0 o. M$ b2 u+ z5 |' J9 Z
! U6 k7 o' _ {/ k" `DATE: 09-16-2011 HOTFIX VERSION: 006! e$ _ r. b y' m' [0 h' ~$ E) o: S
===================================================================================================================================
8 ]+ \* y+ i$ e7 M. a7 mCCRID PRODUCT PRODUCTLEVEL2 TITLE
' W* x/ B1 K! H: j) F& ?===================================================================================================================================
$ V% }' \& p9 E- p( j820131 CONCEPT_HDL OTHER Moving symbols to other page will make Allegro components unplaced because logical_path changed.% c( ^$ P5 K' J+ w$ e( ^
863860 CONSTRAINT_MGR SCHEM_FTB CM should display or Local Interface and Global nets to help defining low level constraints& G6 j; k8 y! k. ~+ b. e
919822 TDA CORE Cannot configure LDAP to only list the login name
- r) O& k! W8 |! z0 C6 h922907 ADW TDA 搇ast_callout_file� directive in the BOM section is empty causes tda for show Access Denied error, s+ j/ w6 H& u
924322 ADW COMPONENT_BROWSE Random - No instance properties are added on Add To Design (RMB or double click) from Search Results; s. @# l+ |& S" V5 }2 ~
924448 F2B DESIGNVARI Design does not complete variant annotation" Z& z* M3 P+ t: B/ }' ^
925584 CONSTRAINT_MGR SCHEM_FTB 16.3 upreved Design passes the SLOT/Function Properties to PCB
: ?4 }( M; [" b1 |. g+ x927102 ALLEGRO_EDITOR OTHER Question of Conductor Detailed Length Report8 I9 J0 u6 Z% ^6 j; H! n* |% t7 T5 q
927104 F2B DESIGNVARI Tools > Annotate variants crashes when there are ASCII characters in the property values
! t# H* B. d! k8 u' ^927142 F2B DESIGNVARI Incorrect pop up asking while executing variant editor from the command line: _ ?3 U, h& M2 m" G7 Q. q0 H
927166 CAPTURE NETLIST_ALLEGRO ENH: Feature like NET_SHORT in Capture Allegro flow which allows user to short 2 or more power nets
9 ~; `; A$ {% S- W$ h$ g2 p* [927410 ALLEGRO_EDITOR DATABASE ERROR(SPMHUT-144): Illegal arc specification error when Run DBDoctor5 ? S* \$ C* F
927475 CONCEPT_HDL CORE About forcereset command of nconcepthdl
$ Q, P3 i9 b! G. ?3 H% u/ c3 v" _$ u9 y927498 CONCEPT_HDL CORE Pin_Name starting with minus causes incorrect behavior for $PN display8 w9 J- K' e) d$ l+ B' z8 ~$ d3 M: m. o
927608 ALLEGRO_EDITOR PADS_IN Import PADs fails with error message: Failed to close the Allegro database
* R- g# H: @5 Y3 h7 T927637 SCM CONSTRAINT_MGR ASA crashes on change root and also performance is too slow.1 C! v( \ f* D% l; |+ f
928429 SIG_INTEGRITY OTHER Request - Package Wizard to work in PCB SI.
( N5 Z: x3 N4 m5 g; m! h928483 ALLEGRO_EDITOR DRC_CONSTR Running Update DRC removes Via List DRC Error when via is actually not in the list
, V, Y: ?, T I1 B928738 PSPICE PROBE Y-axis grid settings for multiple plots
6 v; A; N8 J" X6 m' I' m) z928748 PSPICE PROBE Cursor width settings not saved1 c5 \8 ?1 q1 s+ ~# Y4 e
928779 CONCEPT_HDL CORE Error (1053) occurs on a copied part in SPB165 release$ l" q" p3 I j9 {! T" {
928838 CONCEPT_HDL CONSTRAINT_MGR ECSets not migrated in 16.51 v0 s% K7 _; z% v3 n2 N+ }
928885 SIG_EXPLORER EXTRACTTOP PCB SI crashes when extracting a net from Probe2 y5 Y& q s" c6 ]
929284 CONCEPT_HDL ARCHIVER archive does not create a zip file
1 S" m8 c* o3 _# s$ v) v929542 SIP_LAYOUT DIE_ABSTRACT_IF net issue of multiple ports of co-design die in SiP
0 `0 G X4 w& A0 Y$ A. Q) M0 z# ^7 X( [929656 ALLEGRO_EDITOR PADS_IN PADS translation fails with Microsoft Visual C++ Runtime Library error. Y9 A" M2 U: T4 ?! e! o) q' y
930063 ALLEGRO_EDITOR TESTPREP Test prep crash Allego when it can not create pin escape* ^0 p9 Z# R3 z; W) Q
930217 CAPTURE NETGROUPS Net aliases doen't gets assigend to bus bits if bus name is checked in NETGROUP.
' @9 D4 ]+ s; Z e1 d930355 SIP_LAYOUT WIREBOND about "wirebond add nonstandard" command
; [& z* q& c/ Y* G! ?2 C3 E m930607 APD OTHER Layer mapping information is reomved from Layer conversion file upon exporting DXF from board file.$ _3 I$ o* \5 S
930646 ALLEGRO_EDITOR DRAFTING Bug - Adding Linear Dimenstion for ISO standard add the Angle information as well5 j% e$ v2 R& }4 ^: Y9 B
930894 CAPTURE TCL_INTERFACE PDF export doesn't creates property file if some symbols are used in page name/folder name+ H# ^) U* j( I3 A r
930944 ALLEGRO_EDITOR OTHER Setting variable 'appmode' equal to 'none' is not changing the Application Mode when reinvoked
}0 M% ~* e; T1 @: w1 V v2 n9 m2 D930978 ALLEGRO_EDITOR SCHEM_FTB 3rd party netin error - Pin is connected to net <netname> not reconnected no longer happens
9 f' }" Z1 |5 z# x- l3 U931248 ALLEGRO_EDITOR DRC_CONSTR Match Group was removed if member nets became xnets.4 ~" D' U- e- c0 o; e% e2 ~' R$ w
931278 CONCEPT_HDL INFRA $PN gets copied when upreving design from 16.2 to 16.5 version" O' T* Q4 a) u: ^2 L ~; K) e
931349 CONCEPT_HDL COMP_BROWSER DEHDL craches and corrupts connectivity file when using Modify command extensivly.$ A; O+ r* s8 i' Y5 b
- `. z# ]/ |: u$ u
DATE: 08-31-2011 HOTFIX VERSION: 005
' q( O- S" H2 O$ H* u* Z===================================================================================================================================
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8 a: V% T8 j6 E) D x' t( G825848 ALLEGRO_EDITOR SHAPE Shape not filled when edges from 2 RKO shapes touch around mouting hole8 |2 Y6 O: }" b
837723 CAPTURE PROPERTY_EDITOR Occurrences of external design not related to current root should not show
5 t l/ v" Q! X) h891079 CONCEPT_HDL CORE DEHDL crashes with large number of commands in Winodws mode: Q |6 i9 y5 n' J7 ]( Z. U
910908 SIG_EXPLORER OTHER Cannot open top if Tx AMI dll name contain more than 2 dot.
X Z9 j2 N, @# {! F5 _2 W4 }914036 CAPTURE LIBRARY ENH: Option to delete a corrupted part from a library and leaving other parts intact in the library.5 t& E! w) Y1 N( [5 R) s
914679 ALLEGRO_EDITOR INTERACTIV Custom toolbars are not retained when switching between brd to dra and back to brd file using the File > Recent Designs7 L) R2 }2 M; y( |
914870 MODEL_INTEGRIT OTHER mergedml fails to merger 2 DML files from the model integrity
7 n$ P$ N* v! D7 H0 h. \ J7 n915645 ALLEGRO_EDITOR MANUFACT Allow the user to place the cross-section chart at a desired location2 t2 t% ?2 \# E0 N& x
915653 ALLEGRO_EDITOR INTERACTIV unable to delete non-etch shape# B& M8 V3 N, ?( F5 w
915711 ALLEGRO_EDITOR MANUFACT dimensioning tolerancing by limit not working) A- E Z4 ]% H- b
916321 CAPTURE GEN_BOM letter limitation in include file8 `9 T. ^1 d4 v. D0 t# Y9 Z4 z
916907 CAPTURE SCHEMATICS 揂uto Connect to Bus� should place the wire through non-connectivity objects
7 H+ E& }! v# p+ b6 _9 x; Y& b. ^920327 CONSTRAINT_MGR ANALYSIS The TotalEtchLength predicate in Constraint Manager does not work for a netclass with a bus.
" Q6 W0 a4 |+ G9 x. f0 b3 x+ H" t3 _: C920753 ALLEGRO_EDITOR GRAPHICS If I confirm to padshape with zoom-in after install the s002 It was changed to wrong shape." L/ }% `$ t2 V- l% i/ F) b
921097 ALLEGRO_EDITOR GRAPHICS Padstack seen partail filled when Zoomed in even "static_shapes_fill_solid" is set
4 l" M+ p$ r9 V r921226 ALLEGRO_EDITOR DRAFTING Unable to select Package Geometry class when dimensioning in the symbol editor.
% e$ n" H0 z, g+ N" c+ X921623 ALLEGRO_EDITOR GRAPHICS Bug : Symbol not visible when zoomed in 16.5 S002/ P7 l; g0 ~) x6 r' G
921891 ALLEGRO_EDITOR DRAFTING dimensions are lost after downrev(ing) a SPB 16.5 design with associative dimensions9 ~" O1 @3 A& z9 G2 k
921937 ALLEGRO_EDITOR COLOR Padstacks with shape symbol are not showing correctly
" F9 |6 _; e: |9 K. ^) z$ p! g922066 CONSTRAINT_MGR ANALYSIS Custom measurement Actual not being cleared when layout changes.
0 o7 L# n4 [* c% o922117 PSPICE PROBE Label colors are not correct in Probe
( q8 V, w/ A: ]% s922519 ALLEGRO_EDITOR SKILL add_bviaarray command fails for some clines but not all( E& E7 U% h4 t( S
923224 ALLEGRO_EDITOR GRAPHICS Thermal flash Display problem in Allegro v16.5 Hotfix S002- L9 }6 x7 v+ w; V+ G$ S# x% t' A
923286 CAPTURE DRC DRC markers not reported for undefined RefDes
# @5 c. m: `, I2 j923362 ALLEGRO_EDITOR PLOTTING Print to Postscript file not correct in 16.59 k+ p# X& j F, |9 g5 g& D
923416 ALLEGRO_EDITOR PAD_EDITOR Pad Designer crash on clicking on the Arrow before Soldermask_top
' [, M9 ^& e. k0 \- ~923507 CONCEPT_HDL CONCEPT-PCBDW The function of Import Design in the SPB16.5 Design Entry HDL (for data of ADW15.5_S23 + SPB16.3)
; U. \( `0 D0 _ K5 s923910 CIS PART_MANAGER Copy & Paste operation from Part Manager copies properties only to first section of the part.
( g0 _0 O2 T0 p( l( ^- ?923913 CAPTURE PROJECT_MANAGER Capture runs slow on attached design
2 C0 r: |! Z" ?) S923937 CONCEPT_HDL CORE Back annotation time significantly increased with the metadata generation on
+ W% `9 s& g* V1 Z/ H3 h923949 ALLEGRO_EDITOR INTERFACES Incremental DXF_IN gives 'Invalid subclass' error# K5 a- `4 R+ }5 ^5 F) G& w3 q$ \
924458 SCM OTHER Project > Export > Schematics crashes
8 [4 V+ l: d `; _# f924621 ALLEGRO_EDITOR SHAPE Dynamic shapes are disappearing upon updating them to smooth.* V' K: e, W( C: j
925193 SIG_INTEGRITY FIELD_SOLVERS Diffential Impedance (DiffZ0) values computed in the layer stack-up is incorrect3 c& ]( d, e* J- b0 a6 e: {
925195 ALLEGRO_EDITOR DRC_CONSTR Incorrect pin to shape DRC error) X+ W/ Z8 [" {' M. k* {4 W$ x9 u
925338 CONCEPT_HDL CORE This application has requested the Runtime to terminate it in an unusual way
$ e4 {+ F$ ^; }- Q; M3 m925435 CAPTURE TCL_INTERFACE Capture crashes if 揝ave design as UPPERCASE� option is disabled., ~2 f- [4 X6 C& I T: A
925530 SIG_INTEGRITY OTHER Why the single line impedance value for Top and Bottom layers are different for this design?
- F2 Y; B' n* a3 A+ u1 @6 c8 h925864 ALLEGRO_EDITOR DRAFTING Ability to add dimensioning to different CLASS/SUBCLASS1 f, e, r% c7 U& O! w
925976 ALLEGRO_EDITOR MENTOR mbs2brd fails to import data
( `4 ?- Z D; u4 J" t" z7 p$ o' I; G926409 SIP_LAYOUT DRAFTING Exporting a 16.5 design to 16.3 will cause the leader/dimesion lines to be removed.& \. o1 k8 A! a. g
926443 CONCEPT_HDL CONSTRAINT_MGR In new 16.3 "035" ISR Concept2cm will crash with error.; {$ R; z6 K$ j% m) q
926503 CAPTURE GENERAL Memory leak Capture/Pspice
0 I2 r. L" M o7 k4 ~8 z926553 CONCEPT_HDL CONSTRAINT_MGR CMGR ERROR There is no net in the Cset that has pins matching those in net 1 in the Xnet
4 v" B" U$ Y1 U6 p: c5 C926691 ALLEGRO_EDITOR OTHER Crash while Importing Technology File in CM, with Overwrite Constraints.
" h8 g7 G. I* h6 j1 |7 ]926887 CONSTRAINT_MGR CONCEPT_HDL Pin pairs lost after Export Physical
' a! i% W& ^+ |. C; M927159 CONCEPT_HDL CONSTRAINT_MGR Export Physical fails due to errors in ConCM.log when SIGNAL_MODEL injected property is ''
3 w. u7 y E# w$ y
3 A) K; W6 \( B5 }0 YDATE: 08-19-2011 HOTFIX VERSION: 0043 P1 X1 F& Z- w5 J$ [
===================================================================================================================================
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===================================================================================================================================
% ]/ [" E7 o6 u785417 CONCEPT_HDL COPY_PROJECT copyprojectui crashes with a Windows runtime error
3 N; \1 q7 |6 k) e5 C3 _851044 CAPTURE GEN_BOM "Export BOM report to Excel" does not appear in the Standard Bill of Material Window.
8 y6 h: \$ H$ v/ y# U868216 PSPICE MODELEDITOR Encryption of subckt names, internal nodes, comments7 Q, N7 B4 K* L1 z/ I
870247 PSPICE SIMULATOR Encrypt a model and simulate it, info about inside nodes being dumped in the probe file
0 l, P; s# Q' a7 _) z877091 CAPTURE SCHEMATICS Save JPEG, GIF, PNG and other image formats in the database in its compressed form) t4 D4 E8 _9 K: P0 f% c
894059 CAPTURE OTHER Enhancement: Adding column in edit>browse>parts window' ?3 X0 N' g& _" U9 t
895902 RF_PCB OTHER Alphanumerical allegro pin numbers are unusable in ADS 2009 Update 1
# s7 Y7 S0 x2 R; p3 i; o895919 RF_PCB OTHER Round trip Allegro to ADS to Allegro requirement
; O) b3 R4 j% I* h+ f8 L903102 ALLEGRO_EDITOR OTHER Zcopy shape command for cline seems not to work correctly.
) P0 W2 W0 C; [' Z; t5 d905562 SIG_INTEGRITY SIGWAVE Noise margin seems not to be measured correctly with Eye Measure function.
. s: V. C G/ i909469 SCM TABLE ASA crashes when opening project2 P* G. M J+ W; ~. Z
909595 APD LOGIC Inconsistency between export die text out and show element after pin swap
w) d5 [3 x5 n4 U7 Q9 S! a911123 CONCEPT_HDL CORE 16.2 Design uprev to 16.5 fails with ERROR SPCOCD-152
+ b7 [/ h2 X- H3 l, n. D; ]3 R) t911569 CAPTURE EE_INTERSHEET_RE Q: Why is capture assigning incorrect Irefs in attacehd design ?6 x! B# _2 f$ o3 T
915657 ALLEGRO_EDITOR OTHER Allegro PDF Publisher Mirror capability- l, l" v% T) x" o- u3 z9 Y1 N
915755 CONCEPT_HDL CONSTRAINT_MGR Cannot view net in SigXP( o1 A8 M) ?' w: O5 x9 y
916062 CAPTURE GENERAL Auto Wire Crashes Capture
8 \1 k0 K* p+ B8 c916820 F2B OTHER RF create netlist with problem5 u3 p2 @4 [$ A4 O- @
917967 ALLEGRO_EDITOR REFRESH Update symbol resets refdes location for bottom side components only.
' W- d \- R% K0 Z919343 ALLEGRO_EDITOR PLACEMENT Place Manual is crashing the board file8 T, k2 Z9 k2 b# W2 t
919481 CONCEPT_HDL CHECKPLUS CheckPlus isGlobal function is not working x* g( u7 v$ T6 I/ }- I
919510 CONCEPT_HDL PAGE_MGMT takes 10 min to insert page in DE HDL
. {1 r. X" t0 k919976 APD DATABASE Update Padstack to design crashed APD.
# A! }( W$ W4 S! \ f1 Z; Z; F920418 SIP_LAYOUT OTHER SiP enhancement to Auto Assign Pin Use to add ability to change the pin use definition
! T- w% c x# {920420 SIP_LAYOUT LOGIC SiP enhancement to Logic Auto Assign Net to display a dialouge Auto Pin Use assignment should be run
2 N& z$ [9 e! E7 Q* Q920712 ALLEGRO_EDITOR ARTWORK Program has encountered a problem ... error when creating artwork
; c( ?: S8 L2 R& W m4 u% t920763 ALLEGRO_EDITOR ARTWORK Soldermask gerber missing thru-hole pins
+ ]2 v) t1 n0 ^920976 ALLEGRO_EDITOR GRAPHICS Question regarding the difference in the behavior of 3D Viewer w.r.t. height_min2 i( i8 d" i& m1 f$ A; \( ?5 K
920993 ALLEGRO_EDITOR DRC_CONSTR Minimum Metal Spacing Error is detected on Same Net
2 d* M) m( k# f, Q& ^2 D921727 ALLEGRO_EDITOR DRC_CONSTR Pad Boundary causing P/P drc to adjacent symbol.& F y. J! T, p! w! r; s
922579 CONCEPT_HDL CORE Xcon file gets corrupted upon Save of Hierarchical design with Global nets tied to interface nets
9 b* |$ d2 w1 a7 _+ |+ j& e8 n: u S922592 CONCEPT_HDL CORE DE-HDL does not report illegal connection when Global Net tied to interface net using an Port symbol and named
( i$ x; z# v' i# l( ^922758 ALLEGRO_EDITOR DATABASE Allegro crashes while placing second mechanical symbol with route keepin+ l+ U+ N3 P3 ^0 X2 v5 C& ]+ ?+ t5 k
922839 ALLEGRO_EDITOR DFA The DFA drc display is unstable.
* A6 Q, B. s9 q r923293 ALLEGRO_EDITOR INTERFACES File> Export> IDX is failing for this design while creating an empty error log.4 m2 E; ]. K; z8 q. `3 ]
924772 ADW PCBCACHE Import Sheet is not bringing in Parts used in the source pages into target cache ptf
( }6 _( Q8 _( w% n+ e$ \
' K# }. l2 A6 r! ?4 c i0 kDATE: 08-4-2011 HOTFIX VERSION: 0034 Z0 { ~% S) d( }
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===================================================================================================================================
9 _. V# T1 x( H& }787414 CAPTURE PROPERTY_EDITOR Part value can抰 be moved on schematic if a part has been copied to a new design and not saved yet.
/ s" n% c9 A: y$ j2 a- Q+ W903898 PCB_LIBRARIAN GRAPHICAL_EDITOR PDV move symbol graphics and Undo causes corruption in graphics
2 O. p& }3 n6 h0 L" F4 Y904287 ALLEGRO_EDITOR ARTWORK some cline with arc is missed, when creating artwork.
+ S# i$ q1 q; ~4 N, A904418 CHANNEL_ANALYS SIMULATION channel analysis sim does not give valid result
5 t9 U/ A% W i( j905777 SIG_INTEGRITY SIMULATION User gets popup message that halts an analysis until it is acknowledged
2 ^( m4 I: L, l; r1 ?906139 SIG_INTEGRITY OTHER Bus sim result were cleared at the next run even if no preference changed.# [: L3 c: G4 N$ O5 l% Y! k1 k; C
908680 SIG_INTEGRITY OTHER Extra prop delay due to resistance
) u7 i# \! }2 z( \5 U9 Q+ K909583 ALLEGRO_EDITOR SKILL axlPolyOperation AND operation is not working correctly.
; ~! U* g6 f# |: F! k910315 ADW LRM Import Design with ADW causes partmgr and pxl errors
8 a% G& Z) R6 U9 n# I' S8 W0 }8 e910689 CONCEPT_HDL CONSTRAINT_MGR NO_SWAP_COMP warning after uprev to 16.55 l3 h) m9 F# Q( p8 L Y
911684 CONCEPT_HDL CONSTRAINT_MGR Attribute Definitions are incompatible for attribute 'HEADER'. when attempting to place in 16.5
' }; ]. C7 |: _6 |; a' n) \912343 APD OTHER APD crash on trying to modify the padstack" m* g! `3 Q& U8 w! O* ^+ y
912384 PCB_LIBRARIAN CORE PDV Symbol Editor often freezes when moving groups objects by arrow keys# m) |8 M' e q" T5 i/ _' @8 d% y
912853 APD OTHER Fillets lost when open in 16.3.
: Q, \$ I9 T& t- i" Y913586 ALLEGRO_EDITOR ARTWORK Cannot create the drill figures in this design.& U G" T9 T- r+ x1 h( |
914009 ALLEGRO_EDITOR DRC_CONSTR Diff impedance worksheet showing almost zero impedance for differential pair in attached testcase.* K* l/ ~+ G) {5 b1 l) }
914110 CONCEPT_HDL OTHER DEHDL 16.5 Uprev overides property values on hierachical blocks. v5 d" ~. j S. d& y
914264 F2B OTHER Cross Probing from DEHDL for global nets present inside block doesn抰 highlight in PCB Editor.) M# w, c( b3 N
914309 CONCEPT_HDL CORE 16.5 DEHDL crash on saving the user design
! A! |& B | _. N2 U9 v914558 ALLEGRO_EDITOR ARTWORK Gerber6x00 output creates unpainted niche in a shape5 M9 ^2 L8 u& \
914633 ALLEGRO_EDITOR ARTWORK Artwork failing in v16.5 while the same design when downrev'd to 16.3 is working fine.7 I9 W# S6 G, a6 w( b! W- i! \5 H
914634 ALLEGRO_EDITOR SKILL IsThrough flag for a padstack is reset
8 _- e, \9 o! z5 K914746 ALLEGRO_EDITOR DRC_CONSTR DRC Update repeats takes longer on each successive pass.
) M; k4 [7 U! E, A3 _ [) w; o) t2 @914962 ALLEGRO_EDITOR SHAPE Corruption with Shape filling9 |* i6 Q/ A$ w9 _# R7 m
915583 CONCEPT_HDL CORE performance issues in 16.5 compared to 16.3
3 F# V& Q' p9 q8 G M* d915630 PCB_LIBRARIAN OTHER Error when running SI Model Interface Comparison using IBIS models" P& T4 f$ i6 ^8 [! ~; j
915742 CONCEPT_HDL HDLDIRECT I get a newgenasym error and crash when trying to save the symbol
: ] i0 @ _$ T1 s1 U. G916154 SCM NETLISTER scm crashes when exporting physical database to allegro
) q; ~1 ~/ `) {) D916448 CAPTURE NETLIST_LAYOUT Capture 16.5 Layout netlist contains errors @8 K3 f. ^* l* K7 P
916462 ALLEGRO_EDITOR DATABASE Edit>Split_plane>create hangs Allgro PCB Editor! g0 N6 @1 Z- f% M4 v1 E
916469 ALLEGRO_EDITOR REPORTS One Unrouted pin does not show in Unconnected Pins Report7 ?: ?. m' {: x7 r
916495 ALLEGRO_EDITOR INTERACTIV Pick selects components from invisible (Off ) layer
) Y/ Y( t9 n0 \3 W9 [0 b0 {916889 CAPTURE NETGROUPS How to change unnamed net group name?2 ~5 p* i, k4 m7 O4 m' B! K: w
917002 ALLEGRO_EDITOR OTHER Allegro PDF Publisher creates extra circles not available on film2 l& }* m! b7 V+ U. F/ J" |5 o
917434 APD OTHER Stream out GDSII has more pads in output data.
8 f! y6 o) _! n) ?917739 CONCEPT_HDL INFRA Global Net tied to port is getting split into 2 nets in 16.5, in 16.3 it is treated as a single net& \9 P+ R. |+ ^3 ]6 J r
918187 CONSTRAINT_MGR OTHER Missing acGetTotalEtchLength predicate.
: d% E6 Q* U( M9 W( h* Z6 q918576 CAPTURE DRC Incorrect DRC is reported for visible power pins which are connected to power symbol7 ~8 ?* I8 L Q
. E3 Z* C, g7 B( m3 Y& I
DATE: 07-24-2011 HOTFIX VERSION: 002
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7 V; X2 M- V0 C/ j% F527444 ALLEGRO_EDITOR EDIT_ETCH Slide command needs to be enhanced for same net spacings d# v) _. |' w/ v0 R9 `
583257 ALLEGRO_EDITOR EDIT_ETCH Add Connect and slide command needs to be enhanced for same net spacings.
1 {) v, U/ a4 k4 P0 l8 A592956 ALLEGRO_EDITOR EDIT_ETCH Same net traces will not push and/or shove each other.( M" c% a) |3 D+ I
745285 ALLEGRO_EDITOR EDIT_ETCH Requesting a true "shove" in Route > Slide for Same net routing.
1 X" Q$ R+ n" v& S773503 CAPTURE OTHER Doing "Mirror Horizontally" creates extra un-connects or extra junction dots in Capture V16.3.
! o1 E+ @6 r' T6 D* K& S3 _% T# M774270 F2B PACKAGERXL Require to ignore space in Pattern setting to prevent duplicated Refdes.& V( K8 ~3 O( f# [7 u1 S
799984 ALLEGRO_EDITOR INTERACTIV Enhance the Fix command to select just cline segs
: e/ u6 M0 p c& I2 d809008 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".
; S0 m1 n W: X$ k8 B: n1 d810058 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".+ S' k6 G+ L& e$ z! n- }" s9 w
821133 ALLEGRO_EDITOR MANUFACT Output artwork for pad data that are suppressed unconnected pads with Gerber 6x00 format
0 y& s1 V/ u1 }, u- ?8 f" a. k- x$ }831710 CAPTURE SCHEMATIC_EDITOR Capture adds extra junctions to design by itself
, f m1 w. [7 V7 C! V842410 ALLEGRO_EDITOR EDIT_ETCH Ability to slide with "Shove" for "Same Net" segments/vias.
0 x j* n( R- p* y, D* l1 U854971 ALLEGRO_EDITOR INTERACTIV Capability to add cline segment in a temp group, R: {* _6 c3 F9 M: H3 U7 l* U3 D; x
860772 ADW PCBCACHE Save Shopping Cart (pcbcache) is crashing component browser3 Z5 f' |7 a6 s* U9 M/ a$ Y
867842 CAPTURE PROJECT_MANAGER Capture crash with 'Open File Location"
! X2 n1 _; m* @" F: H7 m: |868306 CAPTURE CONNECTIVITY mirror vertically removes junction creates extra nets2 S3 O( T9 f9 h7 P2 \
882677 EMI RULE_CHECK bypass_plane_split fail if BYPASS_XXXX_EFFECT_DISTANCE7 g( X: W' S* N: l" q$ z
891439 ALLEGRO_EDITOR INTERACTIV moving cline segments$ }6 j0 f: K. c) A
893544 ALLEGRO_EDITOR INTERFACES IPC-D-356A netlist issue with BB vias.
/ z' ^+ ^* @: {893765 ALLEGRO_EDITOR PARTITION Mail command not sending out email on Linux platforms.! @- w0 [! _, w9 v4 Y
894390 SIP_LAYOUT EXPORT_DATA Generate all balls in the xml file for export to EDI's readPackage command
3 _' Z" x8 | ?7 }/ e895933 APD DATABASE Update Symbol shifts the center of the Dynamic Fillet and creating DRCs
) [/ _4 H$ k+ P, v& f896598 ALLEGRO_EDITOR PLACEMENT error message is misleading
, m F- b8 K- Q4 v1 ~% A897196 CIS LINK_DATABASE_PA Schematic Contents are not shown in CIS window while link Dbase part for parts placed from library% J& }* V/ b Y4 T
898598 ALLEGRO_EDITOR MENTOR Negative planes from Mentor Board Station not being translated.- \8 c) t1 c- Y* z6 }. y. k4 K
899556 ALLEGRO_EDITOR ARTWORK Import artwork seems not to work correctly.
3 _5 ^ z+ |2 H* V$ T/ N3 S900501 ALLEGRO_EDITOR PLACEMENT "lace Replicate Apply" is showing lot of DRC's during placement of replicated circuit in 16.54 D( M0 b( H7 {) W x/ s. u
901141 CIS EXPLORER Japanese character appear garbled in CIS explorer window.! h. D1 ~- t8 F( M: c
901666 CAPTURE OTHER Home page of Flowcad-Switzerland and Flowcal-Poland is not preserved on captre restart on start page& n( }$ f' v. ]2 {2 ~1 b
902066 ALLEGRO_EDITOR DRC_CONSTR Shape in Region not follow the constrains: ^ Z' J( I2 V0 E- t3 H9 L4 h
902349 CAPTURE LIBRARY Capture crashes while closing library B2 ~0 P) d$ Z' J# D* r) f; S
902508 F2B PACKAGERXL SPB16.5 Packager-XL consumes much more memory than 16.3
5 `+ m$ W0 P& D1 _! |902841 CAPTURE GENERAL Capture Start page does not show7 X3 u( f' `0 l6 @
902876 F2B PACKAGERXL Packager fails on the design upreved in 16.5
* _4 g% C. k; _& X! \902959 CONCEPT_HDL HDLDIRECT HDLDirect Error while saving design* z+ O) X* x+ S7 {$ h5 V* D' x
903171 PSPICE NETLISTER Why Capture is treating hierarchical power ports as floting nets in complex heirarchy designs?
' c! _7 D- `( T) @: x903713 ALLEGRO_EDITOR PARTITION Placement Replication do not work fine in the Design Partition1 d4 ^8 m7 a- W
903799 SIP_LAYOUT DIE_EDITOR Disappear die pins after exiting co-design die editor, t3 Y) b0 I) C. i
904021 ALLEGRO_EDITOR OTHER Export PDF from SPB 16.5 produces a file not text searchable
% N5 x6 a( z' l. A) H1 ?904339 CONCEPT_HDL CORE new design crashes using the attached CDS_SITE
! H6 s& N1 H/ n9 R8 |2 d& [904522 F2B PACKAGERXL Part will not package in 16.5 but packages in 16.3
4 M7 R; c" k+ o/ f- I904764 APD OTHER Enhance Scale Factor of Stream Out to support 4 decimal places
$ t! P9 k5 a& S9 m904771 ALLEGRO_EDITOR MANUFACT Pin Number display issue.+ ?1 |6 }8 `: h. `/ Z4 L p' Z
904853 ALLEGRO_EDITOR GRAPHICS Enhancement for showing Static shape as it was seen in 16.30 |) c( C/ A: w p$ @/ u
905144 CONSTRAINT_MGR ECS_APPLY Min Line Spacing is larger than Primary or Neck Gap less(-) Tolerance but No Warning in CM$ ?$ k3 B: N) _2 r" T1 e, Z. F
905314 F2B PACKAGERXL Import physical causes csb corruption, s9 U" u ^* I
905337 CONCEPT_HDL CORE ConceptHDL crashes after Import Design process.
1 J4 I7 t0 N# ^; X905533 ALLEGRO_EDITOR INTERACTIV Pin numbers for components on BOTTOM Side are moved in Preselect mode,when the BOTTOM layer is invisible
; |- [5 l. z' i1 R905796 CONCEPT_HDL CONSTRAINT_MGR Fujitsu CM issue inaccurate concept2cm diff pair issues
. V, g. h- f; e$ E! Q- {905811 CAPTURE EE_INTERSHEET_RE interesheet references in the form of grid grid page number instead of page number grid+ n \ M1 b" X' y( u% Q. c4 J
906118 CONCEPT_HDL CONSTRAINT_MGR Cannot open CM if SIGNAL_MODEL value was not assigned in ptf.
! v. H; ~, {3 X+ W) h906153 ALLEGRO_EDITOR SCRIPTS Unable to run allegro script in batch mode on the attached board.5 k3 a5 h; O& ~/ N: s# }4 Q& X( M
906182 APD EXPORT_DATA Modify Board Level Component Output format. e& q8 V1 `3 W: z; z# z6 {
906200 ALLEGRO_EDITOR DFA Enh- DFA drc invoked in Batch mode returns false constraint value in Show Element: \7 ~6 X: t" \) v6 g6 E
906517 PSPICE PROBE PSpice new cursor window shows incorrect result.
# h1 E) C- ?: \2 |, p5 K7 l& Y; @906627 ADW COMPONENT_BROWSE ppt options are not read if ucb is launched from FM. works fine if launched from dehdl.. r3 r0 |2 q) s7 j6 ^+ ^8 M
906647 SIG_INTEGRITY LIBRARY lib_dist creates a signoise.log in current directory (with backup files like ,1 ,2 etc.) on each run {4 Y9 O: {5 O# j
906673 F2B PACKAGERXL Ignore the signal model validity check during packaging
! b9 ]+ A/ ]: t; I) T906688 ADW LRM A copy of source design gets created in worklib of target design after 'Import Design'
$ g# J( ?1 n2 Q906750 ALLEGRO_EDITOR PARTITION Importing design partition removes the testpoint reference designation) G K* V5 w: _9 O$ I, O; `7 B
906874 PSPICE NETLISTER Error less than 2 connections for unconnected hierarchical pin- m6 }. G* }) d' J; y
907095 F2B OTHER Part Manager does not show Error as Undefined when directive ptf_mismatch_exclude_inj_prop is used4 y. Y( M8 a; J; g0 c# j4 o5 f
907424 ALLEGRO_EDITOR GRAPHICS Allegro add option for pre 16.5 shape display
7 o3 F; Q" g l907490 CAPTURE NETLIST_LAYOUT 16.5 Layout netlist is not correct. It differs form 16.3 layout netlist.
. u9 n. j7 f" q$ V3 C907884 SIP_LAYOUT MANUFACTURING Need to add an "NC" pin text option for "Manufacturing Documentation Display Pin Text"6 a+ f$ D9 r" a( c% ]1 z
907885 SIG_INTEGRITY OTHER Matchgroup targets lost when importing netlist to Allegro layout in HF31
" Z$ L% q, D0 I# ~907929 CAPTURE TCL_SAMPLE TCL command to delete a property from parts in a library is not working correctly
3 F- r5 k; [7 v0 ?3 n7 V907933 SIG_INTEGRITY OTHER Single line impedence not working in OrCad PCB Professional' h& a8 [8 ]/ U! A
907963 CONCEPT_HDL CORE Design uprev issue when moving from 16.2 to 16.5/ @+ ~3 L3 ~, X: {
908000 SIG_INTEGRITY OTHER Inconsistence z-axis delay reported on Tpoint when define at via location.3 J- f ]$ m; m% \( X- ~& T
908057 CONCEPT_HDL CORE DE HDL crash with the cut and paste of a signal name0 d9 a5 D" S- m7 h' A" @5 J! K
908060 CONCEPT_HDL CORE CTRL+LMB Option not working correctly in 16.3
P7 J( W/ ]6 A) L; ?0 g0 A# I908210 CAPTURE CONNECTIVITY Connection is being lost while dragging a component4 F: |) [8 l. X1 z" E" D5 |5 R
908241 CAPTURE DRC DRC error column is blank in DRC markers window in 16.5, K1 L' {$ h$ N9 N, G
908339 RF_PCB BE_IFF_IMPORT mechanical holes VIAFC are not at the right place; r5 p' S; w! e6 R+ w$ o0 p" z
908534 SIP_LAYOUT SYMB_EDIT_APPMOD issues with symbol editor and copying pin arrays# M6 c1 U9 F( b! T
908535 F2B DESIGNVARI When I try to view my variant file the variant editor crashes
$ A$ M, B5 P7 ]9 _* W0 R! b908595 APD 3D_VIEWER Cadence Design 3D viewer" screen pops up and is all black because the colors have all converted to b* n! ^& D% h0 C# Z3 G
908849 CAPTURE ANNOTATE Getting crash while annotating the attached design& F- O+ Y# n" y8 W/ n; R
908874 CONCEPT_HDL CORE Part Manager - No Part Found error when using CCR# 775788 feature
4 p+ }% [: I: A! m2 [1 g909077 CONCEPT_HDL CORE After packaging pin numbers remains invisible even when $PN/ S( z' J* d& l- J# F
909104 ALLEGRO_EDITOR SYMBOL Warning message needs to be modified. It does not save the symbol and also not tell the actual problem.
" {( ]. S) Z6 Y& h; a9 N4 L$ c0 `909417 ALLEGRO_EDITOR REPORTS "report -v upc" returns 'Segmentation fault' on Linux9 Y' e" P; I; j
909635 SIP_LAYOUT DIE_STACK_EDITOR Add Interposer crashes in SiP Layout
. L/ w7 I" O1 @) v8 W4 E909749 ALLEGRO_EDITOR MANUFACT Allegro Crash during dimensioning
( [9 Q7 N* t3 ?' F, A909760 SIP_LAYOUT MANUFACTURING Create bond finger solder mask doesn't follow the mask opening as defined in the padstack
# }5 W, ^3 t1 n+ R909861 F2B PACKAGERXL NetAssembler broken within the latest 16.30.031
! L7 z0 ^8 B3 r* a910006 CONCEPT_HDL INFRA Motorola design fails to uprev from 16.3 to 16.5, xcon file is getting corrupted.
% Z0 E$ j! N. r$ x1 V4 G8 A0 n5 B910141 CAPTURE NETGROUPS Modify NetGroup definition does not update Offpage Connector7 t5 x. e6 ^( m! o3 M: e- b* l
910340 ADW LRM Import design in schematic, only 1 page import, the entire block is getting imported.: M3 l/ s, S0 }& o3 v5 A1 t
910678 SIG_INTEGRITY OTHER The Analyze> Model Assignment> Auto setup is not creating/assigning models to discrete components in 16.50 O T) n9 h& G$ a. ?2 a( G' I+ U
910713 F2B DESIGNVARI Variant Editor crashes when you click web link under Physical Part Filter window.
3 @. q! X G! R* `! l910936 F2B PACKAGERXL ConceptHDL subdesign net name is inconsistent: k1 \' S* B; B0 N" K
911530 ALLEGRO_EDITOR SYMBOL Package Symbol Wizard does not create symbol with the name given
1 x% i: Y/ c6 {- `' t! f911631 CONCEPT_HDL CORE DEHDL crashes when opening a design: a F8 v( v% ^6 p; }6 k5 q
912001 ALLEGRO_EDITOR OTHER option_licenses entries are made in allegro.ini even when not set as default
+ ]6 T, }7 @/ z/ ]1 r912459 F2B BOM BOMHDL crashes before getting to a menu9 Z5 B4 n( I* B+ y Y
913359 APD MANUFACTURING Package Report shows incorrect data
) B( n* z5 X$ V- b/ v) I2 w5 ]' X+ }9 ]
DATE: 06-24-2011 HOTFIX VERSION: 001
& r' @1 w; }8 v, h) d6 {7 o===================================================================================================================================0 [; Y3 I* ]0 k9 j D
CCRID PRODUCT PRODUCTLEVEL2 TITLE
2 K5 @7 |3 n" ?- |7 v/ H===================================================================================================================================) w# C4 r: s z4 K4 t7 I
293005 ALLEGRO_EDITOR DATABASE Allegro crash when attempting to move mech. symbol& V L, O/ ~5 S6 Z$ B0 g
298289 CIS EXPLORER CIS querry gives wrong results; Q- T% i' w! ?" a8 L" Y3 ^
366939 ALLEGRO_EDITOR OTHER Cannot attach refdes on silk subclass with add text0 [4 c$ N' I/ X+ z5 i. `
432200 ALLEGRO_EDITOR MANUFACT Fillets with an arc are required for Flexi designs
- u: y* }! k) b" }8 A443447 APD SHAPE Shapes not following the acute angle trim control setting.
# n7 W6 U& ?3 P5 N' q1 ~2 d+ a. I- e473308 PSPICE AA_SENS Passing variables to lower level blocks using subparam
s0 ^6 \' `$ _+ Q* }* e517556 PSPICE AA_SENS Advanced Analysis does not support variables being passed down the hierarchy
7 W, `" `3 U: p: h548143 ALLEGRO_EDITOR SHAPE Dynamic shpe on Etch TOP will not void properly.: R0 h$ A- ~& k( v2 _3 G" T
606959 ADW COMPONENT_BROWSE Key properties with blank values are not getting read in shooping cart
" F5 P2 O6 ]) i6 H616466 ALLEGRO_EDITOR SHAPE Solid shapes are not getting filled
. C- \( {, p! l5 f, @! n641358 SIP_LAYOUT DIE_STACK_EDITOR Request for Via and Multi Layer Pin support for DIE stack Area (blue region)% ~+ Y6 J$ o$ R4 r, |
644122 SIP_LAYOUT OTHER SiP Layout - xsection - ERROR Adjacent conductive layers are not allowed, but these are diestack layers not conductor
. U$ S+ G; w' v9 l n+ t6 m+ F645816 ALLEGRO_EDITOR SHAPE Slide a cline all removes gnd shapes on board
7 o6 l2 K5 u& H$ f* n" l725355 ALLEGRO_EDITOR SHAPE User can not voided Logo correctly.
2 N. V. l; T" i* o2 D1 |763569 CONCEPT_HDL CORE Display status of Hide/Show unconnected pins icon in DE HDL UI v, S! J2 {+ M% ~
770021 CAPTURE BACKANNOTATE Changing pin group property after pin swap resets pin numbers; M+ J% M9 H& Y# i
792126 CAPTURE PROPERTY_EDITOR Attempt to change display for occ prop resets0 X7 i9 m5 T' G7 j
799014 CONCEPT_HDL CONSTRAINT_MGR concept2cm errors not shown in export physical after hier_write- i9 I- u4 t' P: T, h) L& ?
803147 CIS LINK_DATABASE_PA Link DB part should not change RefDes of multi package part
( S4 z- D4 p/ ]804240 PSPICE DEHDL Problem in simulation result for a multi-section split part.( O* q" k2 `$ g; e$ x2 ?
809118 CAPTURE NETLISTS ENH to compare two schematic Capture designs* u9 ` c d* B0 V/ `# T) q" ?
816568 ALLEGRO_EDITOR SHAPE shape disappears when update to smooth.. State no etch
7 }# _0 Z7 `5 ]1 t830053 CAPTURE STABILITY DXF export fails if schematic folder name as /
4 w8 ]/ @/ M/ Y- d832108 ALLEGRO_EDITOR SHAPE Shape void incorrectly.
8 x4 }4 e" z% m" }5 g8 k833542 CONCEPT_HDL CORE PDF publisher font is NOT WYSIWIG with respect to what seen in DE HDL
3 D( G E2 c1 P5 L835777 CIS DERIVE_NEW_DB_PA For XLS, donot display table as worksheetName$worksheetName to avoid 8012 error6 i' s5 [6 ~$ `5 r7 w
837640 CIS GEN_BOM date format of CIS BOM has broken macros of 16.2 in 16.3 version
- n3 w/ X3 U: d4 |" Q( ?5 D844074 APD SPECCTRA_IF Export Router fails with memory errors.: U. f+ _. ?- O: L7 J2 \
851595 CONCEPT_HDL CORE Pin numbers overlap on the pin and increase in size1 w4 j F; ^. k
852832 CAPTURE BACKANNOTATE Why is Capture crashing with Mentor back annotation?6 o) }) Q2 N5 m
855015 ALLEGRO_EDITOR OTHER The rats are NOT connecting to the ends of the clines like they should be.
3 ?) h5 @2 z3 j2 ]859883 CAPTURE NETLISTS ENH to compare two schematic Capture designs5 V/ w) ]. P' J: X
866009 SIG_INTEGRITY OTHER Net with Pull-up/down should not be used for Diff-pair.
& P9 s9 }* N) M# w- c/ t' f866830 SCM REPORTS Multiple lines added as separator between title block and report header instead of single line2 Q3 w! p/ h/ w% z: H4 Q
866833 SCM REPORTS Extra indentation is left in the left side of the report when the Line Numbers are set to OFF
2 [3 o7 Q% o" l3 I6 G868618 SCM IMPORTS Block re-import does not update the docsch and sch view
s( E6 H3 v i9 F* n; N0 n* h4 ?873402 SIP_LAYOUT LOGIC pin swap for co-design die in SiP
# w5 ?! _2 t; A4 r874010 SIG_INTEGRITY OTHER PCB SI crashes when the Xnet is extracted with VARIANT_TO_IGNORE property.9 Y) U& ]- o% P& p: ^9 G, h. j9 C
874400 ALLEGRO_EDITOR INTERACTIV Flip mode issue with move command, `- {- J8 t M2 ?
874966 ALLEGRO_EDITOR INTERFACES Placed mechanical component do not get Ref Des or part number in IDF file9 d' C/ [: v7 l- p" P
875709 ALLEGRO_EDITOR REPORTS Film area report generated incorrect data at l1
7 Q7 s$ J% @0 N" {/ S' ^& U- f; g ]876275 CONCEPT_HDL CONSTRAINT_MGR Constraint Manager not retaining target net
9 V6 V: t# {; t- z1 }879361 SCM UI SCM crashes when opening project
+ E3 E2 u. K7 Y7 w d6 L2 h879496 CONCEPT_HDL OTHER Customer wants to have the tabulation� key as separator in HDL BOM.
9 _5 j3 e0 | E9 L+ B879514 PSPICE AA_MC Monte Carlo to handle equation as comp VALUE." j/ Z% ` ?; ^' [, b ?
881845 ALLEGRO_EDITOR SHAPE Delete island deletes complete shape
$ q- [2 D( W! |# A Z6 g y+ x; f882413 PDN_ANALYSIS PCB_PI PDN Analysis should support routed power nets
. a4 {+ f: Y2 F/ c882427 PDN_ANALYSIS PCB_PI PDN Analysis target impedance should have a variable multiplier
8 K B& j% k) F; ]882567 SIG_INTEGRITY OTHER PCB SI crash if boolean type prop was specified to VARIANT env.$ N5 o4 z7 [) z8 T5 U3 n) q5 N
882644 ALLEGRO_EDITOR PLACEMENT PCB Place Replicate Function automatically match Enhancement% u. t& x" b7 V, f( U
883164 ALLEGRO_EDITOR INTERACTIV Vias marked fanout moves away from position when moving component
5 }# g+ M4 J- _+ X1 ~4 g883224 SIG_INTEGRITY SIMULATION crash while reflection simulation from Constraint Manager* @" ~; y5 M4 `! `
883760 PCB_LIBRARIAN METADATA Incorrectly formatted revision.dat file in the metadata folder( s9 N6 X; Z! H% P* J# y
885391 SIG_INTEGRITY SIMULATION RLGC data sampling algorithm and w-element interpolation.' I& x% s) J, Y& p+ s
885849 ALLEGRO_EDITOR MANUFACT Silkscreen Audit cannot find Solder mask for the text string. v( O7 ?0 }4 r5 u1 J' R' O
885996 SIG_INTEGRITY OTHER The effect of sn_maxwidthlimit user preference is not seen in cross section impedance calculations5 g8 M e* S0 H/ }1 \- U
886090 ALLEGRO_EDITOR INTERACTIV Add Arc w/Radius does not snap to grid: G" [" W$ ^5 \1 {3 u% a
887180 CAPTURE SCHEMATIC_EDITOR Signals Navigation window doesnt get updated for Buses2 D/ M- O) k, h- n) W/ h# V
887442 APD SHAPE Copper pour of Dynamic shapes on Top layer which contains many existing signal traces fails.
7 c' i8 r( P. I; |4 S9 G/ L887578 SCM AUTO_UI Component Replace pops-up the DSPANE-204 Message
* W) p5 g/ I; S( u6 Z+ K887926 SIG_INTEGRITY GEOMETRY_EXTRACT Field solution failed if diff trace on bottom doesn't have reference plane.: J5 L. q& V9 {+ ?# M
888414 SIG_EXPLORER OTHER View Trace Parameter display the thickness of dielectric incorrectly.& g [* v' C( W2 d- ?& e
888600 CONCEPT_HDL CREFER Cross References not added to Schegen schematic) c0 q/ K* A% u8 `/ r: u7 B7 k$ w
888679 SIP_LAYOUT SHAPE Can't create the Dynamic shape on layer M1_sig without unwanted horizontal openings appearing.% e* V' W# E' c
888804 ALLEGRO_EDITOR OTHER Fillet will become static shape after import from partition board.4 s( J% ^7 b/ f8 E6 }9 s
888945 CONCEPT_HDL OTHER unplaced component after placing module7 Y! S( H. s' C/ t6 o
889222 ALLEGRO_EDITOR SHAPE Allegro freezes/hangs when adding shape as Polygon with OpenGL ON., `7 T4 e# u7 H5 g+ Z) [8 _
889365 SIG_INTEGRITY GEOMETRY_EXTRACT top/bottom trace impedances extracted to sigxp are wrong in 16.34 [. D8 g2 S* b! p) V
889404 ALLEGRO_EDITOR OTHER Incorrect pad size for Top conductor padstack written to column 59-62.
# a' c! Q* H) {7 a) q889426 CONCEPT_HDL CHECKPLUS CheckPlus does not find single node net
( [3 }& w$ s6 m9 U( h1 f. s889636 ALLEGRO_EDITOR MANUFACT Incorrect spelling of "Visibility" in "Film Control" tab in the Artwork Control Form# b, L2 N9 h5 d2 A
891235 F2B PACKAGERXL Packager crashes without creating a pxl.log file
6 H$ c3 J+ |# p' k& X6 H891292 ALLEGRO_EDITOR SHAPE arc routing causes weird undesireable shape fill performance
* ~: {+ B/ N/ K2 m+ I3 _8 A891856 ALLEGRO_EDITOR EDIT_ETCH crash when sliding diff pairs: u* `6 v+ |2 D7 P3 S- @
892375 ALLEGRO_EDITOR PLACEMENT Place Replicate Update disband other groups, irrespective Fixed property added or not.
8 @3 R; f! T; E* U# {6 @) ~$ [892455 ALLEGRO_EDITOR SYMBOL Why the overlapping pins are not reported with DRC?/ s* @7 g* J, }" _" E7 r* m
892541 SIG_EXPLORER OTHER Export/Import layerstack through the technology file is changing the layer thickness) X( z0 `& h; u" Z
892766 APD WIREBOND Excuting Finger moving cannot push aside finger to move with together by shove all mode3 a* r4 T5 r* H( Z0 O6 N
892907 ALLEGRO_EDITOR DRC_CONSTR DRC not reported for etch_turn_under_pin violations1 y, v, v: w1 j5 O3 a# K
892963 ALLEGRO_EDITOR SKILL Bad shape boundary created after axlPolyOperation 'OR
q. x9 ]! J+ f+ O6 D9 E892964 SIP_LAYOUT LOGIC Request that Edit Parts List use Dashes "-".2 o$ m& [4 d) O; F
893295 APD WIREBOND Why move wirebond command does not shove wirebonds? This result in drcs.
/ p' I( G. g6 b" u% v* s3 q5 N# z1 ]5 s893706 CONSTRAINT_MGR OTHER On line DRC hangs on partitioned board" R. d8 p& w1 m) i
893743 APD EDIT_ETCH Route behavior when spanning pads not as expected.+ J3 h( e6 f5 O& r- k
893783 SIP_LAYOUT OTHER Padstack Design Editing update File menu with a Update to Design and Close instead of 2 operation
8 f; L. i; b) h/ |5 j# w894456 ALLEGRO_EDITOR REPORTS Request Net names be added to Propagation delay lines of the DRC report.6 Q% `/ S; E& G6 O9 E7 G3 h
894499 SIG_INTEGRITY LIBRARY Tool crashes when moving a cline or selecting the Info icon with OpenGL on.
5 n9 m4 g d# ^0 N894582 APD SHAPE When making a dynamic xhatch Via shapes surrounding are abnormal.' Z" M! h! |/ d
895542 SIP_LAYOUT WIREBOND SIP design crashing when moving bond finger using blur mode BLUR_BONDFINGER_PRESRV_CON
% ?( `( B' i- O9 V' d895591 ALLEGRO_EDITOR PCAD_IN Importing PCAD file fails to get to the point where we can map layers! e6 T1 y' s9 J; U4 W8 Y
895757 APD ARTWORK Import Gerber command could not be imported Gerber data
0 V# k. b' I2 ^& d5 ]8 m895964 CONCEPT_HDL CHECKPLUS The CheckPlus command getFileSubstrings is not working correctly
1 I# h! D0 M% u- l896428 SCM UI Changed Ref Des value not maintained in DEHDL block when part is replaced
$ Z# h+ m+ f9 N9 z896655 CAPTURE EDIF Import/Export Design of Hierarcy design with OrCAD Capture6 e: W% E9 d7 q9 w1 D4 u; z# R
896846 CAPTURE IMPORT/EXPORT Import edif2cap and capture is crashing
1 m' L$ j8 B3 Y" _/ ^897155 ALLEGRO_EDITOR REPORTS Copper coverage in L2 and L7 looks like the same but film area report had large gap.( A/ w2 o3 B4 @" t/ @, }+ L+ g
897654 CAPTURE EE_INTERSHEET_RE Capture crashes on adding intersheet refernces in abbreviated format on attached design.2 M$ B' Q9 N& p
899344 RF_PCB BE_IFF_EXPORT dlibx2iff does not provide the component boundary drawing
" }% h, b7 ?) p6 ^# u2 M899629 CONSTRAINT_MGR OTHER ECset for Total Etch Lenght is not present in OrCAD Prof# s9 @. _8 X7 N- l& {
900175 CONCEPT_HDL CONSTRAINT_MGR Few Xnets are lost from Match Group after packaging and importing the netlist to board file.2 y" `* B2 l" N W# @ u0 ~
900481 CONCEPT_HDL CORE Genview creates a larger symbol without taking the no. of pin in consideration4 ?/ P9 ?5 L' E0 j! d
900813 ALLEGRO_EDITOR DRC_CONSTR With rotated pads, pad (pin - via) soldermask spacing DRC is unreasonable.& b+ M4 d; Q; n4 b% i
900905 PSPICE STABILITY Simsrvr crash and RPC Server unavailable error while running simulation.# L. Q: S2 R5 h' q1 X$ q$ H* q
901783 CONCEPT_HDL CORE CDS_PART_NAME is annotated on the schematic canvas after running back annotation in 16.5
) ~& R2 n G; s# w+ y5 k1 Z901909 APD EXPORT_DATA The "package_pin_delay_length.rpt" with Z-axis delay turned on seems wrong
& l( w* j( D/ t7 f901987 CONCEPT_HDL OTHER SPB16.5 zoom fit does not center the page while ploting the schematic page
n- {, x- c+ s Z902133 CIS OTHER The visible part property value are being shown very distant from part graphics on schematic! J- |! X. b3 p. Z% x
902166 SPECCTRA ROUTE Specctra crashes when reading in "bestsave.w" file
! A7 t% B; J4 p6 F- I902170 ALLEGRO_EDITOR DATABASE Diffpair Issues with OrCad PCB Designer Professional( M0 o7 [. S3 A# X$ {$ O
902177 CONSTRAINT_MGR CONCEPT_HDL Option to view the layer thickness in CM worksheet through worksheet customization9 m$ Y2 D$ _: e" U# I* L6 h% m7 c% x
902463 ALLEGRO_EDITOR INTERACTIV APD crashes when we click ( show element ) on certain components% [4 f4 b" b: R0 A8 i: d
902621 CONCEPT_HDL OTHER Design Differences (vdd) Crashes
* C( v! u6 Z4 }0 `. {3 q902909 APD WIREBOND die to die wirebond crash& r+ w0 e# ]& ?6 H6 ]7 _: x
902933 ALLEGRO_EDITOR PADS_IN Pads_in fails while reading PADS ASCII file body
2 l' W) z) P) x( F5 {903284 PDN_ANALYSIS PCB_STATICIRDROP IRDrop voltage gradients are plotted outside of the PCB outline
. A t) c f. K: T, `8 ?" n903680 CONSTRAINT_MGR ECS_APPLY Constraint Manager not passing all hiearchical member objects to a custom measurement.3 O! z- M) z, n2 E2 l5 |1 R
904403 ALLEGRO_EDITOR DATABASE Allegro crashes when refreshing module |
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发表于 2012-2-21 14:58
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发表于 2012-3-8 15:09
