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偶也跟一贴！
4 x1 @3 j' {' B1 C' m以下内容来自《high speed digital system design》。/ f) e, o, x# \4 M
% c/ _; a5 G0 m3 O5 f; Q( `A via is a small hole drilled through a PCB that is used to make connections between various. y7 z+ ] s. U3 J
layers of the PCB or to connect components to traces. It consists of the barrel, the pad, and
7 m# M' x. e, k! [$ I2 Q' e; m7 ]the antipad. The barrel is a conductive material that fills the hole to allow an electrical
& q& j$ F3 E' s0 ~/ d2 i9 n9 U& Rconnection between layers, the pad is used to connect the barrel to the component or trace,/ g1 D0 b) @) d
and the antipad is a clearance hole between the pad and the metal on a layer to which no, i. ?/ R9 \3 t' \$ F# L; I$ b
connection is required. The most common type of via is called a through-hole via because it
@ W$ c. @, h! fis made by drilling a hole through the board, filling it with solder, and making connections on9 C8 g+ ?% A; `$ v
appropriate layers via the pad. Other, less common types of vias, used primarily in multichip
, R1 n% d9 d* [3 }0 umodules (MCMs) and advanced PCBs, are blind, buried, and micro-vias. Figure 5.1 depicts5 p0 \5 h+ z6 V. I2 x6 R/ U* x( ?- W
a typical through-hole via and its equivalent circuit. Notice that the pads used to connect the
6 b* g% a( p2 P5 Rtraces on layers 1 and 2 make contact with the barrel and that there is no connection on
) ~" D& g) f! `! slayer 3. Blind and buried vias have a slightly different construction. Since through-hole vias* H/ {% e h6 z8 s" ~' n" ^( x
are by far the most common used in industry, they are the focus of this discussion.
: ^ Z4 _4 q V7 T3 ~
+ A7 ?2 U) S7 XNotice that the via model is simply a pi network. The capacitors represent the via pad
% v# u$ G ?5 I3 G0 E$ wcapacitance on layers 1 and 2. The series inductance represents the barrel. Since the via
$ ]7 S/ j: ^: J. Lstructures are so small, they can be modeled as lumped elements. This assumption, of
! j7 L- V/ b* E3 Y* {. }course, will break down when the delay of the via is larger than one-tenth of the edge rate.
1 T0 l% @" K2 ~3 }The main effect that via capacitance has on a signal is that it will slow down the signal edge) M9 [! v" N% C5 V2 z- K9 g. L/ _- O
rate, especially after several transitions. The amount that the signal edge rate will be slowed
S4 F; e8 b5 |# Scan be estimated by examining the degradation of a signal transmitted through a capacitive
/ O6 Y4 @: |' D9 _load, as shown later in this chapter in equation (5.21). Furthermore, if several consecutive% K# P: z/ E; O+ }4 Z! N8 ^: X
vias are placed in close proximity to one another, it will lower the effective characteristic
" s. Y2 T& I' z* w4 D g, ximpedance, as explained in Section 5.3.3. The approximate value of the pad capacitance is0 k# \- v! Z/ h& L4 j
[Johnson and Graham, 1993]
+ k% L8 g7 ]2 ]) h! K3 k
' _7 o; }! ]- D
[ 本帖最后由 killerljj 于 2007-11-21 20:51 编辑 ] |
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发表于 2007-9-11 14:20
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7 E" a8 x& q) O. c7 ^
发表于 2007-9-15 15:34
俺也顶一下,因为焊盘描述的太形象啦!
发表于 2007-12-19 08:39