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画完原理图后,导入LAYOUT时,弹出arsii.err文本文件提示以下内容:0 `' |# \7 ~8 N+ D6 S! o% s
3 w# @6 R% D+ T3 i& ?+ U0 o, W- DReading file -- C:\PADS Projects\padsnet.asc; F, _0 Y' H) Q( a* u. W, \6 X7 C5 m
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal C54 v- t* H A% i/ a, J' D( i# B
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal C4+ x$ D% J; ^. {9 U) r
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal C3
' ?+ i6 ~- b& q+ Q% O*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal C2% \' d: o {( C/ w' k: z, y! s- ~2 T3 s
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal C1: P+ J' v/ Y7 S2 |0 Q5 r
Warning: deleting signal C5
8 `. H$ \2 ^2 MWarning: deleting signal C48 ~. T* i! J# g
Warning: deleting signal C3
4 r3 y* I2 b1 J2 F) p' ^- CWarning: deleting signal C23 B+ z3 l$ u w* ?
Warning: deleting signal C1
: ?. `: y8 g. }9 m$ C**INPUT WARNINGS FOUND**/ m* ~5 q+ i |. }
# U3 D' j+ v# W3 V6 R我检查了下,封装和连线应该是没有问题的,并且在这个原理图中,除了以上所提示的C1~C5之外,同时从库里调出的这个电容也用在了其他位置,却没有提示出错。
0 q& B% Q4 m+ m' T9 H9 }想请教下各位看官,这是个什么情况? |
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