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Fixed CCRs: SPB 17.2 HF021
( n& O! N, Y9 \" J) z" f) X* G06-3-2017$ u+ E% B W' T O, i" Q W
========================================================================================================================================================
9 U/ T) f8 K5 C' vCCRID Product ProductLevel2 Title
( r/ {7 B" ?% R* B! X========================================================================================================================================================$ ~8 Z* p6 |. b1 Z3 s" d% M
1401318 ADW DBEDITOR Bulk Edit - Previously modified cells do not turn blue when selected
) B( c' {( c- T' y/ d1621446 ADW DBEDITOR Bulk Edit - sorting highlights incorrect cells to mark them as changed
0 l9 X4 f/ u4 P1743997 ADW LIB_FLOW Match file for standard models is incorrect6 Q' ?" i Q4 a+ Y' {% ^: O
1746052 ALLEGRO_EDITOR DATABASE PCB Editor crashes when applying no drc property
1 E' |0 [& V0 `# O! R1736067 ALLEGRO_EDITOR DRC_CONSTR Interlayer checks not reporting DRCs between cline and mask layer, f, m% F* Z b' L7 m% U8 ]1 q
1738587 ALLEGRO_EDITOR EDIT_ETCH Line width changing on slide for ETCH - Conductor (Not on a NET)
, d3 H: X' W: w9 Z ?: m% e5 b1745277 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on using the slide command
. K5 g5 `( c9 \8 Q g1747942 ALLEGRO_EDITOR EXTRACT Fabmaster Out does not export arc in pad_shape
3 R* |" V) n6 O% H9 I4 b& i1737202 ALLEGRO_EDITOR GRAPHICS Setting the variable display_raster_ops. t+ g5 g- u W2 a$ y
1744042 ALLEGRO_EDITOR GRAPHICS Unused pad suppression is not working on few nets
\: A' a. Y9 X# Z2 W; z3 W x1703848 ALLEGRO_EDITOR INTERFACES IPC 2581 fails with error 'E- (SPMHGE-268)' and the log file is empty/ v1 U" Y5 s, E2 O4 {
1743899 ALLEGRO_EDITOR MANUFACT Glossing dangling vias crashes PCB Editor$ s P$ U1 A- C1 s$ X. y
1744467 ALLEGRO_EDITOR OTHER The 'logical_op_new' variable is not displayed in User Preferences Editor& n! o( @$ H: y; L; |8 }
1748520 ALLEGRO_EDITOR OTHER TDP fails to load on an empty database
9 ?+ B. v5 k3 v5 c$ c) R1 N& _1748581 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crashes when changing default pad geometry2 W9 ]9 s/ C5 [6 G
1751469 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crashes/freezes when browsing for a shape symbol8 G! ]! C/ i' k: @( }0 z$ ^" i7 ^6 Q
1725948 ALLEGRO_EDITOR SHAPE Shape differences after conversion from release 16.6 to release 17.2-2016. {: e8 y# [5 a0 E1 l, Z
1729306 ALLEGRO_EDITOR SHAPE Seting shape_rki_autoclip variable causes no void to be generated% G5 F- u6 j j4 O2 i
1698876 ALLEGRO_EDITOR UI_GENERAL Tabs are large and text is compressed in release 17.2-2016& f& h' {& L5 ^$ o9 c
1698883 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, enlarging icons makes selection boxes/text unreadable on 4K monitors; P9 l0 k6 Z3 y. I" X/ v
1707933 ALLEGRO_EDITOR UI_GENERAL axlUIMenuFind not locating menu as per x_location* F2 p/ D2 a9 M0 D8 M5 d* Q' K
1741460 ALLEGRO_EDITOR UI_GENERAL Right-click, context menu options grayed in some cases after choosing Edit - Copy8 h6 q2 }) P' w
1747588 ALLEGRO_EDITOR UI_GENERAL Interacting with PCB Editor by sending messages is not working& C/ [6 N2 H2 i9 p6 ^2 \
1747488 APD EDIT_ETCH Route connect is improperly affecting existing routes in locked high speed via structures" }+ R( Q% F# @! l: @: ^! h
1750182 APD STREAM_IF The stream out settings are not saved; n1 J1 M, q) ~3 N. _9 O
1752067 ASI_SI GUI Links to differential waveforms do not work in Sigrity SI report/ o- x5 l6 S# S& S! _
1752131 CONCEPT_HDL COMP_BROWSER Symbol view in part manager doesn't match the symbol version* H6 o; B" Y4 G# l- H8 B
1754116 CONCEPT_HDL COMP_BROWSER Default Symbol selected is n°2 instead of n°1 in component Browser
! x' T8 H8 |7 T+ e# b" ]) D, c1754949 CONCEPT_HDL COMP_BROWSER Part Information Manager displays preview window with the wrong symbol and missing footprint% g) [5 D, P. e( e0 d3 t
1721334 CONCEPT_HDL CORE dsreportgen not able to resolve gated part on schematic; X. v: c# U5 C% E' L+ ~! n
1750916 CONCEPT_HDL CORE DE-HDL crashes when trying to uprev a project in release 17.2-2016 B1 z1 z" j; {5 } _% \- ?9 C
1711487 CONCEPT_HDL INFRA Restrict opening of release 16.6 designs from a release 17.2-2016 design using File - View Design( J8 i. s X, @( P) Q2 \" @
1746915 CONSTRAINT_MGR CONCEPT_HDL Unable to copy a Physical and Spacing CSet generated from the Constraint Automation flow
' Y3 U* c; x# A1743523 CONSTRAINT_MGR DATABASE Suppress warning pop-ups from the constraint automation script
5 z& n- F8 |* P: Z1746941 CONSTRAINT_MGR UI_FORMS 'Go to Source' from DRC tab is not working in release 17.2-2016$ X, U3 d8 |+ {# e
1753010 ECW METRICS Metrics not getting collected due to old license in use
" N: g0 r4 H. v2 j* H, a: ~+ q0 q/ T U1713052 FSP GUI Pin/Port Name and Group Name are not aligned properly in FPGA Port and Use Pin Mapping for DeviceInstance
/ |9 q' y# G0 ?' h5 M1 V1719099 FSP GUI Net naming wrong after building block
. j% ?8 G% j3 A4 `1719105 FSP GUI Tabular sorting not working in FPGA System Planner' Z {: o: K, p, s1 N
1720479 PSPICE ENVIRONMENT Probe window does not open consistently on Windows 10 systems Q$ T9 ]! l! U; t) c' I/ @
1723411 PSPICE ENVIRONMENT Probe window does not open consistently on Windows 10 systems# U/ l6 f+ n( g
1746628 PSPICE ENVIRONMENT PSpice Simulation Manager displays same message for all simulations in release 17.2-2016, Hotfix 016
& u5 v! T, m& G" b9 f( e1745976 SIG_INTEGRITY GEOMETRY_EXTR Arcs with coplanar waveguides are extracted with incorrect spacing8 Z1 R n8 \, Y3 l& W7 e
1690820 SIP_LAYOUT PLATING_BAR Cannot add fillets to pads with plating bars in release 17.2-2016
# q# n: i T- M. D$ n- F9 a" z9 K$ S6 A1725042 SIP_LAYOUT PLATING_BAR Creating a plating bar removes dynamic fillets
/ S! S3 x5 ~1 p+ O, c9 i1747534 SIP_LAYOUT SHAPE Moving fiducial crashes SiP Layout) E4 C( v9 J( s' V% O
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发表于 2017-7-2 18:37
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