17.2 hotfix001-004更新点

金志峰

$ @' A; ^, j9 H/ Q  cDATE: 08-14-2016   HOTFIX VERSION: 004
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" o8 W( n5 G! |( W& M* DCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
9 @: H& M( [& W. g& a2 X===================================================================================================================================
908816  CAPTURE        SCHEMATIC_EDITOR Few graphical operations are active even when a page has been locked
1213923 ADW            LIBIMPORT        Cannot delete parts in the Library Import project (XML)
1250476 PCB_LIBRARIAN  LIBUTIL          con2con does not check for PACK_TYPE
1306441 APD            OTHER            The Minimum Shape Area option in Layer Compare uses an unspecified value
1322242 ALLEGRO_EDITOR INTERFACE_DESIGN Using add connect together with replace etch Option is causing the tool to slow down for certain constraint nets
1326716 ADW            DOCUMENTATION    Dataexchange documentation correction needed
" P% W% q  S+ o4 K: C- z: Z7 b1356948 APD            DEGASSING        When using the Degassing tool on shapes the size of the file becomes very large
7 Q2 D6 n+ s' x* L1376510 ADW            DBEDITOR         DX output ERROR after Property Display Ordering of Part Classification.
1408218 ALLEGRO_EDITOR MANUFACT         Specifying the Offset value results in unexpected value of the NC Route coordinates in the .rou file
5 t/ H8 u' b' F2 M5 A1410485 CAPTURE        SCHEMATIC_EDITOR W shortcut and Autowire active on Locked design
1413248 CONCEPT_HDL    CORE             Import from another TDO project makes the block read-only
- c9 j+ z$ P, @% F( a! |" e1413287 ADW            LIBIMPORT        Library Import uppercases all Attributes when reading CSV
( x) M6 ?8 Z% S, w( o  H1417429 ALLEGRO_EDITOR INTERACTIV       Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle
1417442 ALLEGRO_EDITOR INTERACTIV       Spin via stack and only part of the stack spins
6 M1 d, q" l7 X; N6 h1430251 ALLEGRO_EDITOR PLACEMENT        Quickplace placing symbols outside of a polygon shaped room
) l& b# z0 x& J( Z5 b  D1440509 ALLEGRO_EDITOR PLOTTING         Ratsnest do not follow the refdes position when plotting the BOTTOM layer with the 'Mirror' option
1441086 PCB_LIBRARIAN  OTHER            Changes made to a package with sizable pins generated from the sym1 view are not saved
1443339 PCB_LIBRARIAN  PTF_EDITOR       ALT_SYMBOLS syntax in PTF file not checked
1444144 ALLEGRO_EDITOR DRC_CONSTR       The 'add taper' command generates line to line spacing DRC
1451766 CONCEPT_HDL    COMP_BROWSER     License error message should indicate which license is required
1 V1 a9 F, T0 q1451977 CONCEPT_HDL    PDF              Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set
1457138 CONCEPT_HDL    CONSTRAINT_MGR   devices.dml: difference in content generated by _automodel add command and Constraint Manager launch
1458439 F2B            PACKAGERXL       The Packager pstprop.dat file reports false conflicts in net properties
9 b# D5 H7 ^% V. [8 d) x# M9 v1464865 CONSTRAINT_MGR ANALYSIS         For identical nets, topology in DE-HDL CM is different from the topology in PCB Editor CM
1464948 PCB_LIBRARIAN  VERIFICATION     The errors/warnings do not match between the various tools
  O; E; f8 N3 S# J0 n1467826 CONCEPT_HDL    PDF              PublishPDF from Console Window creates a long PDF filename
# S9 f8 l+ S% V1470106 ALLEGRO_EDITOR MANUFACT         silkscreen program cuts auto-silkscreen lines excessively
1471287 CONCEPT_HDL    CONSTRAINT_MGR   Importing pages from other designs with different units should inherit the source constraint units
1472046 ALLEGRO_EDITOR OTHER            Gloss routine, 'Via Eliminate' - 'Eliminate Unused Stacked Vias' is not removing unused microvias from the stack
0 r9 R4 Q# K3 h9 R. m, |1472414 ALLEGRO_EDITOR SCHEM_FTB        netrev changes pin-shape spacing rule in constraint region
2 V1 y2 _9 ?- m' W0 p. K1472444 ADW            ADWSERVER        Multiple errors in adwserver.out after SPB 054 / ADW 47
; @0 G$ v# G- c$ F6 N* h/ j1473056 ALLEGRO_EDITOR ARTWORK          Gerber export has additional phantom data not on design
1473900 CONCEPT_HDL    CORE             DE-HDL stops responding when a hierarchical block with variants defined inside the reuse block is enabled
5 M5 t5 Z" o5 |1474020 ADW            DBEDITOR         Unable to modify schematic classification when a part is checked out previously by another librarian
1474066 ADW            DBEDITOR         Bulk edit performance lags when parts included have large number of properties
1474764 ALLEGRO_EDITOR PLACEMENT        In Hotfix 56, the 'place replicate create' command does not produce desired results if a fanout is marked
1474894 ALLEGRO_EDITOR PLACEMENT        Place replicate fails to include vias when the module is applied to other circuits.
- p; ^4 Q% m% R- o7 {" [9 F1475650 ALLEGRO_EDITOR OTHER            Using Outlines - Room Outline gives WARNING (axlRemoveNet): No match for subclass name - 'BOARD GEOMETRY/__EPB_SCRATCH_'
5 x: O$ s2 g" T0 h1476528 ORBITIO        ALLEGRO_SIP_IF   While translating a .mcm to OrbitIO, the error 'allegro2orbit.exe has stopped working' is thrown
* k; l- T. O  A/ N0 ?9 u" }% V0 M1476920 CONCEPT_HDL    OTHER            Genview consistently fails in some indeterminant manner.
1477369 CONCEPT_HDL    INTERFACE_DESIGN A significant number of problems are reported when running genview with port groups
9 ]* `' f& ~7 u- X6 F1478111 F2B            DESIGNVARI       Hierarchical block variant not shown in testcase with S57 although it was working with 2015 release
$ u+ p/ I+ H& C4 p$ e# G1478200 GRE            IFP_INTERACTIVE  Allegro give error "Low On Availlable Menory" and then crash
# g  o' H7 F# u7 A1478680 CONCEPT_HDL    CORE             Unable to move components in a schematic using the arrow keys
7 s$ m, M1 @9 {5 F( G$ a5 g6 T1479135 F2B            PACKAGERXL       Hierarchical design reports conflicts when signal names change through the hierarchy
2 q1 A$ c+ J8 r% t3 W1 V& G. ^1479153 CONCEPT_HDL    CORE             File - Save Hierarchy flags an error and does not update subdesign xcon
1479227 CONCEPT_HDL    CHECKPLUS        Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy
1479454 CONCEPT_HDL    OTHER            DE-HDL issue: locked DIFF_PAIR property is editable
- U/ P+ I7 w5 f6 ?( M5 @7 N1479569 PCB_LIBRARIAN  OTHER            hlibftb fails with error SPCOPK-1053
1479785 ORBITIO        ALLEGRO_SIP_IF   brd file does not get loaded in OrbitIO
1480005 ADW            DBEDITOR         DBEditor/DBAdmin GUI do not allow the same characters in Property  as LibImport CSV Files
1480367 SIG_INTEGRITY  OTHER            Differential pair extraction SKILL error, 'parseString: argument #1 should be either a string or a symbol'
1480499 ALLEGRO_EDITOR PARTITION        Cannot delete partition
1482544 ADW            DBADMIN          Hierarchical PPL not functioning correctly
1483136 ADW            COMPONENT_BROWSE About searching the parenthesis or comma in Component Browser of ADW Mode
) f% f4 b; @* E( `6 ]4 D1483617 ALLEGRO_EDITOR DATABASE         Delete islands command crashes database with filled rectangles
1484100 SIP_LAYOUT     INTERACTIVE      Tool crashes when copying and rotating a symbol
1484781 CONCEPT_HDL    CORE             Three different Hierarchical Viewer issues
1485059 PCB_LIBRARIAN  CORE             Part Developer pin attributes are randomly marked as read-only
1485931 ALLEGRO_EDITOR INTERFACES       Errors generated when importing IDF in an existing board file
4 S( |6 X. d+ ?" z# Y  P1485960 CONCEPT_HDL    CHECKPLUS        Custom DE-HDL Rules Checker rule is crashing the project
6 M2 L& O; y! K; `1 ~# U% B1486086 ALLEGRO_EDITOR ARTWORK          Cannot generate artwork.
1486378 ALLEGRO_EDITOR PARTITION        Unable to delete orphan partition as it is not listed in workflow manager.
3 V, L; i5 E2 t$ @* {( h1487085 CONCEPT_HDL    CONSTRAINT_MGR   Import Physical with the Constraints only option reports problems
1487125 ADW            COMPONENT_BROWSE Results not displayed in the component browser when no mfr parts are associated
. Z* w$ |& E8 m1487265 CONCEPT_HDL    CORE             Replace command in Windows mode shows incorrect behavior
) {% L/ g$ ~, [# `' }1487496 ADW            DATAEXCHANGE     DX Changes checkout ownership when override action is set to remove existing relationships
/ B1 @, W6 W8 i& n1487656 ADW            LIBIMPORT        PreAnalyze reporting false warnings
1487733 CONSTRAINT_MGR OTHER            Running Export Physical - It takes over two hours to update the PCB Editor board
( C3 ]* k2 j/ u1488753 CONCEPT_HDL    CORE             Import sheets in a design with no change in models: CM_VALIDATION_ON_SAVE variable is triggered
1488758 CONCEPT_HDL    CONSTRAINT_MGR   CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager
9 H9 d2 [) }1 b5 ]2 x" b1 }/ X0 ?1490299 SCM            OTHER            ASA does not update revision properly
" h: S: A, l* m% N: L1490744 ALLEGRO_EDITOR SKILL            axlChangeLine2Cline changes line to cline and places it on the TOP layer
( y" |0 ^9 E  E) \! q6 g1490924 F2B            PACKAGERXL       Save Design/Export Physical is resetting Via constraints
# m/ [4 |7 ?( R7 }- w; w. ^6 R2 M1491351 ALLEGRO_EDITOR OTHER            Create Detail for bond fingers on a custom layer not working
1492013 CONCEPT_HDL    CORE             Stale PNN properties not cleared from schematic on packaging design (backannotation)
' U' ^$ O: o) v3 s+ c2 L! u1492595 ALLEGRO_EDITOR MANUFACT         Dimension character substitution help is wrong
1492703 CONCEPT_HDL    OTHER            'Global Property Display' not working for symbol edit
1492777 ORBITIO        ALLEGRO_SIP_IF   OrbitIO import of customer mcm results in crash
$ E, `6 T- b: |+ K1492901 CONCEPT_HDL    CORE             Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL
1494194 CONCEPT_HDL    CORE             Random display of the 'PHYS_NET_NAME' property in hierarchical designs
1497597 ALLEGRO_EDITOR DATABASE         Show Element on pin shows wrong drill size
: h1 `' y0 B# T& h( I' i9 n1497956 CONCEPT_HDL    CORE             ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root
1 F4 l/ K% d; b; `9 r: [/ W3 h1498234 ALLEGRO_EDITOR ARTWORK          PCB Editor fails to create artwork and no error is listed in the log file
1499363 CONCEPT_HDL    CORE             Custom attributes under variant management stopped working in Hotfix60
1500422 ALLEGRO_EDITOR SKILL            SKILL function, axlTriggerSet, results in PCB Editor crashing at launch
1500725 CONSTRAINT_MGR CONCEPT_HDL      Unable to clear pstprop.dat file conflicts
3 L* K+ z% ]. C2 ]1501093 SIP_LAYOUT     OTHER            Package design variant shows wirebonds connected to a die which is not part of the variant
1501165 F2B            DESIGNVARI       TDO does not manage overlay files and variant_roz1040660_1.ba cannot be created unless variant_merged.dat is checked out
/ W8 L% p& N3 J5 s% M( a1501294 ADW            COMPONENT_BROWSE Missing tabs such as graphics, properties and classification properties that were there before the migration
4 D- v% M  l, n/ U/ v# a( @" G. g1501974 F2B            PACKAGERXL       'Feedback has found Illegal pin swap(s)' error although the pin was already swapped and fed back (B2F) to DE-HDL
- W( V8 K; U& E( {1 h4 I1502282 ADW            CONF             What does Message: 3 > 2 means?
9 ]6 ^: I1 B6 G, T1502782 ALLEGRO_EDITOR SCHEM_FTB        Allegro System Architect (SCM) - Export Physical stops unexpectedly without any errors or warnings
* Q. I' e8 V9 J$ [8 \! {3 @4 g1504093 ASI_SI         GUI              View Topology and Waveform buttons overlap when Signal Analysis window is resized
* F5 Y4 v, G* e- P+ U1504767 CONSTRAINT_MGR SCHEM_FTB        Constraint Manager generates errors if the 'sNoF2BFlow' property is added to the Constraint Manager Dictionary
1506110 ALLEGRO_EDITOR DRC_CONSTR       No DRC shown when a text on etch layer is overlapped on mechanical pin
' R( M+ g; S5 I5 d4 y5 t1506654 CONCEPT_HDL    INTERFACE_DESIGN Netgroups broken when moving
1507497 ADW            COMPONENT_BROWSE Switching rows in component browser does not change the graphics of the symbol
1509184 ALLEGRO_EDITOR DATABASE         BB vias in mirror have terminal pads suppressed by artwork
' k1 p1 i1 @6 a: D% i' M1510387 FSP            EXTERNAL_PORTS   Break in extending a net as a deep connection when it is targeted to multiple FPGAs connected in a daisy chain
1510570 ADW            DATABASE         ERROR: Unable to check in block model because the part with instance id used in the model is not available in the databa
1511180 ADW            DBEDITOR         The DBEditor dialog wizard shows an incorrect message about a schematic mode when performing an association of a footpri
( J" [+ L* x, V7 ?1511397 SIP_LAYOUT     TECHFILE         Tech file exported from release 16.5 cannot be reused in SiP Layout in 16.5 or 16.6
1511744 ALLEGRO_EDITOR OTHER            Allegro PCB Editor removes property from component instance
1511761 SIG_INTEGRITY  OTHER            Allegro PCB Editor crashes on running the cns_show command.
$ A- q) J9 z, `9 a% I1511947 ADW            DSN_MIGRATION    Command line arguments of the 'designmigration' command are not working
1513085 CONCEPT_HDL    CORE             NC pins combine with NC_1 and routed as one net in Allegro PCB Editor
1513092 ADW            DBEDITOR         Create Footprint Model name is not working properly if it already exists in the local flatlib
1513737 ADW            CONF             DesignerServer from a different network domain does not show distribution data
1514469 CONCEPT_HDL    CORE             Unable to get rid of an underscore from the PHYS_NET_NAME property
$ Y: I0 L: w5 n; R1514942 SIP_LAYOUT     CROSS_SECTION    Why is AIR not permitted in stackup in 17.0?
1515318 PCB_LIBRARIAN  IMPORT_EXPORT    Import Pin Table: 'CTRL + C' and 'CTRL + V' not working correctly
) @) E9 o* P- g# K  Q/ C8 X# @1517351 CONCEPT_HDL    CORE             Genview does not update an existing split symbol
2 M9 t' O+ _5 h' i1517388 ALLEGRO_EDITOR SHAPE            DRC error reported as PCB Editor fails to read the void for a via
2 g( h& I0 B2 X0 ]) R1518032 CONCEPT_HDL    SECTION          How to get rid of error 'SPCOCN-2009 - Symbol has the SEC property but the required SEC_TYPE property is missing.'
1518724 PCB_LIBRARIAN  PTF_EDITOR       PTF Editor is not saving changes
2 \8 z9 M5 ?, R7 P. a! D( f$ U" ]8 M1519040 ALLEGRO_EDITOR DATABASE         Match groups are lost when a board created in SCM is saved in Allegro PCB Designer.
$ G& k6 _& v( D* w1519518 CONCEPT_HDL    OTHER            Genview does not generate split symbols
1519623 CONCEPT_HDL    CORE             Differential pair added to a NetClass does not display 'NET_PHYSICAL_TYPE' on the canvas
1519910 CONCEPT_HDL    INTERFACE_DESIGN Hotfix 62: Information on manually-remapped port groups is not saved, but reset to default
1519946 CONCEPT_HDL    CORE             Renaming a net leads to loss of constraints associated with the net
1519987 ALLEGRO_EDITOR SCHEM_FTB        In Hotfix 61, constraints are lost on importing a netlist
7 `6 V/ F3 K3 o0 E1520207 CONCEPT_HDL    CORE             Genview crashes after renaming ports
1520727 CONCEPT_HDL    CORE             In Project Manager, the 'Design Sync - Export Physical' command does not automatically update the schematic
1521174 SIP_LAYOUT     DIE_STACK_EDITOR Padstack shapes not converted correctly to die-stack layer using Die-stack Editor
) G: q6 W  V" A1521871 CONSTRAINT_MGR CONCEPT_HDL      CM from DEHDL Allows Creation of Layer Set Name with Illegal Space and No Warning
& ]: y" J  i5 V4 W+ I7 P+ O1522831 APD            OTHER            axlSpreadsheetSetColumnProp with 'AUTO_WIDTH' propName does not autofit the contents.
1522900 ORBITIO        ALLEGRO_SIP_IF   Padstack shape distortion after translation to OrbitIO from SiP design
/ z0 z% B* j3 s  B5 H1523237 ALLEGRO_EDITOR SKILL            SKILL function axlDBGetExtents() causing PCB Editor to crash
1523426 ALLEGRO_EDITOR DRC_CONSTR       Dynamic shape not adjusted based on keepout; DRC generated
/ }. L* |5 ?  c1524875 F2B            PACKAGERXL       Packaging using csnetlister fails, while manual packaging of individual blocks works fine
1525432 CONSTRAINT_MGR OTHER            User-defined property not being transferred from DE-HDL to PCB Editor
1525883 ADW            DATABASE         invoking libimport on an existing DB should verify that the libimp_su variable is set correctly
, s- N' `$ Z8 Q1 k! W  U' M1525948 F2B            PACKAGERXL       Reference designators assigned by the Packager tool are not correct
1526914 ADW            LIBIMPORT        Can not import to new library DB
, }% T7 \/ Z6 u* |4 \" z& m& |% Q1527321 ALLEGRO_EDITOR SCHEM_FTB        Unable to create netlist with the 'Open Board in OrCAD PCB Editor' option in Hotfix 63
1528075 CONCEPT_HDL    OTHER            Auto Generate: DML model assignment fails with error 'There is PHYS_DES_PREFIX property in PTF file.'
8 Y( D% W4 S8 Y* Q# ~% Q* p1528235 ADW            DBEDITOR         About the rule "Validate Classification Property and Property Values" of Release/Pre-Release
1528254 CONSTRAINT_MGR CONCEPT_HDL      Import Logic with the 'Overwrite current constraints' option is deleting some attributes
/ ]9 B- n& c* T: W: d# q% a1528398 ALLEGRO_EDITOR SCHEM_FTB        Problem with pin number format used in NC property
5 M5 w* U" R$ p$ c8 r  d+ N1528479 ADW            LRM              LRM crashes when opened on a lower-level block in a hierarchical design
1528894 ADW            DBEDITOR         Lack of PTF_SUBTYPE in the classification prevents Part's release
& ]. P% b- Y3 T1 U, G& f1529178 SIG_EXPLORER   OTHER            Values not transferred correctly for PinPairs when created ECSET from a net
! `3 J- L9 h$ M( m* Z( v2 S1529209 CONCEPT_HDL    CORE             When adding a component symbol version, the More option does not show all the versions
# U4 d. y7 A8 w$ ]1529720 CONCEPT_HDL    COPY_PROJECT     Running ADW copy project does not update the 'master.tag' file
1530445 ALLEGRO_EDITOR EDIT_ETCH        PCB Editor crashes when 'Add Connect' is used
1530707 CONCEPT_HDL    CORE             Request to recover a 16.6 design after DE-HDL crashes
1531425 CONCEPT_HDL    CORE             DE-HDL crashing while trying to add a NetGroup
0 y3 z9 z( M) ?9 t1532865 CONCEPT_HDL    CHECKPLUS        Provide the ability for Rules Checker to report a GND symbol from the standard, and not our local library, in .mkr
1533543 ADW            DBEDITOR         Component Browser free text search returns 2 parts when only 1 exists
1536273 CONSTRAINT_MGR CONCEPT_HDL      Model-defined differential pair is removed, and Constraint Manager Design Differences does not report an issue
1537055 CONCEPT_HDL    CHECKPLUS        Rules Checker - POWER_PINS value not obtained when schematic instance has the POWER_PINS and POWER_GROUP properties
* ?; N) E* R6 H/ T( B$ _$ a1537339 CONCEPT_HDL    INTERFACE_DESIGN No warning is flagged when moving a Net Group over a net
" Z6 n3 k! A8 ]- T+ [1537521 FLOWS          PROJMGR          Do not allow project creation if there are spaces in directory or file names on the Linux platform
1539077 ALLEGRO_EDITOR SYMBOL           PCB Editor crashes when choosing 'Layout - Renumber Pins'
1539227 CONCEPT_HDL    CORE             Renaming a page from the hierarchy browser crashes the schematic editor.
8 c* W2 P, ]" z8 _  N1539997 ALLEGRO_EDITOR SKILL            PCB Editor crashes when the axlStringRemoveSpaces() command is run
1541532 SCM            SCHGEN           Generate Schematics crashes with 'Out of Memory' error
7 D' T8 x$ D3 G5 N1541680 CONCEPT_HDL    DOC              A dot (.) or period in design name created 2 separate design folders in worklib
* m6 l( R, I, x4 {* E0 k1542817 ALLEGRO_EDITOR DATABASE         Import Netlist not getting completed on specific board
: C0 ]' t' t/ q- j. E: _1542949 ASDA           EXPORT_PCB       Export to PCB Layout Fails to Accept Entered Output Layout File Name
1543537 ASDA           NEW_PROJECT      While creating new projects, the new folder name is not visible clearly in the explorer
1544060 SCM            SCHGEN           Generate Schematics causes Allegro System Architect to crash
1544633 APD            STREAM_IF        The 'stream out' command causes Allegro Package Designer to crash
( R% ]/ m! e) H1544698 ALLEGRO_EDITOR PLACEMENT        'place replicate' does not add clines and vias to fanouts if fanouts are marked
! S3 e& U9 m! k4 p3 r. w1544856 ASDA           CANVAS_EDIT      Edit > Find places the process (UI) behind the SDA tool.
, |7 i2 G) o, E' |1 G5 D: H1545136 ALLEGRO_EDITOR PLACEMENT        All fanouts are marked as part of one symbol instead of the symbols they attached with
1546062 ADW            TDO-SHAREPOINT   Failure to launch TDO Dashboard, need to update error message with more useful information
1549105 APD            OTHER            'Stream out' fails with message: 'Request to terminate detected. Program aborted'
' r/ T- G* i" v" C1549658 ADW            TDA              Unmapped network folder in TDA
1550052 ALLEGRO_EDITOR PLACEMENT        PCB Editor crashes when copying symbols
1551635 CAPTURE        TCL_INTERFACE    GetSelectedPMItems returns error for design cache objects
1553027 ALLEGRO_EDITOR UI_GENERAL       Beta - Allegro display freezing very frequently - canvas not resposive and turns white.
1555246 ADW            DBEDITOR         Part Copy As does not copy AML and reliability model relations.
) X. K: J4 C  g% g  ]3 \( o# |; n1555254 ADW            DBEDITOR         Loose focus on Free Text search Window removes the text.
1557542 ALLEGRO_EDITOR OTHER            DXF export creates strange result for donut-shaped polygon
# G& @- r$ E7 m4 w6 D3 A1573039 ALLEGRO_EDITOR INTERFACES       IDX returns control to the general interface prematurely during an incremental IDX export
1580571 ADW            DBEDITOR         xml files for released FP and padstacks are left in flatlib area.
* G  u* U! C) y& b' {1580580 ADW            LIBDISTRIBUTION  list files are not getting cleaned up for custom models if they are purged.
1582064 ALLEGRO_EDITOR UI_GENERAL       User defined menus not working in 17.2
1582628 ADW            TDA              When one user takes an update of physical object while the other user is still checking in the object, TDO crashes
6 u3 V( C. O8 b$ T2 J4 H1582856 PSPICE         MODELEDITOR      Getting ERROR: [S2C3471] Base part library does not exist when Export to Part Library, though olb created
8 V$ ~5 ^% E0 F5 W) n) `1584719 TDA            CORE             Caching errors coming for a board ref project while doing Block update
  N, S$ D5 d0 B. A- F7 `. H1587045 CAPTURE        IMPORT/EXPORT    Unable to import PDF file
. c- x. D3 `" z6 |7 o. _. d1587259 ALLEGRO_EDITOR UI_GENERAL       axlUIMenuFind not working correctly for the 'bottom' option
1588736 PSPICE         MODELEDITOR      Model Import wizard says "Invalid configuration" when lib opened in Modeled
1588742 PSPICE         PROBE            Browse icon is missing from Pspice File > Export > text
1590006 ALLEGRO_EDITOR UI_GENERAL       PCB Editor 17.2 crashes when multiple browse windows are opened
. E( `( W" e/ q9 a: o0 O1590597 PSPICE         PROBE            Problem with the adaption in the Probe Window icons
7 ?# g8 {  L( ^, t3 v8 f$ R1591264 ALLEGRO_EDITOR UI_GENERAL       Film order in Visibility View sorted alphbetically and does not match with the Manufacturing artwork
5 O& N' F7 f% |9 D: L1592089 PSPICE         MODELEDITOR      Can not get PSpice DMI Model DLL while using PSpice DMI Template Code Generator
, o/ `$ n: V* c1593436 ADW            DBEDITOR         new Model type form does not focus cursor in window, User must select the Model Name before any text shows up
1594076 TDA            CORE             TDO is crashing on concurrent checkin when one of the user got blocks which are not modified
1595987 ALLEGRO_EDITOR PLACEMENT        Subclasses not getting updated in Placement Edit mode
1596162 ASDA           IMPORT_DEHDL_SHE Importing sch pages from DEHDL imports the block as well
% Q' q; D; Y3 _1597000 CONCEPT_HDL    INTERFACE_DESIGN Renaming NG does not work if >1 segments have NG names
1 f' g! z4 X9 [* F: a1597406 ALLEGRO_EDITOR SHAPE            Dynamic Shape does not void the traces and voids open areas
1597957 ALLEGRO_EDITOR PLACEMENT        Quickplace: placed and unplaced counts not getting updated
* F! C+ s7 E8 E$ Y( S1600194 ALLEGRO_EDITOR DRC_CONSTR       Update drc command changes the amount of DRC count when using 8 threads
0 p& H4 u/ u, d; ]1600800 ALLEGRO_EDITOR GRAPHICS         LINUX 17.2 operation of Update DRC is not the same as Windows – graphics not updating
1602605 CONSTRAINT_MGR OTHER            OrCAD: constraints not getting saved
' @$ Y6 d1 @" Z3 \( c1602801 SIG_INTEGRITY  OTHER            Dielectric Warning message when opening SiP tool.
1603377 PSPICE         ENVIRONMENT      At Markers Only option does not generate .dat file
1604166 CONSTRAINT_MGR CONCEPT_HDL      Audit ECSets does not work from 'Referenced Electrical CSet' column header
1604741 ASDA           CANVAS_EDIT      tcl console changes the present working directory (pwd) when you open the proj preferences & close it.
1605310 TDA            CORE             TDA is crashing sometimes in the Join Project wizard
1606861 CONCEPT_HDL    CORE             Crash on Linux during Generate View
1606917 CONSTRAINT_MGR CONCEPT_HDL      Importing tech file in DE-HDL Constraint Manager is creating a duplicate 'DEFAULT' cset
1607157 ALLEGRO_EDITOR INTERACTIV       Edit - Change allows lines to be copied to Cutout subclass, but that subclass requires closed polygons
( X! N- H. C& t6 {5 n1607330 CONCEPT_HDL    CORE             Variant view schematic PDF corrupted with attach_props set
6 M8 O: `/ E# b; K: `1 x7 j) o0 S1607568 ALLEGRO_EDITOR NC               Allegro shows wrong drill legend Top to Top drill.
. e, \/ z$ D& K; H& U: q1607986 CONCEPT_HDL    SKILL            cnGetSetupProjFilePath skill command in SPB 17.2
8 h3 n8 [+ ^) E% [3 \1608524 SIP_LAYOUT     MANUFACTURING    The Display Pin Text tool fails in the 16.6.073 version with a parseString error.
; m7 f$ P) L. ^' J, W1609400 ASDA           CANVAS_EDIT      RMB > Assign Differential Pair should be grayed out when a single net is selected
1 V" a' D/ |3 O4 H5 S! T& u1609809 ALLEGRO_EDITOR UI_GENERAL       Crash in Allegro PCB Designer version 17.2-2016 on Linux
1609856 ALLEGRO_EDITOR ARTWORK          Embedded paste and soldermask showing up in both top and bottom gerber files.
, C! H& J7 e; I8 N0 ]8 m1609922 CONCEPT_HDL    INFRA            Launching Model Assignment crashes DE-HDL when the temp/edbDump.txt is read-only
1611226 ALLEGRO_EDITOR SYMBOL           Allegro shows crash message while saving flash symbol.
1612108 ALLEGRO_EDITOR OTHER            Netlist Import is crashing with the .SAV message.
1613123 ALLEGRO_EDITOR SKILL            drillType Attribute in Skill for Ovel Drill return OVAL SLOT in place of OVAL_SLOT
1614000 ADW            LIBDISTRIBUTION  lib_dist does not complete and does not allow to delete the .lck file.
1614667 SIG_INTEGRITY  SIMULATION       Different results from Probe in SI Base and SigXp
, d/ V( X3 C' x3 `8 L& @1615601 GRE            IFP_INTERACTIVE  Delete Bundle then try to delete plan lines results in fatal error
1616235 ORBITIO        ALLEGRO_SIP_IF   oio2sip import doesn't map layers correctly
1616540 SIP_LAYOUT     DRC_CONSTRAINTS  Same net DRC Line-to-Line reappearing after dyn shape update
1616733 ALLEGRO_EDITOR INTERFACES       Genrad output no longer working in 17.2. Gives Error: extracta process failed. Command terminated
1618751 ASDA           DRC              SDA is showing Zero node Net errors when we run DRC checks, but user had RETAIN_ZERONODE_NET 'NO' in Site CPM file.
1618797 ADW            FLOW_MGR         Flowmgr fails to execute command
1618930 CONSTRAINT_MGR INTERACTIV       Hovering over row column cell causes the application to go into a not responding state.
1620350 ASDA           EDIT_OPERATIONS  Uupdating version for a connector pin looses the pin number
1621963 ASDA           SELECTION_FILTER When working in SDA, I am able to select "Pins" on all parts except connection pin symbol.
0 ~9 S. q2 `& R" ?! j% \1 r1622715 CONCEPT_HDL    CONSTRAINT_MGR   Extracting a XNet crashes the tool
) y! S3 p% B: W1625209 ASDA           IMPORT_PCB       File Import from Allegro shows board differences
- G, Y* a# N) E9 ]- c9 ^' x& t. z$ PDATE: 07-28-2016   HOTFIX VERSION: 003
===================================================================================================================================
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
===================================================================================================================================
1423889 ALLEGRO_EDITOR EDIT_ETCH        AiDT gets poor routing result
! z( A2 G% ]# S! S  P" {2 Q7 d1461626 CONCEPT_HDL    CREFER           CREFER shown to each instance of block pin though net changes
1472456 CONCEPT_HDL    CORE             XCON and design are out of sync
1546151 CONCEPT_HDL    CORE             Add port, Genview, move pin on block - the pin name disappears
1547356 ALLEGRO_EDITOR EDIT_ETCH        Results variations from ISR S034 to S066
1560102 ADW            FLOW_MGR         172BETA: eval in command string does not work
( A  W/ r$ B' C4 e: \& \! Y$ d1570032 ALLEGRO_EDITOR GRAPHICS         Issue with 3D View
& S/ C) T9 O7 D0 ]  u( d1574676 ORBITIO        ALLEGRO_SIP_IF   sip->oio eco doesn't work properly
9 |: Y& J9 O* n. C" k) X) |  P1578876 ADW            ADWSERVER        Component Browser crashes when trying to show details on a part number
( \& D; f- a5 N) D# q$ q- C1580744 F2B            PACKAGERXL       ERROR(SPCODD-114): Duplicate physical part name NETSHORT found
1582863 CONCEPT_HDL    CORE             Generate View creates non existent ports
% @- \6 f3 i! L1584317 CONCEPT_HDL    CORE             When  packager fails, no option to open pxl.log file from design sync window.
1587018 ADW            FLOW_MGR         Project Update at Ericsson in ADW 17.2 asks to specify flow name.
1587157 CONCEPT_HDL    CONSTRAINT_MGR   pstprop.net reports conflicts on nets with VOLTAGE properties
1587498 CONCEPT_HDL    INTERFACE_DESIGN Possibility to tap bus bits removed
0 b  q: I, X0 P3 o1 r) @+ |/ C1587718 ADW            LIBIMPORT        Library Import Pre-analyze report is not being written
1588197 ALLEGRO_EDITOR INTERFACES       STEP output fails when External copper selected on Win10-17.2
  c2 A! Q7 ^- u8 g/ V1588786 ALLEGRO_EDITOR OTHER            strip_design reports "Design corrupted message"
1589252 CONCEPT_HDL    CORE             Search options go to page origo not chosen component
1589318 ALLEGRO_EDITOR DRC_CONSTR       Via to SMD Fit DRC between Embedded pin and via which do not share layers
# m0 T% K+ u. G& l# M+ }1589979 ADW            FLOW_MGR         Design Name change in EDM 17.2 doesn’t reflect in flow manager in same session of project
7 p4 A, E! g$ L1590538 CONCEPT_HDL    DOC              Open Archive shows unclear behavior
: a! C' D( u" _- o' U3 w1590639 CONCEPT_HDL    OTHER            DEHDL crash when importing design
1590651 CONCEPT_HDL    INTERFACE_DESIGN DEHDL duplicate NetGroups created in Interface Browser and CM
) ?& [& G3 H' u  H" Z1590720 ALLEGRO_EDITOR INTERFACES       Text Size Parameter file does load names into the text table
. g5 V6 B+ N' O* P* f1591070 PSPICE         PROBE            PSpice crash while evaluating measurement from trace>measurements
$ d% R7 Q  V* K; x. f) B1591223 CONCEPT_HDL    CORE             Variant information does not display on lower level schematic
1594240 CONCEPT_HDL    ARCHIVER         Archiver is not able to change the permissions of the cells archived
) R; X# P$ \3 t3 y3 ~, _' p( I1594416 ALLEGRO_EDITOR PAD_EDITOR       Padstack Editor crash in 17.2
1596615 ADW            DBEDITOR         Component Browser didnt come up to search parts, also the database editor didnt return search results
1596780 ALLEGRO_EDITOR SKILL            PCB Editor crashes after doing SRM update and save
2 S0 P+ }. t; B. R) d' ~( A: x" b1597153 F2B            DESIGNVARI       ERROR SPCODD-53 in Variant Editor
1597385 F2B            DESIGNVARI       Some 16.5 variant DNI parts are now appearing in 16.6 as X-OUT and some don't have X-OUT or DNI
1598629 F2B            PACKAGERXL       Export Physical crashes
" x: B7 W/ [! ^! K5 a6 `; p! E6 G1599452 ALLEGRO_EDITOR ARTWORK          Import Artwork, Mirror option does import pins or shapes.
$ o# r: Z) s2 ~' J! n1 K  s1599744 ADW            FLOW_MGR         Few flow manager buttons are not working in EDM 17.2
1599950 SCM            OTHER            Adding the GND net to parts/pins takes a long time.
' I5 G7 O) y! K1600226 RF_PCB         AUTO_PLACE       Fail to auto-place RF group
7 W9 L- p. B/ ?2 `& b1600618 ALLEGRO_EDITOR DRC_CONSTR       case sensitive issue with Physical Constraint Set
5 g% M  v& B9 @1 T6 m9 Y7 f- o0 |1600914 ALLEGRO_EDITOR INTERFACES       File > Export > PDF shows the shape as unfilled.
- Q/ v4 \& F, \- e1601165 ALLEGRO_EDITOR DATABASE         Thermal Relief is not added for Rounded Rectangle pad
1601281 ALLEGRO_EDITOR OTHER            STEP model link gets corrupted with SKILL axlLoadSymbol
: |/ c# d, M9 y: D( \1601282 ALLEGRO_EDITOR OTHER            Export Libraries will not export device files when there is a space in the folder name.
1602514 PCB_LIBRARIAN  METADATA         References to some primitives is missing in block metadata causing TDA errors for missing parts after join project
1602823 SIP_LAYOUT     WIREBOND         SiP Crashed during Add Wire command
1602955 ALLEGRO_EDITOR SHAPE            Shape no DRC when there is a Route Keepout in base layer.
1604223 CONCEPT_HDL    CORE             ERROR: SPCOCD-553: Connectivity Server Error
1604746 ALLEGRO_EDITOR OTHER            In 17.2, there is a discrepancy in layer data when importing extracta files into their Mentor Graphics extraction tools.
+ U& l* e2 B  d' R6 i% H9 z" I1605322 ALLEGRO_EDITOR TECHFILE         Cadence SPB17.2 Issue - Long duration in Tech File generation
DATE: 06-31-2016   HOTFIX VERSION: 002
===================================================================================================================================
1 L: k$ [1 e% b$ TCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
===================================================================================================================================
# E/ H# ~7 O# ^6 y% z1452838 CONCEPT_HDL    CORE             Apparent discrepancy between Bus names and other nets
2 N( x/ X: m4 \, n7 J* [1469146 ADW            LRM              ERROR(SPCODD-5): Pin '1<1>' on the following primitive instance cannot be packaged in package
1481802 ORBITIO        ALLEGRO_SIP_IF   import of oio to an existing sip offsets the results incorrectly
1518957 APD            SHAPE            Shape void result incorrect
  Z8 q& t3 t# }3 H1519155 ALLEGRO_EDITOR OTHER            IPC-2581-B Negative Plane Error
8 X5 w" O2 }4 \1 d1524947 SIG_INTEGRITY  SIGNOISE         SI Base, PCB SI: Custom Stimulus is not recognized correctly
3 b4 f" H. ]$ r- U$ _( f' G1532162 CONCEPT_HDL    CORE             The Rename Signal command does not update split symbols.
1543997 CONSTRAINT_MGR OTHER            Import Logic is overwriting the constraints in attached design.
' k: x, R% j1 ]. |( d1544675 ALLEGRO_EDITOR OTHER            Export libraries corrupts symbols if paths do not include the current directory (.)
1549097 CONSTRAINT_MGR XNET_DIFFPAIR    Need to warn users creating differential pair(s) in the Physical Tab with nets that have voltage properties set
1551934 ALLEGRO_EDITOR SKILL            axlBackDrill command is not analyzing new layer set when application mode is set to 'None'
1554919 ADW            LRM              LRM does not find PTF data for cell 'res' in the reference library
1555009 CONCEPT_HDL    INTERFACE_DESIGN Not possible to rename NG
$ z5 f; t/ \% X1559136 ALLEGRO_EDITOR EDIT_ETCH        Cannot connect floating clines to vias with nets
/ `, \! C' ^, `% h1559552 SIP_LAYOUT     ORBITIO_IF       device offset in oio2sip translation
8 i. |- I" s8 @1 d( ]. N; B1560301 CONCEPT_HDL    CORE             DE-HDL hangs when Edit menu commands are called on Linux if xclip is open
' {+ Z/ Q  f# i0 k1560804 ALLEGRO_EDITOR OTHER            Film records order gets reversed when using File - Import - Parameters after File - Export - Parameters
1 a0 f( {" h' Z1561501 ORBITIO        OTHER            oio -> SiP refresh seems to hang
2 u* k; Y, G! c0 a1 z: _) _* i. p1564036 CONCEPT_HDL    CORE             User-defined custom variables are not getting populated in the TOC
1564545 CONCEPT_HDL    OTHER            Signal model property deleted from an instance is not deleted from the instance pins
1564552 CONCEPT_HDL    CORE             Find Net should zoom to the nets on schematic canvas
1566119 CONCEPT_HDL    CORE             Right-clicking the schematic to add a component does not show all the schematic symbol versions
% M1 |* n6 ?" u* Z! s9 `( B1566848 ALLEGRO_EDITOR ARTWORK          Board Outline artwork is incomplete
: p$ R  {$ J- l& d+ J1566942 ASDA           MISCELLANEOUS    SDA172: A lot of files in /tmp/ on Linux
  S% r- N& B1 d# V1567290 ALLEGRO_EDITOR MANUFACT         Import Artwork fails to import a shape.
1567587 ALLEGRO_EDITOR MANUFACT         Extended tool name in header of drill file is not correct
1569056 CONCEPT_HDL    CORE             Opening New Cascaded Window Causes Graphics Artifacts on Old Window
1569087 ALLEGRO_EDITOR DRC_CONSTR       Running DRC Update gives the message  'Figure outside of drawing extents. Cannot continue.'
- v  q7 B& }2 G  c( q1569147 CONCEPT_HDL    CORE             Signal Name AutoComplete Drop Down List Not Correctly Displayed
1569394 ALLEGRO_EDITOR SKILL            axlPadSuppressSet( 'on 1 '(via)) not working on SPB17.2
1569924 CONCEPT_HDL    CHECKPLUS        ERROR (body_to_physical_check) - Pin name(s) not found in package : PEX_REFCLK0_N* PEX_REFCLK1_N*...
1570398 SIP_LAYOUT     DATABASE         Diestack layers can't be deleted if there are unplaced symbols in the design
' R. |: g% `/ [1570419 CONSTRAINT_MGR CONCEPT_HDL      How do I add a customized worksheet custom property weblink in Constraint Manager
# w1 {3 C3 l5 W/ S8 {1570624 APD            ARTWORK          Artwork file has missing voids on a layer and is causing a short
* S9 \! Q! q3 a1570678 F2B            DESIGNVARI       Variant Editor error when adding an RSTATE property
8 Q$ Y! R% Z" G/ v" Y; k  e4 B1571113 CONSTRAINT_MGR DATABASE         Reports generated from cmDiffUtility show the differences in mm units only
1572593 ALLEGRO_EDITOR ARTWORK          ARTWORK: 'Draw holes only' option does not match display
! R$ Y  b& R, A. m: G$ R1573127 CONCEPT_HDL    COPY_PROJECT     copyproject creates incorrect view_pcb entry
9 J3 u6 d: }: n, X" l1573205 CONCEPT_HDL    CORE             dsreportgen is unable to resolve the physical net names (PHYSNET)
1573625 CAPTURE        PROJECT_MANAGER  Toolbar customization is reset when Capture is re-invoked in SPB 17.2
1573755 ALLEGRO_EDITOR CROSS_SECTION    Switching between plane and conductor changes material in Cross Section.
1573970 CONCEPT_HDL    ARCHIVER         archcore fails to archive the <project CPM>.arch file
) G. g$ _* P3 ]" C( Q# s1574381 CONCEPT_HDL    OTHER            Packager crashes with some advanced settings
% J- g1 _* P3 G" Q, E1576100 ALLEGRO_EDITOR SYMBOL           Update symbol crashes, creates '.sav' file, but shows update was successful in 'refresh.log'
1577381 CONCEPT_HDL    CORE             ERROR(SPCOCN-2128): The NetGroup structure does not match the PortGroup structure
6 u6 X- o' i% w$ u1 i) h% l5 a1580103 ALLEGRO_EDITOR DATABASE         dbstat of 16.6 does not recognize 17.X files
1580891 SCM            REPORTS          Dsreportgen crashes on different scenarios
1581254 SIP_LAYOUT     CROSS_SECTION    "Apply" or "Ok" crashes XSection
  r/ ]5 _4 ?$ g3 j/ ~7 u1584957 ADW            FLOW_MGR         17.2 Flow Manager, JavaScript - Tool Launch Error
, w) y4 l0 {' v9 Q( O! V$ a1588823 ADW            FLOW_MGR         UNC paths have stopped working in Flowmanager in 17.2
1590064 ADW            LRM              EDM 17.2 gives LRM unnecessarily.
DATE: 05-06-2016   HOTFIX VERSION: 001
===================================================================================================================================
$ l; L, h' R1 ~% p1 WCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
===================================================================================================================================
1272355 F2B            DESIGNVARI       Property changes on replaced component shows incorrect result in BOM output
7 r3 a( y1 [# i' Z8 }. @) w3 B1482953 ALLEGRO_EDITOR DATABASE         Part change disassociates parts from Group
6 R& K3 D0 Q) B1 E, l1 d) m1484075 ALLEGRO_EDITOR PADS_IN          'pads_in' imports ASSEMBLY_TOP  and PLACE_BOUND_TOP outlines that are defined as shapes as lines
1488909 ALLEGRO_EDITOR DRC_CONSTR       Test Via causes net scheduling verification to fail
  q& g: B8 O9 U: c1498389 SIP_LAYOUT     DIE_GENERATOR    Provide the ability in the 'die in' command to specify flip chip as a DIE symbol
1499515 ADW            COMPONENT_BROWSE The Search Criteria property value is automatically being set in the ADW Component Browser
1506672 ALLEGRO_EDITOR INTERACTIV       Replicate Place - Shapes are missing
6 ~6 T) N0 Z, Q4 H) v1522411 FLOWS          PROJMGR          License selection should persist on invoking Layout from Project Manager
9 [. L$ r, G5 b% Q2 D1523532 F2B            PACKAGERXL       Adding subdesign names in the "Use subdesign” or “Force subdesign" sections hangs for more than a minute
1525783 CONCEPT_HDL    CORE             \BASE scope does not work for SYNONYMed global signals
6 L: c9 }- j$ D5 S2 G" V1526729 SPIF           OTHER            Exporting a dsn file causes PCB Editor to crash - in the interactive and batch modes
1529846 ALLEGRO_EDITOR SHAPE            Some shapes are not generated in the artwork
* v/ z7 L: ?0 |" y1537499 CONCEPT_HDL    CORE             Adding the same version (already placed) with the same split block name should not be allowed
' u5 C$ [# [4 H' g- F' `1541589 ALLEGRO_EDITOR INTERFACES       STEP model incorrectly shown in 3D viewer. Shows pins as angled.
1542334 CONCEPT_HDL    CREFER           creferhdl leaving lock files in sch_1 folder
1542722 ALLEGRO_EDITOR INTERFACES       IDX export: RefDes and PART_NUMBER missing for mechanical symbols
& Q' l6 k8 x: q( ]2 H1543410 ADW            LRM              LRM shows confusing pat status. It reports that update is needed but clicking update doesn't work
2 X' v% h% Y* s3 I9 @1544614 ALLEGRO_EDITOR SKILL            Associative dimension data reaches the 'psm' file despite deleting the layer on which it was set in the 'dra' file
5 I0 d* l6 L, @5 q: k1545370 APD            OTHER            Pads in .mdd file getting placed on different layers as compared to the design
+ R7 U6 t! s- K+ J8 X1545909 ALLEGRO_EDITOR UI_FORMS         Show 'microvia' checkbox in 'Blind/Buried Vias' form only with the 'Allegro_PCB_Mini' license
. P5 Y# |2 ]* }4 k% Z1546141 ALLEGRO_EDITOR SHAPE            Shapes missing from Artwork
  |5 }9 d: ]) x& o& C$ U# j. ?1546877 CONCEPT_HDL    CORE             Align Left on Wires Fails With Incorrect Error Message
; t. G4 X- d( _" F% v1547224 CONCEPT_HDL    CORE             Lock the 'PATH' property once it is assigned by system
1547584 SIP_LAYOUT     OTHER            SiP - Design Variant - delete embedded layer if not selected.
1548116 CONCEPT_HDL    CORE             Some versions of Technology Independent Library do not appear when adding a symbol
1548151 ALLEGRO_EDITOR INTERFACES       Exporting a step file gives a component rotation mismatch in the *.stp file
' [1 M( z4 t) n8 S: Y1548421 F2B            BOM              Parts with same 'BOM_IGNORE' set do not behave the same way in the BOM report
1548978 ALLEGRO_EDITOR MANUFACT         Shape not voiding clines
1549662 ALLEGRO_EDITOR OTHER            Import Parameters Path' fails if parampath does not have the current directory ('.') set
6 g) r4 N  J* O7 H: E7 R1549836 CONCEPT_HDL    CORE             Tools -> Customize -> Keys -> Reset does not actually reset keyboard shortcuts
3 l4 W5 T. p3 @6 C2 M1550941 PCB_LIBRARIAN  PTF_EDITOR       PDV Part Table Editor new column sorting causing problems
1551713 ALLEGRO_EDITOR DRC_CONSTR       Hole to hole drc between Via and pin
1553950 ALLEGRO_EDITOR SKILL            Executing axlUIControl('pixel2UserUnits) crashes Allegro
1554333 CONCEPT_HDL    CORE             Changed connectivity error when aligning ports attached to netgroups
# E. i6 H  B, U+ R. ]1 s: R8 K9 |1555092 SIP_LAYOUT     DEGASSING        Degass offset is not working with hexagons
1556261 ALLEGRO_EDITOR DATABASE         Running DBDoctor on board file gives an error"Illegal database pointer encountered, Exiting DBDOCTOR." and crashes
1557716 APD            OTHER            Stream out fails with request to terminate detected - Program aborted
8 v$ X4 A5 J# G1559951 SIP_LAYOUT     SYMB_EDIT_APPMOD Wrong bump locations after Symbol Editor -> Refresh co-design die
1560197 CONCEPT_HDL    CORE             bomhdl adds extra charcters to subdesign_suffix when generating hierarchical BOM
; B- [6 ]/ F5 C4 t3 H1561077 ALLEGRO_EDITOR INTERFACES       Beta - IDX User Layer export fails on Linux
1562537 ALLEGRO_EDITOR MENTOR           Mentor BS to Allegro 16.6 results in Fatal Error
$ ?" g6 s4 m/ j+ [) j$ E1564203 ALLEGRO_EDITOR ARTWORK          ARTWORK : Can't generate negative film.
3 o! L$ w0 w6 m9 a. s2 @+ I
$ j" B$ |4 l, u

longzhiming99

steven.ning 发表于 2016-9-9 21:38
还是没有可以降到16.6版本的消息。17.2不真心不敢用。

已用17.0一年多，一条路走到底，没有回头路……
7 Y% v+ _% }  G: K9 g$ D6 C

longzhiming99

  Mentor BS to Allegro 16.6 results in Fatal Error 这行什么意思，跟16.6有什么关系？

每天学一点

好多年前学会建封装后就一直没时间画板练手，现在还一直用PADS

金志峰

:)

金志峰

:(:(:(:(

Csec

有没有下载链接？

nanlvge1982

都用17.2了？

d0211

感謝說明相關 hotfix 內容

haoyingxiang

好厉害
7 \  Z5 Y% ]: A! P' k: M

zxpchx

patch不到"死",不算数.

muller1981

大感謝!
Hotfix 一定要來更新與修正的
; ~2 N, u9 L" E1 ]% W  c感謝您~

hua_wind

    谢谢楼主

Ivanzhang

谢谢楼主提供更新内容

steven.ning

还是没有可以降到16.6版本的消息。17.2不真心不敢用。

minidust

可惜没有链接啊