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17.2 hotfix001-004更新点

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发表于 2016-9-7 01:03 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式

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DATE: 08-14-2016   HOTFIX VERSION: 004
% p, ?' E; @" S6 Z0 `: i  L" h===================================================================================================================================
8 P" Z, {* {0 Q- a& q! e( A; fCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
( L8 f# r( F( ^2 o) y- K===================================================================================================================================
& |$ j) u8 v# s: }% Y9 J908816  CAPTURE        SCHEMATIC_EDITOR Few graphical operations are active even when a page has been locked
2 J, o3 p* z  }0 O6 n1213923 ADW            LIBIMPORT        Cannot delete parts in the Library Import project (XML)3 ]- R3 \3 _1 c- p8 M  l8 i
1250476 PCB_LIBRARIAN  LIBUTIL          con2con does not check for PACK_TYPE
1 l8 q7 R+ O9 G/ \( R# A8 F+ ~1306441 APD            OTHER            The Minimum Shape Area option in Layer Compare uses an unspecified value
8 ~# E+ h  v+ h7 _1 s$ a1322242 ALLEGRO_EDITOR INTERFACE_DESIGN Using add connect together with replace etch Option is causing the tool to slow down for certain constraint nets8 f" p: U  B9 n0 k; w- q0 T
1326716 ADW            DOCUMENTATION    Dataexchange documentation correction needed
; T' C, d# V5 p2 m# [. @1356948 APD            DEGASSING        When using the Degassing tool on shapes the size of the file becomes very large
3 Y+ Y- \1 E2 x3 M; y" z# k, b1376510 ADW            DBEDITOR         DX output ERROR after Property Display Ordering of Part Classification.
1 d/ v& a4 e/ E' W1408218 ALLEGRO_EDITOR MANUFACT         Specifying the Offset value results in unexpected value of the NC Route coordinates in the .rou file. V# l' L* P* m4 r8 D: _5 ~' [- L
1410485 CAPTURE        SCHEMATIC_EDITOR W shortcut and Autowire active on Locked design
* P+ ~0 A- s4 s# ?4 o' o1413248 CONCEPT_HDL    CORE             Import from another TDO project makes the block read-only1 G% R; S' |8 B+ p- e# l
1413287 ADW            LIBIMPORT        Library Import uppercases all Attributes when reading CSV! z* d4 B7 M9 p- [  R8 a8 t
1417429 ALLEGRO_EDITOR INTERACTIV       Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle
/ b. z3 g6 U3 d1417442 ALLEGRO_EDITOR INTERACTIV       Spin via stack and only part of the stack spins
) c) r, o6 U- y+ y1430251 ALLEGRO_EDITOR PLACEMENT        Quickplace placing symbols outside of a polygon shaped room/ @: G* O; p1 P3 q
1440509 ALLEGRO_EDITOR PLOTTING         Ratsnest do not follow the refdes position when plotting the BOTTOM layer with the 'Mirror' option
/ y- f+ V1 B* z: ~$ t! R1441086 PCB_LIBRARIAN  OTHER            Changes made to a package with sizable pins generated from the sym1 view are not saved6 t6 D# R6 ?/ x3 p+ H4 B
1443339 PCB_LIBRARIAN  PTF_EDITOR       ALT_SYMBOLS syntax in PTF file not checked
# c! q( @. v' ]4 F5 @1 p1444144 ALLEGRO_EDITOR DRC_CONSTR       The 'add taper' command generates line to line spacing DRC
6 x) |0 z$ N6 N8 a9 d  k* O: q1451766 CONCEPT_HDL    COMP_BROWSER     License error message should indicate which license is required
  H- K' R' ?0 n  Z$ I& Y1451977 CONCEPT_HDL    PDF              Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set( p# U# ~$ d8 K: E9 x& b
1457138 CONCEPT_HDL    CONSTRAINT_MGR   devices.dml: difference in content generated by _automodel add command and Constraint Manager launch6 }, ^1 X5 R9 P8 r+ X# _; S$ Y
1458439 F2B            PACKAGERXL       The Packager pstprop.dat file reports false conflicts in net properties' c5 z, ^; i- a
1464865 CONSTRAINT_MGR ANALYSIS         For identical nets, topology in DE-HDL CM is different from the topology in PCB Editor CM+ f' q% x8 C8 t- Y( D' A; Q0 p
1464948 PCB_LIBRARIAN  VERIFICATION     The errors/warnings do not match between the various tools% i% U7 }' I' o/ V) `
1467826 CONCEPT_HDL    PDF              PublishPDF from Console Window creates a long PDF filename; e# b2 r3 g& V8 q  S/ v
1470106 ALLEGRO_EDITOR MANUFACT         silkscreen program cuts auto-silkscreen lines excessively4 O$ \8 `9 i" b
1471287 CONCEPT_HDL    CONSTRAINT_MGR   Importing pages from other designs with different units should inherit the source constraint units& D/ W! T. @4 t
1472046 ALLEGRO_EDITOR OTHER            Gloss routine, 'Via Eliminate' - 'Eliminate Unused Stacked Vias' is not removing unused microvias from the stack
0 P3 Y9 ~& a  n. O1 z3 @1472414 ALLEGRO_EDITOR SCHEM_FTB        netrev changes pin-shape spacing rule in constraint region
% Z# c5 c$ ^  o- T7 O9 b. p( [) @1472444 ADW            ADWSERVER        Multiple errors in adwserver.out after SPB 054 / ADW 47; H  ]) [6 q% {. P6 B3 a. N
1473056 ALLEGRO_EDITOR ARTWORK          Gerber export has additional phantom data not on design; _4 n4 s8 T- x! d$ I6 Z
1473900 CONCEPT_HDL    CORE             DE-HDL stops responding when a hierarchical block with variants defined inside the reuse block is enabled+ N. B9 O) e8 S+ V
1474020 ADW            DBEDITOR         Unable to modify schematic classification when a part is checked out previously by another librarian+ n7 W7 ?, Y2 [  }6 B9 L
1474066 ADW            DBEDITOR         Bulk edit performance lags when parts included have large number of properties  M3 {. ]3 l# s6 n/ L* T% t
1474764 ALLEGRO_EDITOR PLACEMENT        In Hotfix 56, the 'place replicate create' command does not produce desired results if a fanout is marked
9 f6 ?. F! ]$ g( Z/ Z' o1474894 ALLEGRO_EDITOR PLACEMENT        Place replicate fails to include vias when the module is applied to other circuits.
+ w8 u, _" j+ V1475650 ALLEGRO_EDITOR OTHER            Using Outlines - Room Outline gives WARNING (axlRemoveNet): No match for subclass name - 'BOARD GEOMETRY/__EPB_SCRATCH_'1 h0 L# J( n! `% Y9 X9 v# B
1476528 ORBITIO        ALLEGRO_SIP_IF   While translating a .mcm to OrbitIO, the error 'allegro2orbit.exe has stopped working' is thrown& `; l7 m& b5 M. Z
1476920 CONCEPT_HDL    OTHER            Genview consistently fails in some indeterminant manner.
* F5 G+ S5 ?: l5 `0 z- A1477369 CONCEPT_HDL    INTERFACE_DESIGN A significant number of problems are reported when running genview with port groups
) X/ o; c- o: ^' W# [: i" }1478111 F2B            DESIGNVARI       Hierarchical block variant not shown in testcase with S57 although it was working with 2015 release
" b' A$ n; Q' ^( n" t4 m1478200 GRE            IFP_INTERACTIVE  Allegro give error "Low On Availlable Menory" and then crash0 Q! I; B$ ]3 V" y& T
1478680 CONCEPT_HDL    CORE             Unable to move components in a schematic using the arrow keys
0 c: i  K7 [# [& a0 g1 ]1479135 F2B            PACKAGERXL       Hierarchical design reports conflicts when signal names change through the hierarchy" y  _& }  U' J
1479153 CONCEPT_HDL    CORE             File - Save Hierarchy flags an error and does not update subdesign xcon& x8 y, A0 S1 x" [
1479227 CONCEPT_HDL    CHECKPLUS        Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy* L8 @4 c& ~$ D+ B1 u/ e8 Q: K
1479454 CONCEPT_HDL    OTHER            DE-HDL issue: locked DIFF_PAIR property is editable
, ^. |* z- [6 d2 s1479569 PCB_LIBRARIAN  OTHER            hlibftb fails with error SPCOPK-10538 ~9 H8 U9 `0 s- A- W$ K0 ^
1479785 ORBITIO        ALLEGRO_SIP_IF   brd file does not get loaded in OrbitIO& \4 k# J5 z" ^4 o; g' _
1480005 ADW            DBEDITOR         DBEditor/DBAdmin GUI do not allow the same characters in Property  as LibImport CSV Files
% Y4 f6 o6 T- `% ]$ g+ P# U5 E9 s1 Y1480367 SIG_INTEGRITY  OTHER            Differential pair extraction SKILL error, 'parseString: argument #1 should be either a string or a symbol'
2 Q# C& o5 u; p' T' d$ p1480499 ALLEGRO_EDITOR PARTITION        Cannot delete partition4 H7 G% V0 {, ~  J, y
1482544 ADW            DBADMIN          Hierarchical PPL not functioning correctly
2 \/ f0 o4 R' g% B, @+ g1483136 ADW            COMPONENT_BROWSE About searching the parenthesis or comma in Component Browser of ADW Mode
6 r; {8 Y) f3 U1483617 ALLEGRO_EDITOR DATABASE         Delete islands command crashes database with filled rectangles
8 W) P# b5 j6 f! F( ^" T. h1 F1484100 SIP_LAYOUT     INTERACTIVE      Tool crashes when copying and rotating a symbol
; W' g4 ^- f! `" ~/ E" g, t1484781 CONCEPT_HDL    CORE             Three different Hierarchical Viewer issues# W) O7 W8 W' ~* |. D; R* q
1485059 PCB_LIBRARIAN  CORE             Part Developer pin attributes are randomly marked as read-only- U7 B8 p! z1 O* _0 n
1485931 ALLEGRO_EDITOR INTERFACES       Errors generated when importing IDF in an existing board file
( s7 t7 i" m  x+ v, |1485960 CONCEPT_HDL    CHECKPLUS        Custom DE-HDL Rules Checker rule is crashing the project6 F+ X% h3 e; l( O* x
1486086 ALLEGRO_EDITOR ARTWORK          Cannot generate artwork.
# E4 S7 G$ n& W5 L- }4 x2 b: O1 g1486378 ALLEGRO_EDITOR PARTITION        Unable to delete orphan partition as it is not listed in workflow manager.
: t3 T  b; E; J9 c8 }5 h, S+ V& m1487085 CONCEPT_HDL    CONSTRAINT_MGR   Import Physical with the Constraints only option reports problems$ U; A) N7 X6 U* E/ O8 g! \
1487125 ADW            COMPONENT_BROWSE Results not displayed in the component browser when no mfr parts are associated" E% S  V( @) X+ n% ?" L
1487265 CONCEPT_HDL    CORE             Replace command in Windows mode shows incorrect behavior
3 `+ r* p& v, R; K; T' k1487496 ADW            DATAEXCHANGE     DX Changes checkout ownership when override action is set to remove existing relationships- d. ?) e& q* t
1487656 ADW            LIBIMPORT        PreAnalyze reporting false warnings
0 U+ A7 q/ c3 g- u' l1487733 CONSTRAINT_MGR OTHER            Running Export Physical - It takes over two hours to update the PCB Editor board
7 {9 U: d0 T8 j! U* I$ N. `+ ]4 R1488753 CONCEPT_HDL    CORE             Import sheets in a design with no change in models: CM_VALIDATION_ON_SAVE variable is triggered* F! B) ?9 z0 R# z! c
1488758 CONCEPT_HDL    CONSTRAINT_MGR   CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager
3 s  l* g* I+ _& S" R1490299 SCM            OTHER            ASA does not update revision properly
0 s; m! F3 b: Y. b1490744 ALLEGRO_EDITOR SKILL            axlChangeLine2Cline changes line to cline and places it on the TOP layer- w: _8 k2 a% ?, s" ~
1490924 F2B            PACKAGERXL       Save Design/Export Physical is resetting Via constraints
- h" @1 V+ E6 {! c" W: ]3 E1491351 ALLEGRO_EDITOR OTHER            Create Detail for bond fingers on a custom layer not working
. T& i; Q$ _* p% D) [1492013 CONCEPT_HDL    CORE             Stale PNN properties not cleared from schematic on packaging design (backannotation)/ X( A# B/ Z; v6 v8 M& k
1492595 ALLEGRO_EDITOR MANUFACT         Dimension character substitution help is wrong  G% s7 Y. y/ Y
1492703 CONCEPT_HDL    OTHER            'Global Property Display' not working for symbol edit
: }5 B! |# x9 c, R8 \1492777 ORBITIO        ALLEGRO_SIP_IF   OrbitIO import of customer mcm results in crash7 O3 Z% u; v5 a6 c' Y' v  d. o
1492901 CONCEPT_HDL    CORE             Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL1 c* x0 x+ d+ \( j% N
1494194 CONCEPT_HDL    CORE             Random display of the 'PHYS_NET_NAME' property in hierarchical designs+ R: P- ^6 L1 C& v4 Q- v/ \1 p
1497597 ALLEGRO_EDITOR DATABASE         Show Element on pin shows wrong drill size; {3 T- W' D' ^/ d: X
1497956 CONCEPT_HDL    CORE             ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root
- b  Q4 h: h3 j0 i1 t8 U7 G' i$ {1498234 ALLEGRO_EDITOR ARTWORK          PCB Editor fails to create artwork and no error is listed in the log file
$ s( Y. f* r9 a+ D1499363 CONCEPT_HDL    CORE             Custom attributes under variant management stopped working in Hotfix602 @3 \( H, G! j" E, l/ ^
1500422 ALLEGRO_EDITOR SKILL            SKILL function, axlTriggerSet, results in PCB Editor crashing at launch
/ }6 U# x. T# k1500725 CONSTRAINT_MGR CONCEPT_HDL      Unable to clear pstprop.dat file conflicts
: }& f, B# i* N  d# p1501093 SIP_LAYOUT     OTHER            Package design variant shows wirebonds connected to a die which is not part of the variant& B5 e/ X9 g* E' {" f9 ?7 G
1501165 F2B            DESIGNVARI       TDO does not manage overlay files and variant_roz1040660_1.ba cannot be created unless variant_merged.dat is checked out) g" Z: i3 c- Z. Y7 A0 t
1501294 ADW            COMPONENT_BROWSE Missing tabs such as graphics, properties and classification properties that were there before the migration7 z) b! q2 D" a7 D, H, c9 S
1501974 F2B            PACKAGERXL       'Feedback has found Illegal pin swap(s)' error although the pin was already swapped and fed back (B2F) to DE-HDL
# m" e5 I& i7 `: B3 s5 D1502282 ADW            CONF             What does Message: 3 > 2 means?( I+ p2 t' \5 X, T" E( S4 X( `
1502782 ALLEGRO_EDITOR SCHEM_FTB        Allegro System Architect (SCM) - Export Physical stops unexpectedly without any errors or warnings% T$ K% `0 D& V  k' W; k
1504093 ASI_SI         GUI              View Topology and Waveform buttons overlap when Signal Analysis window is resized9 ]- j; ?) H& Y! S% ~, b" p
1504767 CONSTRAINT_MGR SCHEM_FTB        Constraint Manager generates errors if the 'sNoF2BFlow' property is added to the Constraint Manager Dictionary6 H7 C' I4 `5 @4 X9 y' J  ~( s
1506110 ALLEGRO_EDITOR DRC_CONSTR       No DRC shown when a text on etch layer is overlapped on mechanical pin. K$ f: C6 `5 d( m, m, E) ~- ?1 a3 G
1506654 CONCEPT_HDL    INTERFACE_DESIGN Netgroups broken when moving
, ^0 ]% C" A  E4 P' @* C, x1507497 ADW            COMPONENT_BROWSE Switching rows in component browser does not change the graphics of the symbol
7 n9 u# `3 s+ z% ?4 ^7 J+ [* x0 G1509184 ALLEGRO_EDITOR DATABASE         BB vias in mirror have terminal pads suppressed by artwork
7 c9 o- E* _; d) J! a5 a: t1510387 FSP            EXTERNAL_PORTS   Break in extending a net as a deep connection when it is targeted to multiple FPGAs connected in a daisy chain
* C. y0 E4 y6 i1510570 ADW            DATABASE         ERROR: Unable to check in block model because the part with instance id used in the model is not available in the databa
/ [9 e: y2 c  A1511180 ADW            DBEDITOR         The DBEditor dialog wizard shows an incorrect message about a schematic mode when performing an association of a footpri% |- K5 V! ?; z4 o( l: C4 q
1511397 SIP_LAYOUT     TECHFILE         Tech file exported from release 16.5 cannot be reused in SiP Layout in 16.5 or 16.6* p! B* G1 l3 V
1511744 ALLEGRO_EDITOR OTHER            Allegro PCB Editor removes property from component instance% {0 c& k" g5 x: z( C7 q
1511761 SIG_INTEGRITY  OTHER            Allegro PCB Editor crashes on running the cns_show command.- \8 ~$ t' [: I8 z; w
1511947 ADW            DSN_MIGRATION    Command line arguments of the 'designmigration' command are not working
  T) ^. m' j$ ^( F1513085 CONCEPT_HDL    CORE             NC pins combine with NC_1 and routed as one net in Allegro PCB Editor7 \+ r& g5 e- z* [9 I
1513092 ADW            DBEDITOR         Create Footprint Model name is not working properly if it already exists in the local flatlib1 ?! k$ ^! C! `; d! p6 M
1513737 ADW            CONF             DesignerServer from a different network domain does not show distribution data
1 @4 P* c7 v: d1514469 CONCEPT_HDL    CORE             Unable to get rid of an underscore from the PHYS_NET_NAME property
$ f2 F' l( z) k( e8 `* X1 F2 Z$ G1514942 SIP_LAYOUT     CROSS_SECTION    Why is AIR not permitted in stackup in 17.0?
  `. R1 n. f. l1515318 PCB_LIBRARIAN  IMPORT_EXPORT    Import Pin Table: 'CTRL + C' and 'CTRL + V' not working correctly5 j% u9 I6 x9 T' c$ s
1517351 CONCEPT_HDL    CORE             Genview does not update an existing split symbol
- z6 s/ \8 {  R: ~; z. p1517388 ALLEGRO_EDITOR SHAPE            DRC error reported as PCB Editor fails to read the void for a via3 b& J3 g* U3 @# R) N
1518032 CONCEPT_HDL    SECTION          How to get rid of error 'SPCOCN-2009 - Symbol has the SEC property but the required SEC_TYPE property is missing.'; m# P1 T# s- k$ \- c# K2 q+ \8 O
1518724 PCB_LIBRARIAN  PTF_EDITOR       PTF Editor is not saving changes/ Y( S% z( W* J0 u1 W6 L
1519040 ALLEGRO_EDITOR DATABASE         Match groups are lost when a board created in SCM is saved in Allegro PCB Designer.: R; b; S) O5 h4 T$ o, ?' |
1519518 CONCEPT_HDL    OTHER            Genview does not generate split symbols0 ^& y$ B! j( r
1519623 CONCEPT_HDL    CORE             Differential pair added to a NetClass does not display 'NET_PHYSICAL_TYPE' on the canvas4 Q* K7 t. N* r1 p
1519910 CONCEPT_HDL    INTERFACE_DESIGN Hotfix 62: Information on manually-remapped port groups is not saved, but reset to default
5 ~4 ?/ S( g1 U6 s1519946 CONCEPT_HDL    CORE             Renaming a net leads to loss of constraints associated with the net
) h) p  n  a# L( G% O' [1519987 ALLEGRO_EDITOR SCHEM_FTB        In Hotfix 61, constraints are lost on importing a netlist8 m2 V* _; C/ w0 p
1520207 CONCEPT_HDL    CORE             Genview crashes after renaming ports
* E( p+ K/ m; a3 x1520727 CONCEPT_HDL    CORE             In Project Manager, the 'Design Sync - Export Physical' command does not automatically update the schematic& y1 F4 m. c7 `1 r1 y# w5 i
1521174 SIP_LAYOUT     DIE_STACK_EDITOR Padstack shapes not converted correctly to die-stack layer using Die-stack Editor
; E4 W6 T! d( P6 _$ f/ S' X1521871 CONSTRAINT_MGR CONCEPT_HDL      CM from DEHDL Allows Creation of Layer Set Name with Illegal Space and No Warning
+ ?) V8 ]* W, S2 `: M( c1 d; {$ @$ S' E1522831 APD            OTHER            axlSpreadsheetSetColumnProp with 'AUTO_WIDTH' propName does not autofit the contents.
6 @  Q" V! g- T1522900 ORBITIO        ALLEGRO_SIP_IF   Padstack shape distortion after translation to OrbitIO from SiP design
8 p; o' F, o+ d3 V, C1523237 ALLEGRO_EDITOR SKILL            SKILL function axlDBGetExtents() causing PCB Editor to crash
8 A- B' R0 ?7 C+ f1523426 ALLEGRO_EDITOR DRC_CONSTR       Dynamic shape not adjusted based on keepout; DRC generated0 p; C7 [! f- J3 W  z! M6 g/ |
1524875 F2B            PACKAGERXL       Packaging using csnetlister fails, while manual packaging of individual blocks works fine3 Z2 N$ ^8 |7 C" {  }
1525432 CONSTRAINT_MGR OTHER            User-defined property not being transferred from DE-HDL to PCB Editor6 Y1 u7 u- |4 Z1 W0 L7 V; ^9 j$ r1 _
1525883 ADW            DATABASE         invoking libimport on an existing DB should verify that the libimp_su variable is set correctly! y8 e; L  \& }7 O
1525948 F2B            PACKAGERXL       Reference designators assigned by the Packager tool are not correct
# G8 y) `1 h1 y$ ?7 d' O2 P1526914 ADW            LIBIMPORT        Can not import to new library DB: M& N7 _" c  B. L, S* ?- A: z
1527321 ALLEGRO_EDITOR SCHEM_FTB        Unable to create netlist with the 'Open Board in OrCAD PCB Editor' option in Hotfix 63
* a+ Y0 w4 C  k( q% b! ]1528075 CONCEPT_HDL    OTHER            Auto Generate: DML model assignment fails with error 'There is PHYS_DES_PREFIX property in PTF file.'
- w/ o) H$ t' I' Y. k3 y; t$ J! C1528235 ADW            DBEDITOR         About the rule "Validate Classification Property and Property Values" of Release/Pre-Release9 z% G) h8 W: q: v
1528254 CONSTRAINT_MGR CONCEPT_HDL      Import Logic with the 'Overwrite current constraints' option is deleting some attributes" z% D4 w0 \1 n! Y5 F+ B9 P% c, x, I' r
1528398 ALLEGRO_EDITOR SCHEM_FTB        Problem with pin number format used in NC property& w. y( U' K: n, s) p
1528479 ADW            LRM              LRM crashes when opened on a lower-level block in a hierarchical design
) P. h) p. o. }1 `- |/ V: K3 \1528894 ADW            DBEDITOR         Lack of PTF_SUBTYPE in the classification prevents Part's release
; ~  m9 L- x! n9 _1529178 SIG_EXPLORER   OTHER            Values not transferred correctly for PinPairs when created ECSET from a net
$ W: |  S/ M! P  H1 k# j1529209 CONCEPT_HDL    CORE             When adding a component symbol version, the More option does not show all the versions4 l. P0 }6 c7 h/ X+ ^. t: }" j0 A
1529720 CONCEPT_HDL    COPY_PROJECT     Running ADW copy project does not update the 'master.tag' file
9 F6 K% {' M8 D9 i1 P) T1530445 ALLEGRO_EDITOR EDIT_ETCH        PCB Editor crashes when 'Add Connect' is used0 i' V% o8 K) d0 s. b  [# [
1530707 CONCEPT_HDL    CORE             Request to recover a 16.6 design after DE-HDL crashes, l# @, v3 o3 Z
1531425 CONCEPT_HDL    CORE             DE-HDL crashing while trying to add a NetGroup
* f# M1 e9 e  \) j& ^6 R1532865 CONCEPT_HDL    CHECKPLUS        Provide the ability for Rules Checker to report a GND symbol from the standard, and not our local library, in .mkr
0 y" ^" [: @" g1 N  l1533543 ADW            DBEDITOR         Component Browser free text search returns 2 parts when only 1 exists
3 j5 e( ]- k* t8 {1536273 CONSTRAINT_MGR CONCEPT_HDL      Model-defined differential pair is removed, and Constraint Manager Design Differences does not report an issue9 _0 {0 F" Y' |5 y
1537055 CONCEPT_HDL    CHECKPLUS        Rules Checker - POWER_PINS value not obtained when schematic instance has the POWER_PINS and POWER_GROUP properties3 i; A7 X. w7 ~
1537339 CONCEPT_HDL    INTERFACE_DESIGN No warning is flagged when moving a Net Group over a net
4 U1 H6 s1 T1 i# U1537521 FLOWS          PROJMGR          Do not allow project creation if there are spaces in directory or file names on the Linux platform
$ D) i- T& [# H  R# }. g1539077 ALLEGRO_EDITOR SYMBOL           PCB Editor crashes when choosing 'Layout - Renumber Pins'1 n3 Y+ A: r9 N' ?8 M; O2 Y/ N
1539227 CONCEPT_HDL    CORE             Renaming a page from the hierarchy browser crashes the schematic editor.) ~* O6 @# u2 I! H
1539997 ALLEGRO_EDITOR SKILL            PCB Editor crashes when the axlStringRemoveSpaces() command is run
. @5 C+ U* F! _, W7 a- h1541532 SCM            SCHGEN           Generate Schematics crashes with 'Out of Memory' error/ }$ J& T. u* ]
1541680 CONCEPT_HDL    DOC              A dot (.) or period in design name created 2 separate design folders in worklib
! B! |- i5 [1 Z& d/ @) N1542817 ALLEGRO_EDITOR DATABASE         Import Netlist not getting completed on specific board
6 d* ?( i$ L4 L( T& K1542949 ASDA           EXPORT_PCB       Export to PCB Layout Fails to Accept Entered Output Layout File Name2 O9 s) y' f& U% C+ R) u
1543537 ASDA           NEW_PROJECT      While creating new projects, the new folder name is not visible clearly in the explorer
; B4 U. K% U0 V7 [+ y$ P5 l* g1544060 SCM            SCHGEN           Generate Schematics causes Allegro System Architect to crash
( d7 K- o7 v7 b2 }. o1544633 APD            STREAM_IF        The 'stream out' command causes Allegro Package Designer to crash/ c2 W. p; c9 a' d. A! p6 H5 c1 _
1544698 ALLEGRO_EDITOR PLACEMENT        'place replicate' does not add clines and vias to fanouts if fanouts are marked
) v+ Y# g$ `( V* A1544856 ASDA           CANVAS_EDIT      Edit > Find places the process (UI) behind the SDA tool.5 e1 X* w5 X( x5 D
1545136 ALLEGRO_EDITOR PLACEMENT        All fanouts are marked as part of one symbol instead of the symbols they attached with
2 J6 I7 C6 j2 \$ S5 _8 e1546062 ADW            TDO-SHAREPOINT   Failure to launch TDO Dashboard, need to update error message with more useful information8 q7 T' `& w5 F9 i9 T, U
1549105 APD            OTHER            'Stream out' fails with message: 'Request to terminate detected. Program aborted'
+ W, v# l/ O# R9 ^3 x; G, i1549658 ADW            TDA              Unmapped network folder in TDA
8 G/ [7 ?2 P/ k2 V! @2 {1550052 ALLEGRO_EDITOR PLACEMENT        PCB Editor crashes when copying symbols
. m0 w& H8 E% {9 A4 c" n0 d1551635 CAPTURE        TCL_INTERFACE    GetSelectedPMItems returns error for design cache objects% Y$ w9 Z7 S; M" [( e8 u- [4 t
1553027 ALLEGRO_EDITOR UI_GENERAL       Beta - Allegro display freezing very frequently - canvas not resposive and turns white.! m8 s' n$ i) o7 w6 I
1555246 ADW            DBEDITOR         Part Copy As does not copy AML and reliability model relations.
5 j" k8 M: N0 O- s5 R+ K; @1555254 ADW            DBEDITOR         Loose focus on Free Text search Window removes the text.+ j4 L4 ~6 w# o7 L8 Z4 i9 T
1557542 ALLEGRO_EDITOR OTHER            DXF export creates strange result for donut-shaped polygon
5 t3 C$ W% y$ t. h6 P: L1573039 ALLEGRO_EDITOR INTERFACES       IDX returns control to the general interface prematurely during an incremental IDX export
: S% o3 L; [/ Q. s# G9 a6 w8 r1580571 ADW            DBEDITOR         xml files for released FP and padstacks are left in flatlib area.
' `% x) e4 k' v) q- X' p8 [1580580 ADW            LIBDISTRIBUTION  list files are not getting cleaned up for custom models if they are purged." |% n( N0 a+ u5 _% ?
1582064 ALLEGRO_EDITOR UI_GENERAL       User defined menus not working in 17.2
5 h2 T, u% }" A1582628 ADW            TDA              When one user takes an update of physical object while the other user is still checking in the object, TDO crashes
  w& J! z8 c% n8 V0 \1582856 PSPICE         MODELEDITOR      Getting ERROR: [S2C3471] Base part library does not exist when Export to Part Library, though olb created! Q  d1 h  r% n+ p, P
1584719 TDA            CORE             Caching errors coming for a board ref project while doing Block update& ?$ ^2 t* ~& D1 A% H" p3 x, Z
1587045 CAPTURE        IMPORT/EXPORT    Unable to import PDF file' V$ e. F3 E, ~
1587259 ALLEGRO_EDITOR UI_GENERAL       axlUIMenuFind not working correctly for the 'bottom' option
1 q/ n2 M, [% E1 Y1588736 PSPICE         MODELEDITOR      Model Import wizard says "Invalid configuration" when lib opened in Modeled0 P3 d( b4 ]9 J# S7 r' t! {
1588742 PSPICE         PROBE            Browse icon is missing from Pspice File > Export > text
9 i( d3 H0 e: c& ]/ z4 T" C; w  E1590006 ALLEGRO_EDITOR UI_GENERAL       PCB Editor 17.2 crashes when multiple browse windows are opened! o) J4 h6 S# J5 V* }! P
1590597 PSPICE         PROBE            Problem with the adaption in the Probe Window icons
7 f4 y7 L- t' B7 i  U1591264 ALLEGRO_EDITOR UI_GENERAL       Film order in Visibility View sorted alphbetically and does not match with the Manufacturing artwork2 ~+ _# y2 X' @5 g
1592089 PSPICE         MODELEDITOR      Can not get PSpice DMI Model DLL while using PSpice DMI Template Code Generator* u0 G' i* d$ n2 ?4 |) n. [9 O
1593436 ADW            DBEDITOR         new Model type form does not focus cursor in window, User must select the Model Name before any text shows up( P, g4 L0 N. q% i2 M* F
1594076 TDA            CORE             TDO is crashing on concurrent checkin when one of the user got blocks which are not modified
3 s0 O2 v7 ?6 S. i4 O$ K1595987 ALLEGRO_EDITOR PLACEMENT        Subclasses not getting updated in Placement Edit mode. @5 g" G0 v( A& I0 j" }
1596162 ASDA           IMPORT_DEHDL_SHE Importing sch pages from DEHDL imports the block as well  o" T# l  u9 U  G3 c) ^, f$ J( I
1597000 CONCEPT_HDL    INTERFACE_DESIGN Renaming NG does not work if >1 segments have NG names$ f9 X9 v+ s2 Z1 l
1597406 ALLEGRO_EDITOR SHAPE            Dynamic Shape does not void the traces and voids open areas2 m. y2 |0 f( f$ |6 K
1597957 ALLEGRO_EDITOR PLACEMENT        Quickplace: placed and unplaced counts not getting updated+ o  g! u( V( Q  m" x5 B% E6 _  ~
1600194 ALLEGRO_EDITOR DRC_CONSTR       Update drc command changes the amount of DRC count when using 8 threads! V3 M/ g9 V) U7 ~0 u
1600800 ALLEGRO_EDITOR GRAPHICS         LINUX 17.2 operation of Update DRC is not the same as Windows – graphics not updating
( R; g2 N$ O$ @1602605 CONSTRAINT_MGR OTHER            OrCAD: constraints not getting saved
2 U  a5 L5 T2 T, P0 Y4 W1602801 SIG_INTEGRITY  OTHER            Dielectric Warning message when opening SiP tool.
" j. f8 M2 N& g' Q4 L: a1603377 PSPICE         ENVIRONMENT      At Markers Only option does not generate .dat file
; f0 C7 Q/ |5 q+ w' q1604166 CONSTRAINT_MGR CONCEPT_HDL      Audit ECSets does not work from 'Referenced Electrical CSet' column header4 h& x% b3 V& d! O  a: t
1604741 ASDA           CANVAS_EDIT      tcl console changes the present working directory (pwd) when you open the proj preferences & close it.
% V! c/ W' e' ?7 F) w1605310 TDA            CORE             TDA is crashing sometimes in the Join Project wizard
  q, |  {$ O, z6 M% J* S8 |1606861 CONCEPT_HDL    CORE             Crash on Linux during Generate View2 j3 e* c' }- P0 [0 y
1606917 CONSTRAINT_MGR CONCEPT_HDL      Importing tech file in DE-HDL Constraint Manager is creating a duplicate 'DEFAULT' cset
% [; s6 A! r4 k9 p0 z: B4 U% T2 U1607157 ALLEGRO_EDITOR INTERACTIV       Edit - Change allows lines to be copied to Cutout subclass, but that subclass requires closed polygons
" y4 X! ?- y# C/ ~0 l/ Q; f9 ^1607330 CONCEPT_HDL    CORE             Variant view schematic PDF corrupted with attach_props set
6 j+ o, {$ b* @; Y; m( `1607568 ALLEGRO_EDITOR NC               Allegro shows wrong drill legend Top to Top drill.7 I/ k8 x, ?) N
1607986 CONCEPT_HDL    SKILL            cnGetSetupProjFilePath skill command in SPB 17.2
0 w6 B3 t$ R8 {% R9 x1608524 SIP_LAYOUT     MANUFACTURING    The Display Pin Text tool fails in the 16.6.073 version with a parseString error.
0 O* }4 f  Z. G1609400 ASDA           CANVAS_EDIT      RMB > Assign Differential Pair should be grayed out when a single net is selected
& O) x) G! o+ w+ N" p1609809 ALLEGRO_EDITOR UI_GENERAL       Crash in Allegro PCB Designer version 17.2-2016 on Linux
( S8 A" ?9 k- C- m. w1609856 ALLEGRO_EDITOR ARTWORK          Embedded paste and soldermask showing up in both top and bottom gerber files.
) |( ?6 e; Y- `: M! i2 k1609922 CONCEPT_HDL    INFRA            Launching Model Assignment crashes DE-HDL when the temp/edbDump.txt is read-only" C4 x$ R8 T2 N* U: O+ Y& v. \# i2 _( r
1611226 ALLEGRO_EDITOR SYMBOL           Allegro shows crash message while saving flash symbol.
2 @6 m9 w7 ~( W" _! I7 I' A: ]! \4 H1612108 ALLEGRO_EDITOR OTHER            Netlist Import is crashing with the .SAV message.& C6 [3 C. Q( r
1613123 ALLEGRO_EDITOR SKILL            drillType Attribute in Skill for Ovel Drill return OVAL SLOT in place of OVAL_SLOT& ?8 V1 C5 t( e' a7 m
1614000 ADW            LIBDISTRIBUTION  lib_dist does not complete and does not allow to delete the .lck file.6 X" M+ ~1 A9 V0 h( \
1614667 SIG_INTEGRITY  SIMULATION       Different results from Probe in SI Base and SigXp7 E8 `6 H% O& b  C: w
1615601 GRE            IFP_INTERACTIVE  Delete Bundle then try to delete plan lines results in fatal error6 s, Y* L3 W% k+ d
1616235 ORBITIO        ALLEGRO_SIP_IF   oio2sip import doesn't map layers correctly
* j% n, e& l# I. _' e8 O: H7 X0 P1616540 SIP_LAYOUT     DRC_CONSTRAINTS  Same net DRC Line-to-Line reappearing after dyn shape update2 r+ ^" u3 E6 `6 X# e4 Z# w
1616733 ALLEGRO_EDITOR INTERFACES       Genrad output no longer working in 17.2. Gives Error: extracta process failed. Command terminated: i% s$ S% Z; x# L7 _; ~, d
1618751 ASDA           DRC              SDA is showing Zero node Net errors when we run DRC checks, but user had RETAIN_ZERONODE_NET 'NO' in Site CPM file.
; i0 f4 H' o0 q1618797 ADW            FLOW_MGR         Flowmgr fails to execute command
6 V7 c( v0 L2 L# x1618930 CONSTRAINT_MGR INTERACTIV       Hovering over row column cell causes the application to go into a not responding state.
3 Q9 o3 x" t) Z3 o1620350 ASDA           EDIT_OPERATIONS  Uupdating version for a connector pin looses the pin number
( u5 P# l8 a: W( V0 S  r1621963 ASDA           SELECTION_FILTER When working in SDA, I am able to select "Pins" on all parts except connection pin symbol.
3 @6 S% V+ D. N; V# Y5 o1622715 CONCEPT_HDL    CONSTRAINT_MGR   Extracting a XNet crashes the tool
* ^- c. }4 t4 u: H, j# Z; F1625209 ASDA           IMPORT_PCB       File Import from Allegro shows board differences
# @1 g; M1 v* `  X, PDATE: 07-28-2016   HOTFIX VERSION: 003
+ w! J. o( p4 E===================================================================================================================================1 V+ b' f* v, S2 n9 n; _! u
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
- s9 R6 q5 X9 w) b( f  Z===================================================================================================================================" x( u8 T/ v  F1 m4 I
1423889 ALLEGRO_EDITOR EDIT_ETCH        AiDT gets poor routing result
' B8 p. F8 L2 L" o: c. m1461626 CONCEPT_HDL    CREFER           CREFER shown to each instance of block pin though net changes9 r- S  h' M: c
1472456 CONCEPT_HDL    CORE             XCON and design are out of sync
6 w( [" m6 }. {) o1 ]& `% U( w& l1546151 CONCEPT_HDL    CORE             Add port, Genview, move pin on block - the pin name disappears3 u8 {1 U) t- H
1547356 ALLEGRO_EDITOR EDIT_ETCH        Results variations from ISR S034 to S066
; ^. Y8 _+ s0 D, P& W1560102 ADW            FLOW_MGR         172BETA: eval in command string does not work2 f1 V: M) T) |! v' J  ^3 V
1570032 ALLEGRO_EDITOR GRAPHICS         Issue with 3D View2 [6 p) i* u9 z
1574676 ORBITIO        ALLEGRO_SIP_IF   sip->oio eco doesn't work properly
! Z) _, S' O7 c8 `9 m9 x1578876 ADW            ADWSERVER        Component Browser crashes when trying to show details on a part number. S7 J: k. s! F/ o  }8 H3 r
1580744 F2B            PACKAGERXL       ERROR(SPCODD-114): Duplicate physical part name NETSHORT found' t# \+ n; j, {
1582863 CONCEPT_HDL    CORE             Generate View creates non existent ports
0 V' V. O4 j8 v3 Z1584317 CONCEPT_HDL    CORE             When  packager fails, no option to open pxl.log file from design sync window.
; u* `. M9 q0 \+ R1587018 ADW            FLOW_MGR         Project Update at Ericsson in ADW 17.2 asks to specify flow name.+ @4 m5 x5 ]# J' ^; k7 p
1587157 CONCEPT_HDL    CONSTRAINT_MGR   pstprop.net reports conflicts on nets with VOLTAGE properties
& O; n5 E( \6 R, i: m8 v8 O1587498 CONCEPT_HDL    INTERFACE_DESIGN Possibility to tap bus bits removed
) t  `0 u; k- s1587718 ADW            LIBIMPORT        Library Import Pre-analyze report is not being written4 P0 K8 A. v% x+ y. j
1588197 ALLEGRO_EDITOR INTERFACES       STEP output fails when External copper selected on Win10-17.2
- z! j9 z/ V# h; u; d/ {# A2 F1588786 ALLEGRO_EDITOR OTHER            strip_design reports "Design corrupted message"
. p" D" Y0 {5 Z! W1589252 CONCEPT_HDL    CORE             Search options go to page origo not chosen component
# V" V$ A; l. r4 e+ R1589318 ALLEGRO_EDITOR DRC_CONSTR       Via to SMD Fit DRC between Embedded pin and via which do not share layers3 f8 t% n8 f6 B" B4 }' K
1589979 ADW            FLOW_MGR         Design Name change in EDM 17.2 doesn’t reflect in flow manager in same session of project& U1 n& R0 g& u2 H" M% B
1590538 CONCEPT_HDL    DOC              Open Archive shows unclear behavior& ^; x4 J' b% X, n
1590639 CONCEPT_HDL    OTHER            DEHDL crash when importing design
" B( f# o; R0 i" I7 a1590651 CONCEPT_HDL    INTERFACE_DESIGN DEHDL duplicate NetGroups created in Interface Browser and CM
( U3 X( }1 V/ T/ i' T+ `" H1590720 ALLEGRO_EDITOR INTERFACES       Text Size Parameter file does load names into the text table0 Y( r% @/ Z8 d
1591070 PSPICE         PROBE            PSpice crash while evaluating measurement from trace>measurements
2 B! U, `# a) G9 x5 P$ D1591223 CONCEPT_HDL    CORE             Variant information does not display on lower level schematic7 H  Y: Y# z' s+ W7 A) E! l5 n! w
1594240 CONCEPT_HDL    ARCHIVER         Archiver is not able to change the permissions of the cells archived% x- z4 [& [% |/ i$ V# C
1594416 ALLEGRO_EDITOR PAD_EDITOR       Padstack Editor crash in 17.2. O: @" S5 s! U# S% d, W, q
1596615 ADW            DBEDITOR         Component Browser didnt come up to search parts, also the database editor didnt return search results
/ q) {- W% D. \1596780 ALLEGRO_EDITOR SKILL            PCB Editor crashes after doing SRM update and save
' R/ q: X0 j4 Q1 ]" y) L1597153 F2B            DESIGNVARI       ERROR SPCODD-53 in Variant Editor
/ M: P$ @: g0 |# z2 q, m7 t1597385 F2B            DESIGNVARI       Some 16.5 variant DNI parts are now appearing in 16.6 as X-OUT and some don't have X-OUT or DNI) V& }, ]6 S. u
1598629 F2B            PACKAGERXL       Export Physical crashes
  r1 l: w1 }, M. b1599452 ALLEGRO_EDITOR ARTWORK          Import Artwork, Mirror option does import pins or shapes.4 J7 c9 B, _8 c: m+ E, n+ Z
1599744 ADW            FLOW_MGR         Few flow manager buttons are not working in EDM 17.2
) e& x7 X. {0 X- \! k! C0 L1599950 SCM            OTHER            Adding the GND net to parts/pins takes a long time.; [/ F4 o( F8 m" i& N
1600226 RF_PCB         AUTO_PLACE       Fail to auto-place RF group
7 M: ^# ^0 t& O1600618 ALLEGRO_EDITOR DRC_CONSTR       case sensitive issue with Physical Constraint Set
) n* z* M; m: _9 \+ X5 U, y1600914 ALLEGRO_EDITOR INTERFACES       File > Export > PDF shows the shape as unfilled.. v" p" _5 \4 p0 A
1601165 ALLEGRO_EDITOR DATABASE         Thermal Relief is not added for Rounded Rectangle pad
9 N' U  K3 @' g" Z! e0 _0 L1601281 ALLEGRO_EDITOR OTHER            STEP model link gets corrupted with SKILL axlLoadSymbol
. K; J  A7 j4 ^* l$ T- b; O1601282 ALLEGRO_EDITOR OTHER            Export Libraries will not export device files when there is a space in the folder name.% V' r, s/ y# J* [% F6 z' l
1602514 PCB_LIBRARIAN  METADATA         References to some primitives is missing in block metadata causing TDA errors for missing parts after join project
( f" S+ o7 X2 K, }1602823 SIP_LAYOUT     WIREBOND         SiP Crashed during Add Wire command
) `. V7 O+ g' G* Z1602955 ALLEGRO_EDITOR SHAPE            Shape no DRC when there is a Route Keepout in base layer.
2 `- A* c/ s# `( p7 O1604223 CONCEPT_HDL    CORE             ERROR: SPCOCD-553: Connectivity Server Error
+ ~. a+ m4 l4 S4 U' V1604746 ALLEGRO_EDITOR OTHER            In 17.2, there is a discrepancy in layer data when importing extracta files into their Mentor Graphics extraction tools., ~; n# ~# Y  g4 ]9 A% J- O0 W: I
1605322 ALLEGRO_EDITOR TECHFILE         Cadence SPB17.2 Issue - Long duration in Tech File generation9 X4 o6 ^( ^0 l3 M
DATE: 06-31-2016   HOTFIX VERSION: 002
$ o7 t! b0 ^: f8 S, ]===================================================================================================================================/ m, w$ V/ P% R5 @& M) r
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE+ t) b! _( J* q' F
===================================================================================================================================
1 ]7 x) k) G0 B! e# l- {1452838 CONCEPT_HDL    CORE             Apparent discrepancy between Bus names and other nets" F+ D7 I8 {$ ]* v$ `
1469146 ADW            LRM              ERROR(SPCODD-5): Pin '1<1>' on the following primitive instance cannot be packaged in package
0 E( I$ k; O6 f# W' g* G6 W* i" M1 _1481802 ORBITIO        ALLEGRO_SIP_IF   import of oio to an existing sip offsets the results incorrectly
4 `3 J( G7 J9 ]" q$ \7 D1518957 APD            SHAPE            Shape void result incorrect
& y: O  c. K9 {7 U1519155 ALLEGRO_EDITOR OTHER            IPC-2581-B Negative Plane Error* E8 Y0 L" x- R( j
1524947 SIG_INTEGRITY  SIGNOISE         SI Base, PCB SI: Custom Stimulus is not recognized correctly! S# J6 ?' H' {+ Q: Z6 _# \
1532162 CONCEPT_HDL    CORE             The Rename Signal command does not update split symbols.
) o- W2 P% g, _! X; I4 G1543997 CONSTRAINT_MGR OTHER            Import Logic is overwriting the constraints in attached design.7 v; w: u" Q9 L7 p- Q+ S
1544675 ALLEGRO_EDITOR OTHER            Export libraries corrupts symbols if paths do not include the current directory (.)
/ `7 |! c! K1 V' y3 B1549097 CONSTRAINT_MGR XNET_DIFFPAIR    Need to warn users creating differential pair(s) in the Physical Tab with nets that have voltage properties set  P, u* D7 f7 ?8 M$ I" ?- d
1551934 ALLEGRO_EDITOR SKILL            axlBackDrill command is not analyzing new layer set when application mode is set to 'None'2 q, I. {. K6 F/ k
1554919 ADW            LRM              LRM does not find PTF data for cell 'res' in the reference library
% |* o2 F8 F* W1555009 CONCEPT_HDL    INTERFACE_DESIGN Not possible to rename NG. W! k6 X* p5 D
1559136 ALLEGRO_EDITOR EDIT_ETCH        Cannot connect floating clines to vias with nets5 G5 L5 P5 M8 e# i- Z
1559552 SIP_LAYOUT     ORBITIO_IF       device offset in oio2sip translation
/ W( L! p1 I) c# [$ ]2 _5 N1560301 CONCEPT_HDL    CORE             DE-HDL hangs when Edit menu commands are called on Linux if xclip is open
/ v$ c2 T& \8 ^) _! X3 `2 m1560804 ALLEGRO_EDITOR OTHER            Film records order gets reversed when using File - Import - Parameters after File - Export - Parameters
0 e8 X) K: u" n7 B  A1561501 ORBITIO        OTHER            oio -> SiP refresh seems to hang
/ v6 A8 @! C; h8 H/ U5 w5 Z, }  L1564036 CONCEPT_HDL    CORE             User-defined custom variables are not getting populated in the TOC
. {3 ?7 _' F5 ^* O1564545 CONCEPT_HDL    OTHER            Signal model property deleted from an instance is not deleted from the instance pins
$ Y& ?3 Y- e* k" U! U. |4 G3 R, f1564552 CONCEPT_HDL    CORE             Find Net should zoom to the nets on schematic canvas" t; P% n' S6 j2 r- P6 ?
1566119 CONCEPT_HDL    CORE             Right-clicking the schematic to add a component does not show all the schematic symbol versions1 t) k; f; Y# J* p3 t
1566848 ALLEGRO_EDITOR ARTWORK          Board Outline artwork is incomplete
+ I& N/ E+ v' b  H* J  m1566942 ASDA           MISCELLANEOUS    SDA172: A lot of files in /tmp/ on Linux
' l8 z6 p$ ^1 ?1567290 ALLEGRO_EDITOR MANUFACT         Import Artwork fails to import a shape.+ R/ l' j4 C, N8 `8 y
1567587 ALLEGRO_EDITOR MANUFACT         Extended tool name in header of drill file is not correct
# ^1 H& O' l7 S1569056 CONCEPT_HDL    CORE             Opening New Cascaded Window Causes Graphics Artifacts on Old Window5 \- e' T; m# k" w" E
1569087 ALLEGRO_EDITOR DRC_CONSTR       Running DRC Update gives the message  'Figure outside of drawing extents. Cannot continue.'+ Z9 {1 M0 ~6 k+ P* }8 r
1569147 CONCEPT_HDL    CORE             Signal Name AutoComplete Drop Down List Not Correctly Displayed
5 S. \& R9 h' X3 M6 [1569394 ALLEGRO_EDITOR SKILL            axlPadSuppressSet( 'on 1 '(via)) not working on SPB17.2
% _* W; f5 Y$ r( C0 g1569924 CONCEPT_HDL    CHECKPLUS        ERROR (body_to_physical_check) - Pin name(s) not found in package : PEX_REFCLK0_N* PEX_REFCLK1_N*...7 q0 L( T, b$ J  {9 k: _9 d
1570398 SIP_LAYOUT     DATABASE         Diestack layers can't be deleted if there are unplaced symbols in the design
0 u; X% C6 p! W1 x* D1570419 CONSTRAINT_MGR CONCEPT_HDL      How do I add a customized worksheet custom property weblink in Constraint Manager* |6 W/ {3 R$ `- @$ A! l
1570624 APD            ARTWORK          Artwork file has missing voids on a layer and is causing a short
* E0 P5 j3 x, C2 v1 F% \  p1570678 F2B            DESIGNVARI       Variant Editor error when adding an RSTATE property
$ `' t0 A: H* y1571113 CONSTRAINT_MGR DATABASE         Reports generated from cmDiffUtility show the differences in mm units only; M5 X9 J& r4 \! A% t+ @+ ^
1572593 ALLEGRO_EDITOR ARTWORK          ARTWORK: 'Draw holes only' option does not match display0 `; i- d; C4 C; g0 G. ?
1573127 CONCEPT_HDL    COPY_PROJECT     copyproject creates incorrect view_pcb entry
" w8 P. {8 m& X0 }7 p+ Z1573205 CONCEPT_HDL    CORE             dsreportgen is unable to resolve the physical net names (PHYSNET)/ [8 i+ V: K' O% U  D, U
1573625 CAPTURE        PROJECT_MANAGER  Toolbar customization is reset when Capture is re-invoked in SPB 17.2
6 t  ^; J8 `7 K. ~1573755 ALLEGRO_EDITOR CROSS_SECTION    Switching between plane and conductor changes material in Cross Section.
4 Q6 f* ]+ G! p: }0 S0 F( d- v1573970 CONCEPT_HDL    ARCHIVER         archcore fails to archive the <project CPM>.arch file
0 t$ c3 X# z4 e: {; A1574381 CONCEPT_HDL    OTHER            Packager crashes with some advanced settings0 C: b9 B) G( c& Y" w
1576100 ALLEGRO_EDITOR SYMBOL           Update symbol crashes, creates '.sav' file, but shows update was successful in 'refresh.log'9 }! ~$ S; x7 W
1577381 CONCEPT_HDL    CORE             ERROR(SPCOCN-2128): The NetGroup structure does not match the PortGroup structure
' G* k& R) i- Y) w1580103 ALLEGRO_EDITOR DATABASE         dbstat of 16.6 does not recognize 17.X files$ N  U$ S2 r& b1 |5 A) l& W
1580891 SCM            REPORTS          Dsreportgen crashes on different scenarios
% R6 {! l. r, o* J1581254 SIP_LAYOUT     CROSS_SECTION    "Apply" or "Ok" crashes XSection
/ Z  Y! D0 s1 I1584957 ADW            FLOW_MGR         17.2 Flow Manager, JavaScript - Tool Launch Error
0 N. F5 H( a; S1588823 ADW            FLOW_MGR         UNC paths have stopped working in Flowmanager in 17.2+ V0 h- i% ?3 F1 M: ~* b" ?
1590064 ADW            LRM              EDM 17.2 gives LRM unnecessarily.
5 c- e0 S- @' i- p1 d! W; BDATE: 05-06-2016   HOTFIX VERSION: 001
6 K+ s6 ~1 x5 O/ F# {===================================================================================================================================' j" ?, B, a9 U& O; \5 o3 F, e. r
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE; Y  A" j" P0 Y
===================================================================================================================================6 e1 z' a8 @) X0 s! R5 }
1272355 F2B            DESIGNVARI       Property changes on replaced component shows incorrect result in BOM output
: G. c* Q( F& c; Q* ~1482953 ALLEGRO_EDITOR DATABASE         Part change disassociates parts from Group9 V6 f& u7 s* Q) T
1484075 ALLEGRO_EDITOR PADS_IN          'pads_in' imports ASSEMBLY_TOP  and PLACE_BOUND_TOP outlines that are defined as shapes as lines
+ n0 [$ M0 J$ h* \, b0 V  b$ r1488909 ALLEGRO_EDITOR DRC_CONSTR       Test Via causes net scheduling verification to fail6 E0 ^. N2 X0 C+ g# g3 W
1498389 SIP_LAYOUT     DIE_GENERATOR    Provide the ability in the 'die in' command to specify flip chip as a DIE symbol
8 v- v1 z- a; z4 w5 w1499515 ADW            COMPONENT_BROWSE The Search Criteria property value is automatically being set in the ADW Component Browser
5 }' Q6 |8 g  V1506672 ALLEGRO_EDITOR INTERACTIV       Replicate Place - Shapes are missing
0 L3 U. r' B5 N1522411 FLOWS          PROJMGR          License selection should persist on invoking Layout from Project Manager
. ^+ _& O* L1 G# h' b( S1523532 F2B            PACKAGERXL       Adding subdesign names in the "Use subdesign” or “Force subdesign" sections hangs for more than a minute
( l- h) ]2 I" N# [  \1525783 CONCEPT_HDL    CORE             \BASE scope does not work for SYNONYMed global signals% g/ {9 ~- `- V& w4 S, o  u( x
1526729 SPIF           OTHER            Exporting a dsn file causes PCB Editor to crash - in the interactive and batch modes
2 L" ?1 W! u2 Q1529846 ALLEGRO_EDITOR SHAPE            Some shapes are not generated in the artwork& l( q6 [' W% e, N* O- U+ Y
1537499 CONCEPT_HDL    CORE             Adding the same version (already placed) with the same split block name should not be allowed% H. A/ P( z1 y8 o& l, ?
1541589 ALLEGRO_EDITOR INTERFACES       STEP model incorrectly shown in 3D viewer. Shows pins as angled.: q1 V& c0 D! K1 E
1542334 CONCEPT_HDL    CREFER           creferhdl leaving lock files in sch_1 folder6 p4 X7 \3 v, f' }" D& ]
1542722 ALLEGRO_EDITOR INTERFACES       IDX export: RefDes and PART_NUMBER missing for mechanical symbols3 I" U8 t  E6 V" o4 _7 U4 E( c
1543410 ADW            LRM              LRM shows confusing pat status. It reports that update is needed but clicking update doesn't work/ a6 B1 X. `. C/ ~, Y: g- O& s% v
1544614 ALLEGRO_EDITOR SKILL            Associative dimension data reaches the 'psm' file despite deleting the layer on which it was set in the 'dra' file
/ q( O" y- e' n. I: C) ?1545370 APD            OTHER            Pads in .mdd file getting placed on different layers as compared to the design
( q/ x' I) j9 K8 {' n2 a1545909 ALLEGRO_EDITOR UI_FORMS         Show 'microvia' checkbox in 'Blind/Buried Vias' form only with the 'Allegro_PCB_Mini' license
9 R1 t2 c" g9 J/ o1546141 ALLEGRO_EDITOR SHAPE            Shapes missing from Artwork/ n! Q1 t7 t7 [9 [
1546877 CONCEPT_HDL    CORE             Align Left on Wires Fails With Incorrect Error Message
/ c( v+ I7 B: a) P* K1 u& e1547224 CONCEPT_HDL    CORE             Lock the 'PATH' property once it is assigned by system
% l0 d2 ?" d( z/ m1547584 SIP_LAYOUT     OTHER            SiP - Design Variant - delete embedded layer if not selected.
) X2 X3 u, q2 ?- u# ]% Z1548116 CONCEPT_HDL    CORE             Some versions of Technology Independent Library do not appear when adding a symbol7 c6 k9 x. \2 q$ B: m
1548151 ALLEGRO_EDITOR INTERFACES       Exporting a step file gives a component rotation mismatch in the *.stp file! \7 q# P& y* C" Z
1548421 F2B            BOM              Parts with same 'BOM_IGNORE' set do not behave the same way in the BOM report
) ?6 }& f4 @: C+ q' ]1 `3 n1548978 ALLEGRO_EDITOR MANUFACT         Shape not voiding clines7 J5 n' v( ?  I, {, d/ L( s+ r
1549662 ALLEGRO_EDITOR OTHER            Import Parameters Path' fails if parampath does not have the current directory ('.') set
, _! c+ z, `: b' p1549836 CONCEPT_HDL    CORE             Tools -> Customize -> Keys -> Reset does not actually reset keyboard shortcuts2 B& s8 k5 P1 N2 [1 s8 c
1550941 PCB_LIBRARIAN  PTF_EDITOR       PDV Part Table Editor new column sorting causing problems: Z7 K1 g0 e3 p% m: D
1551713 ALLEGRO_EDITOR DRC_CONSTR       Hole to hole drc between Via and pin3 `  r. t3 q4 Y/ P2 I! \, O7 L9 l
1553950 ALLEGRO_EDITOR SKILL            Executing axlUIControl('pixel2UserUnits) crashes Allegro
3 ?( D% ~- ?6 o4 @9 Y) H/ d1554333 CONCEPT_HDL    CORE             Changed connectivity error when aligning ports attached to netgroups
+ ]) ]3 G+ n& a+ N+ a1555092 SIP_LAYOUT     DEGASSING        Degass offset is not working with hexagons6 f; x* l6 e& `7 M% _3 \. z% [; s
1556261 ALLEGRO_EDITOR DATABASE         Running DBDoctor on board file gives an error"Illegal database pointer encountered, Exiting DBDOCTOR." and crashes- c2 p3 P! H0 {
1557716 APD            OTHER            Stream out fails with request to terminate detected - Program aborted  q" Y3 E1 o3 i$ I+ i9 Z
1559951 SIP_LAYOUT     SYMB_EDIT_APPMOD Wrong bump locations after Symbol Editor -> Refresh co-design die
0 n, A) c* a+ t; g! X$ N9 u3 F1560197 CONCEPT_HDL    CORE             bomhdl adds extra charcters to subdesign_suffix when generating hierarchical BOM: B7 n* U+ s( Z! {
1561077 ALLEGRO_EDITOR INTERFACES       Beta - IDX User Layer export fails on Linux- G; w4 i( f  n9 R
1562537 ALLEGRO_EDITOR MENTOR           Mentor BS to Allegro 16.6 results in Fatal Error
+ d0 s8 i- p/ F: p' C9 ~1564203 ALLEGRO_EDITOR ARTWORK          ARTWORK : Can't generate negative film.
8 W) S# y5 ?# F# v% f- w
7 E- f9 J' T* @" e! U1 V
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收藏收藏 支持!支持! 反对!反对!

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发表于 2016-9-10 10:02 | 只看该作者
steven.ning 发表于 2016-9-9 21:387 S+ S: \; I; m# R& j0 J9 K
还是没有可以降到16.6版本的消息。17.2不真心不敢用。
3 T$ K. n; ~' |9 j  Z$ T: G2 _
已用17.0一年多,一条路走到底,没有回头路……2 ~, ?- k7 w, f: M/ v/ W

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发表于 2016-9-10 10:01 | 只看该作者
  Mentor BS to Allegro 16.6 results in Fatal Error 这行什么意思,跟16.6有什么关系?

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发表于 2016-9-19 21:02 | 只看该作者
好多年前学会建封装后就一直没时间画板练手,现在还一直用PADS

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 楼主| 发表于 2016-9-7 01:04 | 只看该作者
:)

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 楼主| 发表于 2016-9-7 01:04 | 只看该作者
:(:(:(:(

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发表于 2016-9-7 14:36 | 只看该作者
有没有下载链接?
' C6 S, |1 j7 K/ N; p# _

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发表于 2016-9-7 16:27 | 只看该作者
都用17.2了?

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发表于 2016-9-7 17:14 | 只看该作者
感謝說明相關 hotfix 內容

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发表于 2016-9-7 21:11 | 只看该作者
好厉害
$ L# g% e5 O; @$ t7 X

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发表于 2016-9-8 10:09 | 只看该作者
patch不到"死",不算数.

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发表于 2016-9-9 11:49 | 只看该作者
大感謝! . i4 `; W. Z' r) n. c3 {. q
Hotfix 一定要來更新與修正的
- u; j2 Y# n* ?" r" R8 T感謝您~

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发表于 2016-9-9 13:10 | 只看该作者
    谢谢楼主

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发表于 2016-9-9 15:55 | 只看该作者
谢谢楼主提供更新内容

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发表于 2016-9-9 21:38 | 只看该作者
还是没有可以降到16.6版本的消息。17.2不真心不敢用。

点评

已用17.0一年多,一条路走到底,没有回头路……  详情 回复 发表于 2016-9-10 10:02

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发表于 2016-9-9 22:03 | 只看该作者
可惜没有链接啊
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