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Since the earliest days of microprocessors, system designers have been plagued by a problem in which the
% B- t6 w1 A9 f1 C2 [4 Tspeed of the CPU's operation exceeded the bandwidth of the memory subsystem to which it was connected. J$ g/ |, @5 w
To avoid wasting CPU cycles while waiting for the memory to fetch the requested data, the universally' R7 m" m# \ ^) j3 \. z$ Q
adopted solution was to use an area of faster (and thus more expensive) memory to cache main memory data.# J; G! T9 p' a) V: S* \
This solution allowed the CPU to operate at its natural speed as long as the data it required was available in+ y! f- C6 o2 {( i6 x0 F7 P
the cache. |
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