pcie AC耦合电容放置位置请教

xiaoyu19890210

1.发送端和接受端都在同一个板子上，AC耦合电容应该放在哪个位置？
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2.发送端和接受端在不同的板子上，AC耦合电容应放在哪个位置？

超級狗

4 ]% Z; C  B( T( i; u樓主的洋文兒還不錯吧？

! L# D2 i2 z: w! e5 L, {' i有個洋人在花旗國網站上，問了同樣的問題。

! B2 r- \6 Y$ t) x結果………

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Where should I put AC coupled capacitors?

The coupling capacitors are usually placed close tothe transmitter source.


1 {! q! G3 d- o- V9 d& t; n1 lGoing along with Dr. Johnson, we need to figure out the distance. The propagation velocity of signals on most FR4 types of board isabout c/2. This equates to around 170ps per inch for internal layers and morelike 160 ps per inch for external layers.

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Using a standard interface running at 2.5Gb/sec, the unit interval is 400ps, so according to that, we should be much less than 200ps away from the transmitter. If this interface has been implemented in an IC,then you need to remember that the bond wires are part of this distance. Belowis a slightly more in-depth look at the issue.

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In practice, coupling devices are placed as close as possible to the transmitter device. This location naturally varies depending onthe device.

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Now the capacitors. This is an RLC device at these speeds, and most devices are well above self-resonance in multi-gigabit applications. This means you may well have a significant impedance that ishigher than the transmission line.

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. s& t' ]* h1 f& K2 c! pFor reference, the self inductance for a few devicesizes: 0402 ~ 0.7nH 0603 ~ 0.9nH 0805 ~ 1.2nH

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To get around high impedance device problems (a majorissue in PCI express due to the nature of link training), we sometimes useso-called reverse geometry devices because the self inductance of the parts issignificantly lower. Reverse geometry is just what it says: An 0402 device hasthe contacts 04 apart, where an 0204 device uses the 02 as the distance betweenthe contacts. An 0204 part has a typical self inductance value of 0.3nH, significantly reducing the effective impedance of the device.


* x. ]: Y( V& ZNow to that discontinuity: it will produce reflections. The further away that reflection, the larger the impact on thesource (and energy loss, see below) within the distance range of 1/2 of the transition time of the signal; beyond that makes little difference.
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At a distance of 1/2 the transition time or furtherfrom the source, the reflection can be calculated using the reflection coefficient equation ([Zl - Zs]/[Zl + Zs]). If the reflection is generated closer such that the effective reflection is lower than this, we have effectively reduced the reflection coefficient and reduced lost energy. Thecloser any known reflection may be situated with respect to the transmitter,the less effect on the system it will have. This is the reason that break-outvias under BGA devices with high speed interfaces is done as close to the ballas possible. It is all about reducing the effect of reflections.


% a, E. E5 }4 r+ d1 F  w/ ]As an example, if I place the coupling capacitor (forthe 2.5Gb/sec link) at 0.1 inch from the source, then the distance equates to a time of 17ps. As the transition time of these signals is usually limited to no faster than 100 picoseconds, the reflection coefficient is therefore 17%. Note that this transition time equates to 5GHz signaling artifacts. If we place thedevice further away (beyond the transition time / 2 limit), and use the typical values for 0402 100nH, we have Z(cap) = 22 ohms, Z(track) about 50 ohms, and wetherefore have a reflection coefficient of about 40%. The actual reflection will be worse due to the device pads.
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xiaoyu19890210

超級狗 发表于 2016-2-7 23:40
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阻抗不匹配對高速訊號的影響是什麼？

傳輸線阻抗大好，還是阻抗小好？

不匹配點離發射端的遠 ...

阻抗变大突变有正反射系数，使得往前传播的信号幅值增加，在接受端接受端看到的是信号上冲，如果阻抗偏大的突变靠近接受端，那接受端的信号边沿可以更陡峭，尤其长距离传输时体现更加明显，有点像信号预加重？如果这个偏大的突变靠近发送端，就会导致这个上冲在信号上升沿延后一点位置，对信号上升沿没有啥帮助。ac耦合电容应该会导致阻抗变大，所以在不考虑接插件等因素，靠近接受端会让信号边沿更好，刚好弥补长距离传输时边沿的退化？
) T; @' P0 G! H这么想对不？纯属个人瞎想，望狗版主指点，要是再能从您的粮仓里刨出点干货就更好啦。

菩提老树

1、一般都是靠近发送端发，但是也有靠近接收端放的，我们经常放在接收端；2 、放在靠近连接器的位置；仅供参考，其实没有多大影响

xiaoyu19890210

菩提老树 发表于 2016-2-4 16:43
$ U9 T5 q8 m  q2 H( {1、一般都是靠近发送端发，但是也有靠近接收端放的，我们经常放在接收端；2 、放在靠近连接器的位置；仅供 ...

+ A! _3 A6 X0 Q: v十分感谢版主的回答，那：
1.靠近发送端或者接受端，而不是中间，为什么？
8 W* A3 E; |& [7 w" \) s2.靠近接插件放置，为什么？

超級狗

AC Coupling
PCI Express signaling requires AC coupling between the transmitter and the receiver. The capacitor value must be between 75 nF and 200 nF. The 0402 package size and 100 nF value are recommended. The AC coupling capacitors should be placed near the transmitter of the device or the connector to minimize discontinuity effects.

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菩提老树

xiaoyu19890210 发表于 2016-2-4 17:12
十分感谢版主的回答，那：
& n- ^  R6 x+ _+ E: [1.靠近发送端或者接受端，而不是中间，为什么？
2.靠近接插件放置，为什么？

2 {1 s0 P" v, a9 z! z0 ^7 \2个问题都没有为什么，只是布线通道的问题和减少阻抗不连续距离的考虑，另外，我都说了位置没有明显的影响。至少从我的项目上来看没有什么影响，无太多理论依据

xiaoyu19890210

超級狗 发表于 2016-2-4 22:40
AC Coupling
$ b5 e6 e% R  n! a# c2 `$ J( ]PCI Express signaling requires AC coupling between the transmitter and the receiver. Th ...

) B6 X2 G7 k. N' D) r# ]2 R多谢超级狗版主，看一些协议或者设计指导，总会有些建议但未给出原因，我就是特别想知道是什么原因，既然给出建议不会是毫无根据的，像这个pcie ac耦合电容，协议中说靠近发送端或者接插件可以减小阻抗不连续对信号的影响，可为什么呢，难道是仿真对比得出这样结论？请原谅我的固执。

xiaoyu19890210

xiaoyu19890210 发表于 2016-2-6 16:59
; O! A. m5 C3 c# z) v& h; Z多谢超级狗版主，看一些协议或者设计指导，总会有些建议但未给出原因，我就是特别想知道是什么原因，既然 ...

发送端breakout和接插件一般情况下都是会导致阻抗变大的突变区域，ac耦合电容一般情况下会导致阻抗变小，难道是因为这个原因要把阻抗变小的突变因素靠近阻抗变大的突变因素以中和阻抗突变的影响？
, v% ]& j0 f- V+ m1 v, d又或者是将阻抗突变的区域进行集中，有利于减少阻抗突变的影响？

超級狗

• 阻抗不匹配對高速訊號的影響是什麼？
• 傳輸線阻抗大好，還是阻抗小好？
• 不匹配點離發射端的遠近有何影響？
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用心思考一下，樓主可以的。

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超級狗

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xiaoyu19890210 发表于 2016-3-9 22:06
阻抗变大突变有正反射系数，使得往前传播的信号幅值增加，在接受端接受端看到的是信号上冲，如果阻抗偏大 ...

& O; H: o& I: ]+ F+ V大哥講得沒錯啦！但可以想得再簡單些。
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反射路徑短的話，反射訊號和發射訊號相位（Phase）差很小，可以視為同一訊號，對原傳送訊號產生的干擾最小。

如果應用上有連接器，那連接器阻抗不匹配的反射是無法避免的。AC 耦合電容靠近連接器，同樣可讓二者的反射訊號相位（Phase）差很小，可被視為一次反射。而不是 AC 耦合電容反射一次，到了連接器又反射第二次。
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僅為小弟愚見！


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xiaoyu19890210

超級狗 发表于 2016-3-9 23:18
大哥講得沒錯啦！但可以想得再簡單些。

: _3 {" T+ W8 T$ u' h7 [- `反射路徑短的話，反射訊號和發射訊號相位（Phase）差很小，可 ...

! x1 p6 E2 f- n2 Z狗版主，您就不要逗我啦，我才是小弟，不对，是小小弟。关于信号反射和相位相关的概念以前没怎么在资料上看过，可否麻烦您从您的粮仓里翻点料出来让小小弟学习学习？万分感谢！

超級狗

僅為小弟愚見！

不是說了嗎？大家一定要這樣搞？

看我被土石流活埋很精彩就對了。

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$ C5 a* P3 F/ ]5 o' A黃金狗大︰

請你們的救難犬待命，如果我明早還沒回來的話，就開始挖吧！
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xiaoyu19890210

超級狗 发表于 2016-3-10 09:16
. x: i. y1 n, w# f- t' v8 i不是說了嗎？大家一定要這樣搞？
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看我被土石流活埋很精彩就對了。

加油，相信您可以顺利刨出来

jacklee_47pn

超級狗 发表于 2016-3-10 09:16
不是說了嗎？大家一定要這樣搞？
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# Y. l0 D7 K: D+ w5 I2 k看我被土石流活埋很精彩就對了。

飓风营救4 (Taken 4)  馬上開演。
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超級狗

PCIe Return Loss

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