|
|
EDA365欢迎您！
您需要 登录 才可以下载或查看，没有帐号？注册
x
做了一个原理图，有个门电路封装时老是报如下错误信息：
( m. _# {+ R' }, N, _, A. a' u, R1 R9 P- d, C% Z+ d
- u; f$ N ?5 } J t+ Y# ^6 V6 I
The mapping of gates in the Component section+ \- L( l9 b; ^; ^, T4 P) v' u
resulted in a gate composed completely of common pins.1 v4 b q2 g$ U. z
That is, all of its pin numbers were found more than once# I, ~4 e- c5 R% }* g$ M
in the Component section. Such a gate is superfluous and' j; c: a6 H6 m& W' R
illegal and must be removed by correcting the Parts DataBase
& k/ U6 @6 w( ~) e. q7 [
. a( N" w. J3 E q& [# r% y6 p4 E0 _% U& u
' ?9 c3 d, [+ ~" _, A5 K6 H求教如何解决？ |
|
/1 
发表于 2014-6-7 16:15
QQ好友和群
QQ空间
腾讯微博
腾讯朋友
微信
收藏
支持！
反对！
楼主