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DATE: 02-07-2014 HOTFIX VERSION: 022
0 K/ H. |' H t$ k& p===================================================================================================================================; d' C/ ], k) V0 i3 H
CCRID PRODUCT PRODUCTLEVEL2 TITLE+ {. O! e, T2 P2 e
===================================================================================================================================: k7 t! ?' H* @; ~/ F% u
192358 ALLEGRO_EDITOR PADS_IN Pad_in does not translate some copper shapes
1 x1 p- f7 w8 {; t3 R7 I222141 ALLEGRO_EDITOR PADS_IN PADS_IN: Extra shapes are created whenimporting PADS design
8 T$ A" `2 q7 C) O) u$ E274314 ALLEGRO_EDITOR PADS_IN PAD_in boundary defined for flooded area be translated DYN
) Y) A0 Z& N6 z% n5 T7 X$ {413919 ALLEGRO_EDITOR PADS_IN pads_in cannot import width of refdes.
' b; [* @) Y5 _- k* u609053 ALLEGRO_EDITOR PADS_IN "Mils to oversize" of "pads in" did not workcorrectly for MM data.
: m8 A' V: g3 I; g" E, E/ m' b666214 CONCEPT_HDL OTHER Option to increase Line thicknessin publishpdf utility
$ t( \4 j" u4 x, k738482 ALLEGRO_EDITOR GRAPHICS Export image creates black image with Nvidia GeForce 8400M GS Graphicscard
D0 y8 [3 U: p+ A2 N1 s982950 CONCEPT_HDL OTHER change the mouse button for thestroke to have same function with in pcb editor
7 N1 s$ h. Y# T; x, L1020886 SIP_LAYOUT LEFDEF_IF a quicker way to promote die pins (byimporting macro_pin list)% w, L4 ^6 E* N" Z# K5 Q
1032678 CIS VIEW_DATABASE_PA View Database Partgives incorrect result in complex design with variants.
) s3 G# d, x+ j0 W" D" t1033864 ALLEGRO_EDITOR PADS_IN pads_in doesnot translates teardropspresent in design# N/ ?4 H6 J1 a. d0 V
1054862 CONCEPT_HDL OTHER Option to increase Linethickness in publishpdf utility1 a7 h* _% U4 i( k3 E/ c
1055252 FSP PROCESS Add a synthesis option to target agroup to contiguous or consecutive banks2 C7 ?) ?: H* o2 v* l& B
1100772 CONSTRAINT_MGR OTHER In Constraint Manager > DRC >Spacing the Show Element DRC totals are wrong.- S' |' }( x% F8 g# r
1135020 CIS DESIGN_VARIANT Variant list is showing wrong results forhierarchical designs
( x; j( `5 i& e& G" Z% m- q% f1 F+ r1138951 SIP_LAYOUT DIE_ABSTRACT_IF Fix die abstract r/w to properly supportpinnumbers on ports
* s8 Q, q6 ]+ `* M7 Q1 B. N5 [1140042 CONSTRAINT_MGR OTHER Diff_Pair lengths and analysis arelost after closing and opening Constraint Manager.! U9 x& d' |4 g: Q% P
1143662 ALLEGRO_EDITOR INTERACTIV Enhancement Request for RMB - Snap Pickto options increased to include Pin edge
( A. Q1 U2 K7 N0 S7 T1 K s1147961 PSPICE SIMULATOR Simulation produces no output data
: }8 c/ h7 ?0 I' I1150874 ALLEGRO_EDITOR PADS_IN Dimensions in PADS are not translatedcorrectly during pads_in translation* }! i0 F! f5 Y \2 T# B' g
1154184 CONSTRAINT_MGR CONCEPT_HDL Difference in the way topology isextracted in 16.3 versus 16.6 G$ v4 r6 h6 J4 T K
1154770 CAPTURE PROPERTY_EDITOR Variant Name property doesn't show value inVariant View mode
3 a) m3 E7 \) |$ Z1158350 CONCEPT_HDL CORE Need a warning Message whileimporting a 16.3 sub-design in a 16.6 Design
' Z# r% B" U) O9 z6 V7 ~; i( r7 y1162347 ALLEGRO_EDITOR EDIT_ETCH Enh- Allow new option in Move commandsuch that it allows stretching etch using only 45/90 degree segments directly6 Y; u5 P) V' h
1165553 ALLEGRO_EDITOR INTERACTIV Subclass list invoked from the statuswindow does not represent correct colors.. B, h3 V* E/ V* a( r( n+ y
1168079 FSP MODEL_EDITOR Clicking OK or Save As in rules editorallows user to overwrite the master with no warning
: Z2 q9 E& \% F3 b* k* v U* Z" s1172043 SCM OTHER : in pin name causes SCM to crash1 w- Q5 a' w/ a8 d
1172207 CAPTURE STABILITY Capture crash while adding new partfrom Spreadsheet
" i8 {8 q. P. p) u6 j( \) k9 o1172743 ADW TDA Allowed character set for thecheck-in comments is too limited, z2 v, ~) D1 K+ J( B
1174099 SIP_LAYOUT WIREBOND Option to reconnect wire based on 縫in name� in the Wire Bond Replace
7 z; e/ Q( J/ _& O2 l% A v1177672 APD IMPORT_DATA Netlist-in wizard didn縯 provide detail information about whatcolumns have been ignored by import process. K; M! o- J5 ]9 z5 ^3 W2 G
1177714 CONCEPT_HDL RF_LAYOUT_DRIVEN RF component's LOCATIONproperty can not be set to invisible- ?4 Q9 o8 X" K- }" h
1177820 CONSTRAINT_MGR INTERACTIV Done the Allegro command when attemptingto launch CM8 K( `+ J4 D8 B: Y# y+ @4 A, ?
1178586 ALLEGRO_EDITOR EDIT_SHAPE Number of digits displayed after thedecimal point of Shape Creation function does not match the Accuracy of BRD y) n! V, r" i5 I( j8 H. I
1179688 PSPICE STABILITY pspice crash for particular HOMEvariable vlaue& w5 i( ^( E4 `4 P) d/ K5 [: j
1179827 SIP_LAYOUT OTHER SiP Layout - Spreadsheet to Symbolexport - enable field to add Keywords for data fields to excell cells
6 y5 C" _& A- J# H. |6 D: b3 `3 F1179879 SIP_LAYOUT STREAM_IF Data file corrupt when exporting Streamdata from SiP database.
7 }& H1 _1 r- |6 T2 {0 r1180164 F2B BOM BOM csv data format converts toexcel formats# { e5 r" u7 R
1180477 ALLEGRO_EDITOR INTERFACES IPC-356 output is listing a duplicatelocation in the comment section
# ]) j h$ G% h1180932 SIP_LAYOUT OTHER SiP Layout - Symbol to Spreadsheetadd option for writing to existing spreadsheet4 c9 t) d( N* O
1181377 ALLEGRO_EDITOR INTERACTIV Pick Releative does not work correctlywith RMB-Move Vertex
3 \" v" ^; l1 l" {4 a8 @1181516 ALLEGRO_EDITOR DRC_CONSTR Getting a "Thru Pin to RouteKeepout Spacing" when there should not be one.! O9 Q0 o+ P+ Z3 Q
1181739 GRE CORE Running Plan > Spatial crashesGRE }5 \; @9 N6 ]8 y9 b+ f
1181935 ALLEGRO_EDITOR DATABASE Enh. Property that allows internal C-CDRC errors
. _; s0 {5 t& e2 e9 t9 b1182185 SIP_LAYOUT OTHER SiP Layout - Import symbolspreadsheet - suppress Family for the font in the XML spreadsheet, M! t, }" ~6 @. t$ V; Y- |
1182566 SIP_LAYOUT OTHER SiP Layout - Spreadsheet to symbol- Enhance ability of spreadsheet exchange to allow for a portion of a full pinmap/ ~6 O; E8 o T
1182599 CONSTRAINT_MGR DATABASE CM Prop Delay Actuals do not updateafter Z Axis option is turned ON or OFF and Analyze is run.
- X d" k5 x& I# L: G1182892 CAPTURE SCHEMATIC_EDITOR Pspice marker rotationbefore placement
$ ^1 u# {4 }/ P9 y3 e `1183682 ALLEGRO_EDITOR DRC_CONSTR Implement Nodrc_Sym_Pin_Soldermask &Nodrc_Sym_Pin_Pastemask to symbol level
* ~0 Q3 b+ b9 R- J. v8 D1185445 SIP_LAYOUT DIE_ABSTRACT_IF Die abstract export needs to be able toselect xda file type when browsing* w5 [" @& }( d1 J# m# |
1185932 ALLEGRO_EDITOR SHAPE Soldermask in solder mask void DRC" L6 _! N, D. ]$ y, X
1185946 CONCEPT_HDL CORE Ericsson perfomance testing report5 sept 2013- Q; K# N7 `. E
1187213 FLOWS PROJMGR Unable to lock the directive:backannotate_forward
9 q) Z! b& m2 ^+ z5 ~1187444 ALLEGRO_EDITOR DRC_CONSTR With this design Database check promptserror "SPMHGE-47: Error in call to batch DRC"
" A! a" A# b1 I5 R6 E- ^# G( Q4 M5 r* A1187597 ALLEGRO_EDITOR DRC_CONSTR No Package to Package Spacing DRC error,when symbol overlap sideways at 45 degree.; `- u5 U: r2 M3 D
1187723 FSP PROCESS Synthesis can fail depending on componentplacement0 o5 k! h& U K# A2 e
1188164 SIP_LAYOUT OTHER SiP Layout - Spreadsheet interfacesImport Export and Add Component - include Keyword for NET_GROUP
$ {: y& m9 F+ o$ N- n1188245 CONCEPT_HDL CORE INFO(SPCOCN-2055): You cannot runthe CHANGE command in a read only schematic
/ a+ x G$ B2 n: J1190927 CONCEPT_HDL CORE Check sheet does not reportshorted signal/power nets if power symbol is connected to a pin8 O7 ~1 u! H% M8 t
1191497 ALLEGRO_EDITOR INTERACTIV ENH: Adding names to the text blockparameters numbers. j' b2 F7 `# }3 I* d
1192005 SIP_LAYOUT IMPORT_DATA Import SPD2 is missing 1 smart metalshape from file8 l7 ^2 \. `* g! {
1192204 ALLEGRO_EDITOR EXTRACT Need ability to extract vias that arelabeled as microvia" F8 Z) N! ?, k7 v ]* j0 Q. S/ }
1193063 ALLEGRO_EDITOR MANUFACT TestPrep log displays "Pin is notaccessible from bottom". The component is through hole.
9 ~& b- ~$ I6 D4 p+ Y1193418 ALLEGRO_EDITOR GRAPHICS 3D Viewer can`t export image in both SPB166S015 and SPB165S0477 U+ o, N( m& i* o' X N, }9 x
1194305 SIP_LAYOUT EXPORT_DATA export package overlay creates file withno package info, M9 b" U1 J. @ c; j
1194418 APD IMPORT_DATA issue when doFile->import->netlist-in wizard3 [* Z& d" ]) k/ ?, n' A9 h
1195279 F2B PACKAGERXL Ptf files are not being read whenpackaging with Cache. v' O I' V* p6 v8 i' S
1195374 ALLEGRO_EDITOR INTERACTIV Modules are not showing up in Tools >Module reports [- |% q1 @* }5 w9 R3 | N) X' F. }
1196603 SIP_LAYOUT EXPORT_DATA Change form for "Write PackageOverlay..." to better support longer lists of routing layers! P& o6 T) t8 {; C! K" |8 u
1197302 CONSTRAINT_MGR UI_FORMS Inconsistancy in selection of objectfor Spacing Constraint Worksheet! {, o# d$ t9 Q; |& _" ~
1197399 CAPTURE OTHER Draw toolbar disappears when usingPrint Preview
5 `: ] |; r) d( I5 V/ R1 K1 U( O1197543 ADW TDA TDO does not correctly showdeleted pages( J' S a4 b+ T+ H f/ x, B( _$ A
1198033 CONCEPT_HDL CORE Signals do not get highlightedwhen Show Physical Net Name is option enabled
2 E+ i/ j, @! F1198468 ALLEGRO_EDITOR GRAPHICS 3D_step model does not show thecorrect view in 3D_Viewer when symbols have multiple place_bounds.
+ U9 C# q% r1 _$ i, S7 D1198617 CIS GEN_BOM Mech parts are showing with Partreference in CIS BOM2 [+ u" u! y7 c4 G9 u
1199764 ALLEGRO_EDITOR SHAPE Allegro crashes when trying todelete small island on POWER layer.
3 _. {9 ~& s& F5 a0 H1200232 ALLEGRO_EDITOR INTERACTIV Moving all items including board outlinewhich is made of lines does not move the board outline in General Edit Mode. h4 I; c. z: B' Y k
1200748 ALLEGRO_EDITOR INTERACTIV Additional pin edge vertex object tosnap pick
X' e8 l6 T L; ~! y1201056 ALLEGRO_EDITOR DATABASE Unsupported functionality strip designcreates a .SAV file
% w+ P% o3 ]' [! G. e8 d* _1201638 CIS PART_MANAGER Part retains previous linking inside thesubgroup
: a/ g; i* ~: \2 \* w. N, t1201834 ALLEGRO_EDITOR PLOTTING Bug: Import Logo command changesresulting imported object3 h: c# S% m; `) k6 p4 a2 O0 `% J
1202406 SIP_LAYOUT OTHER enable the dynamic display of componentpin names for co-design dies in Sip Layout1 U6 D& y" D |- S6 K
1202431 CONCEPT_HDL PDF The publishpdf -variant optionshould have a "no graphics" option
% r" p1 v2 E) T1202717 ALLEGRO_EDITOR DATABASE About Warning(SPMHA1-108):Illegal linesegment ... end points.1 r" v# s" k' a( A# ~( A' a% ^
1203459 CONSTRAINT_MGR INTERACTIV Object Report has no mechanism to outputinformation for a specific design." B5 y6 r/ {, ] h9 ]
1204544 F2B DESIGNVARI Variant Editor does not warn on save ifno write permissions are on the file
# a9 F# g& \1 P0 B) f% [% _) x1205500 FSP CONSTRAINTS MAPP FSP FPGA port mapping VHDLsyntax
( \% O4 X' }2 O1205952 ALLEGRO_EDITOR GRAPHICS Step Model for Mechanical Part isvisible in 3D viewer only when Etch Top Subclass is enabled! T8 j6 s& `- f6 f7 J6 M
1206103 SIP_LAYOUT IC_IO_EDITING add port name property to pins, and addSkill access I/O driver cell data
8 B0 u! A# P8 Q% U, K7 k& _1 q1206546 CAPTURE ANNOTATE User assigned refdes are resettingwhen 緼nnotation type� is set to 縇eft-Right� or 縏op-Bottom�, ]; }5 z/ y* R: K9 u0 p% O
1206561 ALLEGRO_EDITOR GRAPHICS Not all mechanical symbols made with Stepfiles are displayed in the 3D View4 F8 j7 V2 R4 O/ w1 |
1207125 SIG_INTEGRITY ASSIGN_TOPOLOGY ECSet mapping wrong for 2 bit in a 4bit bus
9 N! H, n8 P7 D1207386 CAPTURE GENERATE_PART Altera pin file not generating the partproperly( V3 O( v; t8 H4 t
1207629 CAPTURE TCL_INTERFACE Bug: GetMACAddresses tcl command notworking
0 m$ `- I8 B' `2 F" C/ p8 x' z1207994 CAPTURE TCL_INTERFACE TCL pdf export in 16.6 fills DOT type pinswith black color
' u+ M: x# a( Y# A" [! f1208017 F2B DESIGNVARI sch name is not same when updatingSchematic View while backannotating Variant
% Y4 d. Y" A+ W7 x1209363 ALLEGRO_EDITOR INTERFACES When placing pins using the polarcommand the tool returns 4500.00 for 45 degrees.
% w+ P0 h( N: l7 T, Z& R% Y1209769 CONCEPT_HDL CORE Top DCF gate information missing
2 Y2 A/ U5 M" H1210194 CONCEPT_HDL CONSTRAINT_MGR HDL crashes with Edit Via List dialog box& F s/ H+ K4 c! P1 v: K
1210442 CONCEPT_HDL INFRA Save design givesERROR(SPCOCN-1995): Non synchronized constraint property found in schematicpage
. c+ t0 g9 U$ c1210685 ASI_PI GUI User can't edit padstack inPowerDC-lite
% a+ t( n3 Q6 Y0 |, D1210744 SIG_INTEGRITY SIGWAVE SigWave: FFT Mode Display unit seemsnot to be correct
+ W% N3 _* X _3 Q8 Y, i: K$ }1210829 CAPTURE NETLIST_VERILOG Shorted port is missing from verilog file
! R# z! h7 d0 `3 M4 u0 L" R1210850 CONCEPT_HDL CORE DE-HDL backannotation crashingafter instantiating specific cell from Ericsson BPc Library. Z# B, B, |/ H: w( p+ e1 K
1211620 ADW COMPONENT_BROWSE Component BrowserPerformance5 R9 O9 m/ k$ f( p3 S2 z2 L0 ]
1212102 ALLEGRO_EDITOR INTERACTIV Shape edit boundary adds arc mirrored tothe highlighted preview.; b3 W2 n4 c' m/ Q
1213294 CONCEPT_HDL SECTION DE-HDL windows mode multiple section fails tosection first contactor pin from column of individual pins
; A: H% g/ k9 r; v- P. ~( q3 u; W1213402 APD DATABASE The old "ix 0 0" fix is now causing the features to lose netsentirely.
9 b. N1 {1 c2 r% b' y) Q, f1 T4 j1213694 ALLEGRO_EDITOR PARTITION Via connected to Dummy Net pin in Partitiongets connected to shape on the board after importing partition
; [. F! W& G* o- O, o5 j1214247 CONSTRAINT_MGR UI_FORMS Selecting the "All" folderin Spacing Constraints in CM does not automatically select the first column forediting( M F6 `. {( y. T. `, `
1214320 SIG_INTEGRITY SIGNOISE signoise command with -L and -k option
0 D6 e9 o) m+ F$ p: a0 l* a; s+ X7 B1214433 CONCEPT_HDL CORE Genview does not update sym_1 withports added to the schematic
8 \$ E9 P& o" E1214909 ALLEGRO_EDITOR NC NC Drill Legend show extra rowsfor drills
. t% d; O! @# b* C" {3 k1214916 SIP_LAYOUT OTHER package design integrity check forvia-pin alignment with fix enabled hangs! @ b r# w$ K8 t4 J, `8 J1 H( {
1215954 SIG_INTEGRITY SIMULATION Cycle.msm does not exist error whensimulating extracted net
: w4 \9 h: j* X7 ~# U1216328 CAPTURE STABILITY Capture crash
; G0 g' @: l" }1216993 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crash on SPB16.50.049
1 D$ x' ?5 w' e; y8 f1217450 F2B BOM ERROR 233: Output file path doesnot exist/ g( I7 Z( H0 K3 H1 v# P9 ], S8 E/ J8 z
1217612 ALLEGRO_EDITOR INTERACTIV Replace padstack will not replacepadstacks that have multiple alphabetic characters in the pin name - AB21-AB37' F# [# Y5 e! c0 I( k4 U6 M$ Q: t3 C
1217823 ALLEGRO_EDITOR INTERACTIV Compose shape fails with SPMHIS-473
* @/ f6 k) Z2 F2 Y; p( X; y1217887 ALLEGRO_EDITOR INTERFACES An undo option to be made available inthe STEP Package Mapping window6 r- L& `- b8 b- m4 _
1218665 ALLEGRO_EDITOR INTERFACES In step viewer, the bottom side partsare placed above the pcb board surface
! Y3 ^( T: e; I" |) U% L' |1219053 PSPICE PROBE PSpice crash with the attachedDesign4 a4 L. p; r1 b# ]( r; u) ]! q
1219067 ALLEGRO_EDITOR EDIT_ETCH dynamic fillets behavior is unstable( v' P. f$ U0 ?+ |* t+ T
1219095 ALLEGRO_EDITOR MANUFACT Design Cross section chart is taperedfor two layer board
* S6 W' R0 v3 @! t- a% g/ E1 L1219126 ALLEGRO_EDITOR SKILL Skill issue with axlRefreshSymbol(). t5 ?/ ?7 F* _3 `
1220701 ALLEGRO_EDITOR INTERACTIV View > Windows > Worldview(showhide view command) fails with command not found9 W8 w1 M' n; h1 }
1221057 ALLEGRO_EDITOR REPORTS Units in Cross section report forspacing is not synced with the design! F: c; f# w, `$ e* e
1221139 ALLEGRO_EDITOR EDIT_ETCH Delay tune is not tuning differentialpair* G% d% d& @3 ^/ @
1221157 SIP_LAYOUT IMPORT_DATA import spd2/na2 file is not importingdata correctly into sip" |2 C* s! C( p. U- U
1221163 SIG_INTEGRITY GEOMETRY_EXTRACT Simulation aborts withsevere convergence issue when coupled vias is enabled.2 p! J% Q) O' a3 j. e A. V7 R
1221416 ALLEGRO_EDITOR DATABASE strip design for function type
" A9 `* f' b1 _" C1221931 ALLEGRO_EDITOR DATABASE Fatal software error when embeddingcomponent
. ]/ K/ f! T V7 e/ k- s# o. c1222105 CONCEPT_HDL CORE Moving Pins around the edge of aBlock causes the text of the pin to change its text size.7 h! r( p# o, h) L! k
1222124 APD DATABASE Same Net DRC's exhibiting inconsistentbehavior.' z3 ?4 |6 ]0 \
1222272 SIG_EXPLORER EXTRACTTOP Cannot extract net or open SigXplorerafter selecting a netgroup2 l0 F# H" p7 ` k+ Q/ H0 _ a) [
1222329 ALLEGRO_EDITOR SHAPE STEP-Model Symbol which has place bound bottom is on Top1 o& T4 H" v/ C( O7 ~
1223183 SIP_LAYOUT BGA_GENERATOR Getting an incorrect error message whenusing the BGA generator with a long BGA name.
& C* K6 O. h8 U% N3 q1223662 ALLEGRO_EDITOR REFRESH Allegro crashes when trying torefresh symbol1 R) ]4 | N- `* `$ w# O4 C; a
1223932 CONCEPT_HDL CORE DEHDL block desend does not find1st page if its not page1
, F% c7 g9 B; f9 ?/ x1223940 CONSTRAINT_MGR UI_FORMS Unable to change CLOCK name inSetup/Hold Worksheet under Timing in CM.
( A; Z7 q$ Q, i1 G2 w1224127 SIG_INTEGRITY IRDROP Is the old static IRDrop in 16.6officially supported?* u& Y/ e; ?8 }6 }0 m/ _
1225492 PCB_LIBRARIAN CORE PDV expand vector pins resizessymbol outline to maximum height again# }) s3 G& `; p
1225546 CONSTRAINT_MGR ECS_APPLY nets where the referenced ECS mapscorrectly in constraints manager for front end but not in back end
! R3 |: r# k" F4 t1 I: ]/ n1226405 ALLEGRO_EDITOR INTERFACES File > Export > IDF ask for filterconfig file eventhough it is created in same session and stored in parent folder) V' T7 H: [3 n A2 D
1226448 PDN_ANALYSIS PCB_STATICIRDROP License failure about PDNAnalysis with XL and GXL
V, r7 i2 `' l4 l1 I0 ~" z1228721 SIP_LAYOUT OTHER File Export Netlist Spreadsheetenhance sort to be a natural method per Jedec according to customer |
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发表于 2014-2-10 15:09
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