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各位大神,以下是截取书里第十三章里的某一部分的内容。在下不明其箇中含义,还望指点一二。. P& y/ U% c9 V I# ]
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Chapter 13 The Power Distribution Network7 z; P# G' W+ ?" v2 c' B1 q) [0 O
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The loop inductance of the package leads in the power/ground distribution path is in series with the pads of the chip to the pads on the circuit board. This series inductance creates and impedance barrier.(还能理解)
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: M8 f! q2 t" x$ D( ]- nFor example, at 100MHz, the impedance of a 0.1nH inductor is about 0.06 Ohm. Even if the impedance of the PDN on the boards was implemented as a dead short, the chip, looking through the package, would see a PDN impedance at 100MHz of 0.06 Ohm. Of course, this is why on-die and on-package capacitance is so important.(什么叫做impedance of the PDN on the boards is dead short?即便把板机的PDN给短路了,芯片还是能侦测到封装的0.06欧姆... 这到底是什么意思啊?短路了板机PDN当然即只剩下封装的阻抗不是吗???)
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When the interactions of the on-die capacitance are added to the package inductance, the behavior is even more complicated. Figure 13-17 shows the impedance profile the chip sees looking into a board that has a short for the PDN. The impedance profile is limited by the package inductance.(这个好理解,亦即是封装的阻抗主导了整体的impedance profile。但是不是在不考虑板机的境况之下??)
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. N E% i+ ]- AThis suggests that no matter what the board level PDN does, it can never reduce the impedance the chip sees below the package lead impedance. When the package equivalent lead inductance is 0.1nH, the board cannot influence the impedance the chip sees to below 10mOhms at frequencies above 10MHz. (为何不能影响芯片所看到封装的阻抗值??如果我在板机加一个大容量的电容1000uF不就能把反共振频率推往低频率点,并且降低整体阻抗吗??)
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TIP When establising the design goals of the board level PDN, the high-frequency limit to where the board level impedance can be effective to the chip is set by the frequency at which the impedance from the combination of the package leads, board vias, and spreading inductance exceeds the target impedance.(我可以推论说上限频率是可变的吗?亦即是只要我加足够大的电容,上限频率就会跟着往左移动??). z, R3 P% P0 a1 v1 `' b
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真心求教! |
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