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本帖最后由 pzt648485640 于 2013-10-16 22:11 编辑 9 A1 o( A3 A6 h# G: g
' ^9 {+ L0 h0 k* Z8 _下载地址：http://pan.baidu.com/s/1kmHkL
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百度网盘 在hotfix附录里% s# y% c* I/ r* B
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DATE: 10-10-2013 HOTFIX VERSION: 0179 q" I7 n' V; K+ J8 F2 O
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===================================================================================================================================5 j% h, O" Q9 A) Z" B
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735992 ADW LIB_FLOW Create Test Schematic does not use the correct package type2 J( u* ^+ l3 X' D, o
5 O3 f, G9 s* D7 e' V. J1121403 FSP PROCESS "Assign to Pin" not getting obeyed by Synthesis.) B: ]% e. D8 o
" r" @( f- N& ?; ~1 [1141844 RF_PCB DISCRETE_LIBX_2A ADS Lib Translation Pin Soldermask/Pastemask missing% @' m9 `" D& s+ r: b
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1169269 ALLEGRO_EDITOR DRAFTING Dimension placed on package symbol moves to different place when it is placed on brd file.
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1170488 ALLEGRO_EDITOR MANUFACT Dimension text(on .psm) move to different position, when it is placed on .brd.9 [, x! d0 a" F) U' W* b
( i S' t) [1 Y c; P1173345 CIS CRYSTAL_REPORTS Crystal Report - Display Parameter dialog for export option2 b# K2 x T, [, S7 O7 W! ^
% g! U& Q8 C8 p: U. T1181759 SCM LVS SCM Crash when doing update all that executing import physical command.' y) Z5 p: F! T* `
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1182499 ALLEGRO_EDITOR OTHER Step export to include through hole padstacks (all pins and via) drill.* B8 u y7 k, t. p* n: u
4 w4 v2 F4 ~5 d" r/ c$ g- P1184682 CONCEPT_HDL CONSTRAINT_MGR Net Constraint not transferring to layout from schematic+ b$ ~+ S* V* y3 F _2 h, W" e; m
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1185524 F2B PACKAGERXL Enhancement User would like notification of pack_short in pxl.log* E7 j4 S) a [
. o, _- E: n% I8 S1185902 ALLEGRO_EDITOR SHAPE Update shapes dont clear some diffpairs in HF15# `# L, p5 \2 ^2 d
4 T( x. n4 F- t7 P0 a1186152 ADW LRM Part Status for Deleted Part in LRM is distinguished with other part status
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1186387 ALLEGRO_EDITOR OTHER DXF cannot catch offset value in s047 hotfix.7 R; ]$ ?: A' Q
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1186805 ALLEGRO_EDITOR OTHER Exported STEP file missing multiple components placed on board
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( D) {1 Q Y0 T T1186818 ALLEGRO_EDITOR COLOR Custom color not retained during dehilight
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1187196 CONCEPT_HDL CORE TOC not populating (page 1)/ Q2 u8 f/ S, b: u$ P7 f
7 w7 Q. ~( M+ A8 L1187667 F2B PACKAGERXL Existing hard LOCATION property in drawing was left unchanged! E" d7 D# J' M3 E: W5 F% T4 s/ ]& w2 |
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1188264 ALLEGRO_EDITOR MODULES Some fillets not regenerated in module created from a board file.
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1190144 ALLEGRO_EDITOR OTHER Fillet shape is not genrated around cline
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1190210 F2B BOM The bomhdl.exe fails - MFC Application has Stopped Working
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: ?/ J2 c4 j/ V0 p1190618 ALLEGRO_EDITOR GRAPHICS Enhancement for Visible grid& @8 b# y% E" e% J
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1190813 ALLEGRO_EDITOR INTERFACES 3rd party netlist file in TEL format fails syntax check but imports successfully- n( B, I( D: c7 F
' V- U+ Z- N8 z b5 c4 K- H1190895 ALLEGRO_EDITOR EDIT_ETCH Route delay meter displays violation when sliding diff pair
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|4 @9 l u% K( b. ^; A9 ?5 U1190908 F2B OTHER DE-HDL aborts if dummy net is being cross-probed from PCB Editor( l. l% g, n/ `* |3 f3 N) @
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1190990 CONCEPT_HDL CORE Mismatch in .csa and .csb files
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0 `$ q' V8 M/ b! \/ I/ ^1191008 CONCEPT_HDL CORE Remove Binary File feature doesn't work
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1191514 SCM PACKAGER Packaging error PKG-100" [1 B7 d% e1 C. G0 N! C
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1191517 ALLEGRO_EDITOR DRAFTING Metric +tolerance when using dual dimensions is not displayed correctly' |$ y/ v1 p% i* I! ?3 S9 f ]# a
- [$ i, q2 {" {8 \2 y5 r* D1192561 ALLEGRO_EDITOR GRAPHICS Padstack with offset is not showing correctly in the 3D Viewer.
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7 g: Q- m7 k8 X" ^* K. H( W1192916 ALLEGRO_EDITOR EDIT_ETCH Wrong static phase values are shown in the dynamic timing meter for certain Diff pairs compared to CM.
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1194197 ALLEGRO_EDITOR OTHER Step export to include through hole padstacks.
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, T" d' ]( r5 D1194239 PSPICE DEHDL Associate Model does not launch from DE-HDL
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1194736 PSPICE SIMULATOR Design causes RPC failure when run consectively
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! J- e6 q- d/ p" _7 D4 }: X1195139 ALLEGRO_EDITOR PLACEMENT Components disappears from board file once they moved: \( o/ F; [* z( o
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发表于 2013-10-15 10:33
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