Hotfix_SPB16.60.013_wint_1of1

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Cadence SPB16.6下载(Hotfix013已发布)

Cadence SPB16.6已经推出，需要的朋友可以点击下面的链接下载：
http://dl.vmall.com/c0ych9k8m3
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DATE: 07-26-2013  HOTFIX VERSION: 013
7 p: u1 y, `% y" Q& M===================================================================================================================================
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
===================================================================================================================================
111368 CAPTURE        CORRUPT_DESIGN   Capture - will not produce allegro netlistwith 10.0
5 d, O" i. r( `2 W134439 PD-COMPILE     USERDATA         caCell terminals should be top-levelterminals
" w8 Q8 [" y& b! D: H3 G186074  CIS            EXPLORER         refresh symbols from lib requires youto close CIS
2 t% h% L$ n, ^3 v583221 CAPTURE        SCHEMATIC_EDITOROption to have the Schematic Page Name as a Property in the Titleblock
5 Q* N- h3 D* d  F591140 CONCEPT_HDL    OTHER            Scale overall output size inPublishPDF from command line
801901 CONCEPT_HDL    CORE             Concept Menus use the same key"R" for the Wire and RF-PCB menus
. P6 x2 Q+ p% T* P6 H5 p8 J+ _813614  APD            DRC_CONSTRAINTS  With Fillets present the "cline toshape" spacing is wrong.
881796 ALLEGRO_EDITOR GRAPHICS        Enhancement request for Panning with Middle Mouse Button
887191 CONCEPT_HDL    CORE             Cannot add/edit the locked property
911292 CONCEPT_HDL    CORE             Property command on editing symbolattaches property to ORIGIN immediately
( N+ y) z6 i6 F+ j9 l0 j$ h987766  APD            SHAPE            Void all command gets result as novoids being generated on specific env.
1001395 SIP_LAYOUT    ASSY_RULE_CHECK  Shape Minimumvoid check reports lots of DRCs which are not necessary to check out.
1030696 ALLEGRO_EDITOR INTERACTIV       Enh - Allow another behavior of PANmovement using middle mouse in Allegro
; y6 H$ ]: Z& C$ T; c1043856 ADW           TDA              Diff between TDOand DE-HDL Hierarchy Viewer is confusing to the user
1046440 ADW           PCBCACHE         ADW: ImportSheetis not caching libraries under flatlib/model_sym when the source design is notan ADW project
1077552 F2B           PACKAGERXL       Diff Pairs get removed when packing withbackannotation turned on
1079538 F2B           PACKAGERXL       Ability to blockall 縮ingle noded nets� to the board while packaging.
6 B4 y8 M3 C  |' ^4 N3 I. V1086362 ALLEGRO_EDITOR SHAPE            Enhancement request to autovoid a viaif shape cannot cover the center of the via.
1087958 PSPICE        MODELEDITOR      Is there anylimitation for pin name definition?
$ V1 ^1 C" [+ A* H' ?) i1087967 CIS           UPDATE_PART_STAT Update part status window shows incorrect differences
1090693 ADW           LRM              LRMauto_load_instances does not gray out Load instances Button
8 \' B! C8 ?+ V1097246 CONCEPT_HDL   CORE             ConceptHDL -assign hotkeys to alpha-numerical keys
1099773 CONCEPT_HDL   CORE             DE HDL goes intorecursive loop if a custom text locked at site level is deleted from Tools >Option
1100945 SCM           SCHGEN           SCM generatedDE-HDL has $PN placement issue
1100951 PSPICE        SIMULATOR        Increasing theresolution of fourier transform results in out file
1103117 RF_PCB        FE_IFF_IMPORT    Enh- Allow theAllegro_Discrete_Library_to_ADS_Library_Translator to output in its originalunit
) G% D* ]2 G) B" F1105473 PSPICE        PROBE            Getting errormessages while running bias point analysis.
1106116 FLOWS         PROJMGR          view_pcb settingchange was cleared by switching Flows in projmgr.
( o- P+ M% F# ?- V1106298 ALLEGRO_EDITOR INTERACTIV       Copy Shape uses last menu pick locationas origin and not the Symbol Origin as specified in Options.
1106626 CONCEPT_HDL   CORE             Concept HDL crashes when saving pages
1107086 ALLEGRO_EDITOR INTERACTIV       manual void with arc's goes in wrongdirection during arc creation
1107172 CONCEPT_HDL   OTHER            Project ManagerPackager does not report errors on missing symbol
1108193 CONCEPT_HDL   CORE             Using theleft/right keys do not move the cursor within the text you're editing
1108603 PCB_LIBRARIAN VERIFICATION     PDV ToolsVerification > View Verification (CheckPlus) leaves<project>.cpm_tmp.cpm
5 ]0 b7 J! J9 |2 Z  j" q1109024 CIS            OTHER            OrCad performance issue from Asus.
* D2 G4 B& p: \3 D$ K3 @1109109 CAPTURE       NETLIST_ALLEGRO  B1: Netlistmissing pins when Pack_short property pins connected
* L- _$ M, [9 p# d$ N, b1109466 ALLEGRO_EDITOR ARTWORK          Artwork create some strange gerberlines for fillet.
8 {' s, N0 p+ |3 k8 y1109647 SIP_LAYOUT    DEGASSING        Shape degassingcommand enhancement - control over what layers are counted in even/odd layersets.
1109926 CONCEPT_HDL   CORE             viewing a designdisables console window
9 e! W* S- u, S( e  a, S1110194 SIP_LAYOUT    WIREBOND         If OpenGL settings for display ofdynamic net names is enabled, should be visible while push/shove wirebonds.
1112357 SIP_LAYOUT    WIREBOND         wirebond commandcrashes the application
- e$ N/ n! B. c$ A2 S) m# E- z1112395 CONCEPT_HDL   CORE             縗BASE\G� for global signal is not obeyedafter upreving the design to 1650.
1112658 CAPTURE       PROPERTY_EDITOR  Changing Part 縂raphic� value from property EditorChanges Occ refdes values to instance
1112662 CAPTURE       PROJECT_MANAGER  Capture crashesafter moving the library file and then doing Edit> Cut
. P: {, X9 J/ S/ O/ R9 c* ?7 K5 w1113177 PCB_LIBRARIAN CORE             Pin Shapes arenot getting imported properly
& s6 y. k& H7 ?7 I' H' q! g1113380 ALLEGRO_EDITOR INTERACTIV       Change layer to - option for packagetype .dra is not available in 16.6 release
8 Q9 q: d4 n# ?! E1113656 SIP_LAYOUT    WIREBOND         Enable Changecharacteristic to work without unfixing its Tack point.
1113838 SIP_LAYOUT    DIE_ABSTRACT_IF  probe pinsdefined in XDA die abstract file are added with wrong location
! O' ^% X, A) Y5 t0 d9 `5 U% `1113991 CAPTURE       GENERAL          Save Project Asis not working if destination is a linux machine
# Q  ~' h, @- B4 E+ Q1114073 APD           DRC_CONSTRAINTS  Shape voidingdifferently if there are Fillets present in the design.
9 ~# f, R6 G9 Z) N- B1114241 CAPTURE       SCHEMATIC_EDITOR Port not retaining assigned color, when moved on theschematic
- H. P2 s; n4 \4 H/ I" ^4 _1114442 PSPICE        PROBE            Getting Internalerror - Overflow Convert with marching waveform on
1114630 CONCEPT_HDL   ARCHIVER         Archcore failsbecause the project directory on Linux has a space in the name
. _5 k9 V! s/ }) K1114689 CONCEPT_HDL   CORE             Unknown projectdirective : text_editor
1114928 F2B           PACKAGERXL       縀rror (SPCODD - 5) while Export Physical even afterchange pin from A<0> to A
1116886 CONCEPT_HDL   CORE             Crefer hyperlinksdo not work fine when user use double digits partitions for page Border.
1118088 ALLEGRO_EDITOR EDIT_ETCH        Should Plan accurate and Optimize beremoved in 16.6?
1118734 APD           EDIT_ETCH        Multiline routingwith Clines on Null Net cannot route in downward direction
% z+ }  s1 H7 U- \9 a0 s1118756 ALLEGRO_EDITOR SHAPE            Shape clearance parameter oversizevalues getting applied to Keepouts
1119606 CONCEPT_HDL   MARKERS          Filtering two ormore words in Filter dialog box
1119707 CONCEPT_HDL   CORE             Genview does not use site colors when gen schfrom block symbol
. }  a% z2 F2 K1119711 F2B           DESIGNSYNC       DesignDifferences show Net Differences wrongly
1 K# c0 U. E6 T- y: v1120659 CAPTURE       PROJECT_MANAGER  "Saveproject as" does not support some of Nordic characters.
$ s5 X0 _4 k! ?. p0 ], W3 b0 \3 y9 N' D1120660 CONCEPT_HDL   CORE             Save hierarchysaves pages for deleted blocks.
+ |( m3 }: k6 |4 K" x1120817 SIP_LAYOUT    SYMB_EDIT_APPMOD Rotate Pads commands not working while in the SymbolEdit App. mode
9 ~: L* s# d/ x& U1120985 PSPICE        MODELEDITOR      Unable to importattached IBIS model
. q9 H: g, N* B1121171 CONCEPT_HDL   CREFER           PNN and correctproperty values not annotated on the Cref flat schematic
" _8 N6 ^6 q- D) m+ x1121353 ALLEGRO_EDITOR INTERACTIV       Local env setting will change aftersaving and reopening.
5 [& ~1 S- D  }3 v( n1121382 ALLEGRO_EDITOR INTERACTIV       Undo command is limited to two for thisdesign
2 N1 a% @: d4 H( m; z1121540 F2B           PACKAGERXL       pxl.chg keepsdeleting and adding changes on subsequent packager runs
1121558 ALLEGRO_EDITOR MODULES          Unrouted net and unrouted connectionwhen module is placed of completely routed board file.
& J: m- w  V8 z  j8 y7 t1121585 ALLEGRO_EDITOR OTHER            Drill Hole to Shape Same NetSpacing with Dynamic Shapes shows wrong result.
" @5 H6 t: [, x) k1121651 CAPTURE       SCHEMATIC_EDITOR "PCB editor select" menu option is missing
# O% s4 H' i: C+ F, J2 K1122136 SIP_LAYOUT    PLACEMENT        Moving acomponent results in the components outline going to bottom side of the design.
9 [% f! ?5 `: P- M; |# M1 g1122340 CAPTURE       NETLIST_ALLEGRO  Cross probe ofnet within a bus makes Capture to hang.
. D8 o' M& B/ @$ u5 R/ ]1122489 CONCEPT_HDL   OTHER            Save _Hierarchycausing baseline to brd files
+ d, E1 u1 W7 x! }* V* k/ \1122781 CONCEPT_HDL   CORE             cfg_package isgenerated for component cell automatically
1122909 CONCEPT_HDL   CORE             changing versionreplicates data of first TOC on 2nd one
: u3 F/ _5 e) i5 s4 q1 N* w) K! J+ A1123150 CONCEPT_HDL   CORE             property on yaxis in symbol view was moved by visibility change to None.
+ P+ j# K+ k. [1 s9 t! s: g1123176 ALLEGRO_EDITOR UI_FORMS         Negative values for pop-up location isnot retained with multiple monitors (more than 2)
1123815 ALLEGRO_EDITOR GRAPHICS         Embedded netname changes to a differentnetname
& A& \1 Y+ S9 `' ~1124369 ALLEGRO_EDITOR INTERACTIV       Sliding a shape using iy coordinate doesnot work indepedent of grid.
1124544 CONCEPT_HDL   CORE             About SearchHistory of find with SPB16.5
/ j* b) Y8 D$ C8 V) i5 I1 Q: N$ Z1124570 APD           IMPORT_DATA      When importingStream adding the option to change the point
  S& y! S  J* q  M8 _: \0 y- Y1125201 CONCEPT_HDL   CORE             Connectivityedits in NEW block not saved( lost) if block is created using block add
$ a( I: @9 P1 n, {7 A1125314 ALLEGRO_EDITOR INTERACTIV       Enved crash during setting of library paths inuser preference
1125366 CONCEPT_HDL   CORE             DE-HDL crachesduring Import Physical if CM is open on Linux
1125628 CONCEPT_HDL   CORE             Crash on doingsave hierarchy
1130555 APD           WIREBOND         Wirebond Import should connect to pinsof the die specified on the UI.
1131030 PSPICE        ENVIRONMENT      Unregistered iconof Simulation setting in taskbar
. r- D1 j9 J+ s. E+ d+ g1131083 ALLEGRO_EDITOR INTERACTIV       Bug: 16.6 crash in changing the mode inFind filter window
, I3 a: E! ?6 |; L4 a7 r1131226 ALLEGRO_EDITOR PLACEMENT        When Angle is set in design parameterswhile placement component is rotated but outline is not.
; t( c( ~/ s1 P1 N1131567 CONCEPT_HDL   OTHER            Lower case valuesfor VHDL_MODE make genview use pin location to determen direction.
1131699 PSPICE        PROBE            Probe windowcrash on trying to view simulation message
1132457 CONCEPT_HDL   CORE             The schematicnever fully invokes and has connectivity errors.
0 s5 L) Y! a4 I9 X) k1132575 CONCEPT_HDL   CORE             2 pin_name weredisplayed and overlapped by spin command.
1 e% U+ j* G+ p6 t8 m1132698 ALLEGRO_EDITOR EDIT_ETCH        Slide Via with Segment option with newSlide command
1132964 ALLEGRO_EDITOR SHAPE            Same net "B&B via toshape" errors created when adding shape
1133677 CONCEPT_HDL   CORE             Cant delete norreset LOCATION prop in context of top
/ u2 M% W; m+ m2 g8 h/ I1133791 CONCEPT_HDL   CORE             Cant do textjustification on a single selected NOTE in Windows mode.
/ e, O  K1 m: t# ]+ G. S1134761 CONCEPT_HDL   CORE             Why does MousePointer/Tooltip display LOCATION instead of $LOCATION property
8 V% |! n/ }! ~1135118 ALLEGRO_EDITOR INTERACTIV       Mirror and other editing commands aremissing for testpoint label text in general edit mode.
6 h$ P3 i* b  l0 ~1136420 CAPTURE       GENERAL          Registrationissue when CDSROOT has a space in its path
1136808 PSPICE        STABILITY        Pspice crashmarker server has quite unexpectedly
) M4 f( [2 j2 }1136840 CAPTURE       SCHEMATICS       Enh: Alignment oftext placed on schematic page
1138586 ADW           MIGRATION        design migrationdoes not create complete ptf file for hierarchical designs
7 q( t$ F1 z$ @$ E; r4 }7 q1139376 CONCEPT_HDL   CORE             setting wirecolor to default creates new wire with higher thickness
  _0 a* ]) L+ x  K4 i1140819 APD           GRAPHICS         Bbvia does notretain temp highlight color on all layers when selected.
1141300 CONCEPT_HDL   CORE             DE HDL hier_writesave hierarchy log reports summarizes Successfully saved block x while blockwas skipped
+ W7 f6 E. O* U2 D% a1 D$ |" _1141723 ADW           PURGE            purge commandcrashes with an MFC application failure message
: n# |  M4 W4 D+ v/ \  D1143448 CAPTURE       GENERAL          About copy &paste to Powerpoint from CIS
6 n( h. w6 e! _4 }+ F1143670 SIP_LAYOUT    OTHER            Cross Probingbetween SiP and DEHDL not working in 16.6 release
/ m1 ]) r; _4 ?- E1143902 ALLEGRO_EDITOR DATABASE         when the shape is rotated 45 degreesthe void is moved.
  l9 u6 ~* n# Z$ A( p) g1144990 PCB_LIBRARIAN CORE             PDV expand &collapse vector pins resizes symbol outline to maximum height
3 M. H" l0 M- s: D4 a4 o; r1145112 CONCEPT_HDL   CORE             Warning message:Connectivity MIGHT have changed
1145253 CONCEPT_HDL   CORE             Component Browseradds properties in upper case
4 ], G4 m2 u$ z  Y+ |, L/ }1146386 ALLEGRO_EDITOR INTERACTIV       Place Replicate Create add Static shapewith Fillet shape
1146728 F2B           PACKAGERXL       DCF with upperand lower case values on parts causes pxl to fail
/ T* T/ f4 D7 k0 W4 Q; _1146783 ALLEGRO_EDITOR INTERFACES       Highlighted component is missing fromexported IPF file.
5 Z0 S0 U7 e, C. Q* B/ M1147326 CONCEPT_HDL   CORE             HDL crashes whentrying to reimport a block
! [4 s9 V8 D8 G9 D; p! i: h1148337 CAPTURE       ANNOTATE         Checking "refdes control" isnot giving the proper annotation result
  _2 }: K4 c1 _& x3 ], g/ e9 V1148633 SIP_LAYOUT    INTERACTIVE      Add "%"to the optical shrink option in the co-design die and compose symbol placementforms
1149778 CAPTURE       SCHEMATICS       Rotation of pspice marker before placementis not appropriate
: T5 f& f: u3 h1149987 PCB_LIBRARIAN PTF_EDITOR       Save As pushingthe part name suffix into vendor_part_number value
1151748 ALLEGRO_EDITOR OTHER            If the pad and cline are the samewidth don't report a missing Dynamic Fillet.
1152206 CONCEPT_HDL   CORE             ROOM Propertyvalue changes when saving another Page
9 Z# [6 q+ y' E3 ]; I. ~2 g1152755 CONCEPT_HDL   COPY_PROJECT     Copy projecthangs if library or design name has an underscore
. Q5 D: u9 M* `% O% ^1152769 PSPICE        ENCRYPTION       Unable to simulate Encrypted Models in16.6
1153308 ALLEGRO_EDITOR DRC_CONSTR       Creating Artwork Getting Warning"DRC is out of Date" even when DRC is up to date
% Y* n& V- d- O( F1 P1153893 F2B           DESIGNVARI       16.6 VariantEditor not supporting - in name
1154185 SIG_INTEGRITY SIGNOISE         Signoise didn'tdo the Rise edge time adjustment.
1154860 ALLEGRO_EDITOR MANUFACT         Double digit drill character overlapswith figures triangle, hexagon and octagon in NC drill legend
1155167 ALLEGRO_EDITOR EDIT_ETCH        Via structure placed in Create Fanouthas incorrect rotation.
1155728 CONCEPT_HDL   CORE             Unable to uprevpackaged 16.3 design in 16.5 due to memory
% G8 c2 \8 A  j2 P1155855 SCM           SCHGEN           A newlyuser-defined net property is not transferred from SCM to DEHDL in PreservedMode
! w$ q' X2 Q* X& Q& ]7 b1156274 ALLEGRO_EDITOR INTERFACES       Exported Step file from Allegro is wrong
1156316 CONSTRAINT_MGR OTHER            Break in functionality whilecreation of pin-pairs under Xnet in Constraint Manager
1156351 CONCEPT_HDL   CONSTRAINT_MGR   Loose members inPhysical Net Class between DEHDL and Allegro
1156547 ALLEGRO_EDITOR DRC_CONSTR       Etch Turn under SMD pin rule checkthrough pin Etch makes confused.
1156779 CONSTRAINT_MGR OTHER            Electrical Cset References in CM notworking correctly
; N, S! |# l* D$ W% [1157167 ALLEGRO_EDITOR SKILL            axlPolyFromDB with ?line2poly isbroken
1 O8 V, t2 Q" I+ ~1158042 ALLEGRO_EDITOR DFA              DFA_DLG writes the dra file namein uppercase.
) a5 G8 N3 w  K) i5 l, V1158718 CONCEPT_HDL   CHECKPLUS        Customer couldnot get $PN property values on logical rule of CheckPlus16.6.
. @, K8 v1 A' \  P# d1158970 ALLEGRO_EDITOR SCHEM_FTB        Changing LOCATION to $LOCATION in DEHDLdoes not update the .brd file
1158989 ALLEGRO_EDITOR INTERFACES       pdf_out -l creates a PDF
1159285 APD           DXF_IF           DXF_OUT fails;some figures are not exported
, P- E, m) z; }" x  O1159432 ALLEGRO_EDITOR SHOW_ELEM        http:// in the Show Element in 166 donot have HTML link to open the Website
1159483 PCB_LIBRARIAN SETUP            part developercrashing with
# S0 w/ N( n- N+ Y5 d& {1159516 ALLEGRO_EDITOR EDIT_ETCH        Unable to slide cline segment with newslide.
4 ~: a$ K3 v$ ]" j6 @1159959 ALLEGRO_EDITOR GRAPHICS         3D viewer displays clines arcsincorrectly
1 y5 i# l; q: D! ]: R9 F( k1160004 SCM           UI               The RMB->Pastedoes not insert signal names.
9 }/ \5 J+ v% b$ H1160410 ALLEGRO_EDITOR DATABASE         Lock databse with View Lock option ismisleading
1160529 SCM           SCHGEN           Schematicgeneration stopped because the tool was unable to create an appropriateinternal symbol structure
* [8 Q, w" g  q  x1160537 SPIF          OTHER            Cannot start PCBRouter
1161363 ALLEGRO_EDITOR SYMBOL           Getting error SPMHGE-73 when tryingto mirror symbol
/ r; H; o' b# r1 L9 m/ P. _$ P" r6 c' _1161781 CONSTRAINT_MGR CONCEPT_HDL      SigXp crash when selecting ECset indesign
! X0 V0 }- `( o0 o/ ~& M1161896 ALLEGRO_EDITOR DRAFTING         Tolerance value added for Dimensionsis not working correctly (HF11-12)
; o0 r6 E" M) A1 o( L/ L; U7 p1162193 SIP_LAYOUT    DIE_ABSTRACT_IF  shapes in diafile not linked to the die after edit co-design die
% f) c% W( N3 l2 J8 j& f8 A1162754 APD           VIA_STRUCTURE    Replace Via Structurecommand selecting dummy nets.