请帮我看下下面的代码错在什么地方，谢谢！

freeunix

我最近在看中国电力出版社出版的FPGA嵌入式系统设计与开发指南这本书，下面的代码是本书的第第一章的第三段代码，我使用QII 11.0WEB版本无论如何无法正确编译，总是提示10559错误，请各位高手帮我看下问题所在，谢谢！
7 P0 C2 D! P( S( ], S, M  h
. P  R2 h, Q$ K8 Z
library ieee;
4 k; p* D$ o- R7 {  I2 P9 euse ieee.std_logic_1164.all;
) @% w% x  f( x7 L) j+ V- y- Y. M# i* p+ Kuse ieee.std_logic_unsigned.all;
entity counter8bit is
  port(int ,reset,enable: in std_logic;count_out: out std_logic_vector(7 to 0));
  end counter8bit;
    architecture counter of counter8bit is
         signal count_in: std_logic_vector( 0 to 7);
         begin
! M0 {% |+ m4 a1 i' Q/ d2 k          process(input,reset)
             begin
                    wait until rising_edge(input);
                          if reset='1' then
2 z% ~( A5 x4 Z1 @                           count_in<=(others =>'0');
0 Q: V, i9 X9 f8 q                                elsif enable= '1'  then
                                  if (count_in="11111110")  then
9 h4 }0 L2 k0 }                                    count_in<="00000000";
                                  else
                                         count_in<=count_in+1;
3 i: v0 U, d6 z3 R( u; ^$ `                                  end if;
: r' @$ N) ^/ s, Z! ?# d                         end if;
                         end process;
9 |" k: O( m, E7 Y                         end counter;
                                         
, y9 g9 A6 q" c' _5 R; D

, x6 l+ e. C% KlInfo: *******************************************************************
! {# i/ k, P8 |, dInfo: Running Quartus II Create Symbol File
        Info: Version 11.0 Build 157 04/27/2011 SJ Web Edition
        Info: Processing started: Wed Jul 24 14:43:41 2013
+ J9 ~! p4 M- z, `  y1 B        Info: Version 11.0 Build 157 04/27/2011 SJ Web Edition
1 A4 z7 X' G0 I5 x3 n5 r        Info: Processing started: Wed Jul 24 14:43:41 2013
% q5 v& Z* ~; T6 Y4 h- ^Info: Command: quartus_map --read_settings_files=on --write_settings_files=off penlvji -c penlvji --generate_
Error (10482): VHDL error at counter8bit.vhd(12): object "input" is used but not declared
8 q* N! |, j/ g. U- Q! D3 T8 GError (10559): VHDL Subprogram Call error at counter8bit.vhd(12): actual for formal parameter "s" must be a "signal"
+ {1 n$ G# S8 `! f% y- b2 HError (10482): VHDL error at counter8bit.vhd(10): object "input" is used but not declared
# _0 y# }2 ]% _2 r& NError: Quartus II Create Symbol File was unsuccessful. 3 errors, 0 warnings
       

zgq800712

object "input" is used but not declared
你先把这句话翻译了再说。

gusumurong

你的输入接口只有int ,reset,enable。"input"信号在哪里呢？

freeunix

但是我看了line12,没找到错误啊
8 b2 A& h6 b3 b1 ~

gusumurong

这个错误信息给的还不够明显？