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本帖最后由 dsws 于 2013-7-1 20:32 编辑 ! U5 P. b/ h2 n" r, g
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DATE: HOTFIX VERSION: 012
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CCRID PRODUCT PRODUCTLEVEL2 TITLE: j- ~0 k5 Q, W/ p' O
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914562 ALLEGRO_EDITOR GRAPHICS 3D viewer, PCB Symbol view in DRA needs to be same as in BRD- H( o! }5 N" H' o. H, A
1120397 CONCEPT_HDL CREFER CreferHDL attempts to create missing vlog004u.sir files. `/ R; v* }! C2 w$ a* D* i
1136449 ALLEGRO_EDITOR GRAPHICS about previous shape fill display, o' m- u2 a7 O w% S
1145635 ALLEGRO_EDITOR SHAPE Auto Voding on the same net shapes with other parameter.
3 z T" p3 T0 S) g% ~" O1150334 ALLEGRO_EDITOR EDIT_ETCH AiDT deletes the clines and turns it back to PLAN line0 |! ]2 a. F' o5 L5 O
1151100 APD VIA_STRUCTURE Net filter not working in replace via structure command.# F9 e2 S5 i' `) k
1151126 APD VIA_STRUCTURE Getting "group is not appropriate at this time" message when using Temp Group.
E6 `" r% G2 |2 L" d* J3 d1151458 GRE CORE GRE crashes on Plan Spatial
* g/ N' G9 U+ @# C. O1151932 F2B PACKAGERXL PXL error when case is wrong at differen levels in hierarchy/ }, ]; `1 Q+ X+ J/ s6 M2 q
1152151 ALLEGRO_EDITOR INTERFACES dxf2a gives error [SPMHGE-268]! X R& f2 I- i
1152475 PSPICE SIMULATOR RPC server unavailable error while simulating the attached design% d/ k4 h; h) G4 M
1152737 ALLEGRO_EDITOR SKILL dbids are removed because highlighted objects in setting the xprobe trigger
3 M2 e* h8 b7 y: M( P {6 ~1153006 ALLEGRO_EDITOR SKILL axlUIWPrint dose no work correctly in allegro PCB Editor 16.6./ |7 [& `+ D6 |' f' ~6 d
1153279 CONSTRAINT_MGR OTHER Netrev changing design accuracy from 3 to 2 dec places" o# u2 [3 p! i5 e. J
1153461 SIP_LAYOUT DIE_EDITOR Regression problem in 16.6 ISR: Dia Abstract ECO is causing Die Editor Finish to fail( M. ]' C8 u: e+ r& H% ~/ x: P
1154973 APD EDIT_ETCH Same Net "Line to Line" violation occurs even with "Allow DRC's" turned off.
4 ]) P0 i% `- l( w: Y9 S$ z! C C1155227 ALLEGRO_EDITOR DRC_CONSTR via to shape check on the negative layer
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http://pan.baidu.com/share/link? ... 0&uk=3826038294
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发表于 2013-7-1 12:00
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