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本帖最后由 dsws 于 2013-7-1 20:32 编辑
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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3 J! a4 H2 F4 u0 {& C5 J: W' v# w! M914562 ALLEGRO_EDITOR GRAPHICS 3D viewer, PCB Symbol view in DRA needs to be same as in BRD
7 a3 k: n: S0 g& X4 E8 m7 x$ d1120397 CONCEPT_HDL CREFER CreferHDL attempts to create missing vlog004u.sir files6 D+ n$ a9 W! U; }0 l ^/ {
1136449 ALLEGRO_EDITOR GRAPHICS about previous shape fill display
* R k" b# H1 k, ]/ C1145635 ALLEGRO_EDITOR SHAPE Auto Voding on the same net shapes with other parameter.
7 W$ U3 |" g6 X# R4 }1150334 ALLEGRO_EDITOR EDIT_ETCH AiDT deletes the clines and turns it back to PLAN line# u" u1 [7 t% j- a( G
1151100 APD VIA_STRUCTURE Net filter not working in replace via structure command.; L! K7 g) q/ F# x
1151126 APD VIA_STRUCTURE Getting "group is not appropriate at this time" message when using Temp Group.
}* t% T3 ^* t l% p9 Z! A1151458 GRE CORE GRE crashes on Plan Spatial9 ]: {+ F7 B) Z( M% Y9 ?* V
1151932 F2B PACKAGERXL PXL error when case is wrong at differen levels in hierarchy
! D8 V% b% S, f6 L* ~& X, t1152151 ALLEGRO_EDITOR INTERFACES dxf2a gives error [SPMHGE-268]
4 K; g) k+ h/ P" V& U1152475 PSPICE SIMULATOR RPC server unavailable error while simulating the attached design5 \* f( T) @ S
1152737 ALLEGRO_EDITOR SKILL dbids are removed because highlighted objects in setting the xprobe trigger9 U# J7 P' J- \2 y; Q8 I
1153006 ALLEGRO_EDITOR SKILL axlUIWPrint dose no work correctly in allegro PCB Editor 16.6.
( f# v1 _. _6 f& ^( a4 J1153279 CONSTRAINT_MGR OTHER Netrev changing design accuracy from 3 to 2 dec places
- V$ w3 D, R1 S" [1 t2 m! C$ ~& }1153461 SIP_LAYOUT DIE_EDITOR Regression problem in 16.6 ISR: Dia Abstract ECO is causing Die Editor Finish to fail' @7 i3 A8 Z# B
1154973 APD EDIT_ETCH Same Net "Line to Line" violation occurs even with "Allow DRC's" turned off.- d* x% x4 x1 w L
1155227 ALLEGRO_EDITOR DRC_CONSTR via to shape check on the negative layer5 u5 L% k4 e- a. x+ W) p f
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! q0 \ z" p4 O# d$ K) Shttp://pan.baidu.com/share/link? ... 0&uk=3826038294
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发表于 2013-7-1 12:00
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