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本帖最后由 dsws 于 2013-7-1 20:32 编辑
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5 M* B6 l' ~" J; z1 W; S* XDATE: HOTFIX VERSION: 012
% K) f7 F' m9 P$ \1 t===================================================================================================================================: ^8 `5 L& o3 O- c3 \1 r/ q8 H
CCRID PRODUCT PRODUCTLEVEL2 TITLE
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$ x4 @# c7 Y `! M! e914562 ALLEGRO_EDITOR GRAPHICS 3D viewer, PCB Symbol view in DRA needs to be same as in BRD p a( `( j! i2 c7 A; Z5 Q
1120397 CONCEPT_HDL CREFER CreferHDL attempts to create missing vlog004u.sir files+ x3 w/ n0 `+ \& G6 ?
1136449 ALLEGRO_EDITOR GRAPHICS about previous shape fill display8 K3 ] P. o0 {6 Q* u, }- g
1145635 ALLEGRO_EDITOR SHAPE Auto Voding on the same net shapes with other parameter.
& _" ]9 A* J% I5 c+ B1150334 ALLEGRO_EDITOR EDIT_ETCH AiDT deletes the clines and turns it back to PLAN line: n; v7 ]' t; @8 s- `8 [- n) }
1151100 APD VIA_STRUCTURE Net filter not working in replace via structure command.
% o5 f3 }0 D3 \4 ]8 v8 [1 X+ e1151126 APD VIA_STRUCTURE Getting "group is not appropriate at this time" message when using Temp Group.) W3 @* @! J+ E" E8 f0 x0 s
1151458 GRE CORE GRE crashes on Plan Spatial+ |7 s% @: k. {0 e( x7 g: O
1151932 F2B PACKAGERXL PXL error when case is wrong at differen levels in hierarchy4 ^, h6 [) `# T% O4 B& U
1152151 ALLEGRO_EDITOR INTERFACES dxf2a gives error [SPMHGE-268]- @6 S ]9 J P, }6 G, y/ s
1152475 PSPICE SIMULATOR RPC server unavailable error while simulating the attached design d/ x$ s, ?/ T0 x! c' O5 q9 Q
1152737 ALLEGRO_EDITOR SKILL dbids are removed because highlighted objects in setting the xprobe trigger# U( V6 n: e3 d4 s; V
1153006 ALLEGRO_EDITOR SKILL axlUIWPrint dose no work correctly in allegro PCB Editor 16.6.
8 H* s, K7 j5 m; n; {) v1153279 CONSTRAINT_MGR OTHER Netrev changing design accuracy from 3 to 2 dec places' O7 H- t9 v0 X4 k; U8 {9 {
1153461 SIP_LAYOUT DIE_EDITOR Regression problem in 16.6 ISR: Dia Abstract ECO is causing Die Editor Finish to fail
2 C! e4 t& y9 e, t1154973 APD EDIT_ETCH Same Net "Line to Line" violation occurs even with "Allow DRC's" turned off.
% O' t Q* I+ t" o. Z/ w2 N1155227 ALLEGRO_EDITOR DRC_CONSTR via to shape check on the negative layer
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, N7 G3 H& R* d2 j- q8 N0 Ihttp://pan.baidu.com/share/link? ... 0&uk=3826038294* @% ^2 l$ C @
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发表于 2013-7-1 12:00
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