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本帖最后由 hzqydq 于 2013-4-9 15:11 编辑 - s& t+ t& I5 S, H
3 F8 P- ~+ g- W- Z3 c7 aHotfix_SPB16.50.041_wint_1of1.exe
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8 I3 ?' t/ x# y3 M7 N下载地址* E- X s) n! O* o% U& Y3 z
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http://dl.vmall.com/c0kgf7xkaj
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# H1 f8 {% P9 j/ \# F# WHotfix中只需要安装最新的版本即可。5 Y/ @$ [1 m9 }# p6 O
DATE: 04-4-2013 HOTFIX VERSION: 041
* ]1 V. h- m4 N9 I7 C5 A: m1 D===================================================================================================================================
/ ~* I" g) Q; A! MCCRID PRODUCT PRODUCTLEVEL2 TITLE9 d4 M' V' n y, j
===================================================================================================================================
& }! N; r3 V5 g: |835944 ALLEGRO_EDITOR OTHER Customer want to change for Jumper symbol by other Alt symbol.7 E6 t0 @0 r# k3 V0 [4 i
988019 ALLEGRO_EDITOR PLACEMENT Allegro hangs when doing place replicate create! N$ h7 M/ o$ k# D
1065641 PCB_LIBRARIAN CORE PDV symbol editor is crashing when deleting a group using delete or CTRL+X' A# d# p4 |. W7 O
1073152 CONCEPT_HDL OTHER Printing Published PDF schematic has missing lines& s9 i* }% X! ^
1082587 FSP FPGA_SUPPORT Support of Xilinx's Zync device
' n. K4 H5 w0 m: F1100945 SCM SCHGEN SCM generated DE-HDL has $PN placement issue! w& Z i$ r$ R9 K0 Y4 E0 v
1107172 CONCEPT_HDL OTHER Project Manager Packager does not report errors on missing symbol; I" @8 l: Q, M2 ]0 t3 r
1107397 SIP_LAYOUT PLACEMENT Place Manual-H rotates die7 L+ j9 P6 w8 x+ Z* @
1108603 PCB_LIBRARIAN VERIFICATION PDV Tools Verification > View Verification (CheckPlus) leaves <project>.cpm_tmp.cpm" ~9 Z3 ?. |0 @0 |# c7 p
1109466 ALLEGRO_EDITOR ARTWORK Artwork create some strange gerber lines for fillet.
4 {2 E/ b' l' n* E( Q1109926 CONCEPT_HDL CORE viewing a design disables console window
. T0 E' J: Z% W7 K6 @0 [1110077 ALLEGRO_EDITOR DRC_CONSTR Duplicate Drill Hole DRC's are not shown for Pins overlapped in same symbol unless "Min metal to metal" DRC is turned ON2 ]8 A7 w2 z* R2 n" F4 W5 ~% ?" e
1110264 RF_PCB FE_IFF_IMPORT IFF Import in DEHDL has component offset
& \- E& j- g2 T8 a" q" x9 e1112295 APD DXF_IF Padstacks offset Y cannot be caught by DXF.
% [; D( a. s% i8 W1 e1 {% g! B6 {1112395 CONCEPT_HDL CORE BASE\G for global signal is not obeyed after upreving the design to 1650.
4 h/ V$ z2 o ?& h3 ~$ a: `1112774 GRE CORE Allegro GRE not able to commit plan after topological plan
( H& B. u3 |& r' ^0 i1113317 CONCEPT_HDL SKILL skill code to traverse design not working properly
; I8 ?5 V1 a* L# h8 H" Y1 D d; D1114630 CONCEPT_HDL ARCHIVER Archcore fails because the project directory on Linux has a space in the name
) K' M3 J% ]" K* t4 x* d( {1114689 CONCEPT_HDL CORE Unknown project directive : text_editor' z5 F; V' h8 m2 j
1114928 F2B PACKAGERXL error (SPCODD - 5) while Export Physical even after change pin from A<0> to A
: m3 H# u- T% W" m6 l1115625 ALLEGRO_EDITOR SKILL Design extents corrupted when axlTrigger is used.
* \9 _0 a4 Y _* I6 W4 P6 F1115708 ALLEGRO_EDITOR INTERFACES Export DXF is outputting corrupt data on one layer. |
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发表于 2013-4-9 15:08
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