What’s New in Cadence OrCAD 16.6 Release

bluemare · 发表于 2012-10-26 13:24

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The Cadence® OrCAD® 16.6 release continues to address our customers’ toughest PCB design challenges. Delivering on four key goals—improved product usability, increased product performance, new design flows, and expanded Tcl scripting integration—the 16.6 release will benefit every user of OrCAD technology.

Cadence OrCAD Capture & Cadence OrCAD CaptureCIS
Capture – PCB SI integration and flow: With product integration comes a new bi-directional schematic entry/signal integrity flow that allows electrical engineers to explore circuit topologies, develop constraints, and analyze signal integrity.

Quick-place for common components: A new menu, Place >PSpice Component, enables quick-place for commonly used schematic or simulation components. The menu items list of components is user-configurable and has been pre-populated with PSpice® simulation devices (passive, discrete, sources, digital).

User-configurable menus and toolbars: Menus, toolbars, and icons in OrCAD Capture, PSpice Advanced Analysis, and Model Editor can now be customized. This makes it possible to run any Tcl method or script from the menus.

Enhancements to the Find function: The Find function now allows searches for parts by value of a given property (e.g. Property Name=Value) or use of a regular expression as the search string. For example, to search for components with designators starting with C or R and followed by any number between 2 and 9, use the search string Part Reference=(C|R)[2-9].

NetGroup enhancements: The NetGroup use model is now aligned with the Bus use model for intuitiveness and consistency. Enhancements areas include: assign a NetGroup to a Bus, reorder pins in an unnamed NetGroup, add and remove pins from a NetGroup, visible NetGroup references, and find NetGroup references.

CIS performance increase: The overall performance for CIS operations, especially when dealing with very large databases or queries, has been significantly improved.

Tcl customization for CIS Explorer: CIS Explorer can be custom-configured with user-definable actions and capabilities. (For example, customized part placement checks can disable placement of an EOL part or provide a warning if part procurement has a long lead time). Query result rows can also be customized. (For example, rows can be highlighted blue for recommended parts or red for parts not recommended or allowed.)

Enhanced Save function for design and library: Pages that are changed and need to be saved are now marked by an asterisk (*)in the Capture Project Manager. When a save is initiated, the marked pages are saved.

Global Replace for OffPage: The Find and Replace dialog box (Edit> Global Replace) has a new option, OffPage Connector, to find and replace OffPage connectors.

Preserve “User-Assigned” designator: Reference designator management improvements now track the user-modified references and allow finer end-user control over managing the part references for the entire design. A reference designator can be interactively set as user-assigned through the newly added “User-Assigned” flag to preserve designators and references in conjunction with the Preserve Designator and Preserve User-Assigned Valid References in the Annotate window. Capture will also mark a reference designator as user-assigned if the reference is manually changed in Property Editor, manually changed in the schematic canvas, or changed by the board through back-annotation.

Design Level auto reference: In addition to schematic-level annotation, design-level annotation is now available by selecting the Design Level option in the Miscellaneous tab of the Preferences dialog box. An option to preserve references when copying is also available.

Browsing/viewing designs created in earlier versions: Designs created using earlier versions of Capture can now be opened and viewed without requiring the design to be uprev’ed. Such designs only need to be uprev’ed when the design is actually saved.

Closing all tabs: Canvas tabs can now all be closed, or all but this tab closed with an RMB selection. Right-click on the tab and choose the appropriate option (Close, Close All Tabs, or Close All Tabs But This).

Custom design rule check (DRC): Though Tcl scripting, user-defined schematic and circuit checks can be created and added to the Capture DRC routines. Several R&D examples include checks for hanging wires, device pin mismatches, overlapping wires, reference prefix mismatches, port-pin mismatches, and shorted discrete parts. Project Save As enhancements: While saving a project in 16.6, a project name that is different from the design name can be specified to mimic the manual process of copying/moving a product from one hard-drive location to another. Options include the ability to copy/move all referenced files, ensuring that all links are updated while saving. RefDes support alignment: Capture and CIS now handle references and designators in the same manner, eliminating the need for manual Reference Designator corrections in the CIS database and BOMs. CIS now supports all reference designator formats including as U2N, C1_R, C12-1, R7-TOP, MP_2V5_REF, and TP3V3_0. Also, the reference designator for multi-packages is consistent (e.g. MP_2V5_REF will be MP_2V5_REF not MP_2V5_REFA).

Multi-value support: Any CIS field can now be set as multi-valued for component instances with numerous information or content sources (e.g. lists for multiple datasheets/application notes or multiple PSpice models for a component).

Linking external design parts: Referenced parts of the external design can now be linked at the group or subgroup level.

Cadence PSpice A/D & Advanced Analysis
Advanced control options: Numerous advanced convergence and simulation control options/parameters have been added or exposed, giving users greater control over simulation and convergence. These options include: bias-point convergence, voltage limiting, worst-case deviations, max-time step control, pseudo transient, and relative tolerance.

Probe .dat upgrade to 64-bit precision: PSpice now generates 64-bit data precision in the .dat file output. This ensures higher precision compared to the 32-bit .dat file data from previous releases. (As an example, in previous releases, when a very small amplitude voltage is superimposed on a large voltage, the resulting voltage lost its resolution in a 32-bit .dat file.)

UNDO support for captured netlists: Netlisting to PSpice now preserves UNDO, making it easier to make iterations and modify parameters, components, and connectivity.

Enhanced IBIS support: The IBIS to PSpice model now supports V-T curves for all IBIS models up to version 5.0

Multi-core engine support: Enhancements to multi-core support and I/O read-write provide significant performance improvements. Focused performance enhancements, especially for large designs or designs with complex model instances (MOSFETS, BJT), also boost performance.

Encryption enhancements: Upgraded model encryption now includes 256-bit (AES) encryption support.

Tcl-based customization: Advanced Analysis, simulation, and .dat file access can be accessed and extended with user-definable actions and capabilities. This enables an environment that can be enhanced to specific flows and needs, and allows users to leverage enhanced features and design capabilities.