求助代码编译问题

stonylian · 发表于 2012-6-26 16:43

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本人新手，下面是一Verilog HDL程序代码，为什么总是编译不成功啊，恳请知道的帮助解决一下啊，
module ihq_counte(rst,clk,ihq_control,ia,ib,ic,iap,ibp,icp,iahq,ibhq,ichq);
input rst;
input clk,ihq_control;
input[15:0]ia;
input[15:0]ib;
input[15:0]ic;
input[15:0]iap;
input[15:0]ibp;
input[15:0]icp;
output[15:0]iahq;
output[15:0]ibhq;
output[15:0]ichq;
reg signed[15:0]a1,a2,a3,bl,b2,b3,cl,c2,c3,iahq,ibhq,ichq,iahq1,ibhq1,ichq1;
always @(posedge rst or posedge ihq_control)
if(rst)
begin
iahql=0;
ibhql=0;
ichql=0;
end
else if(clk)
begin
iahq=ihaql;
ibhq=ibhql;
ichq=ichql;
end
else

begin
if(ia[11]==0)al=ia;
else
begin
al=ia;
a1[15:12]=15;
end
a2=iap;
if(a2>0)a2=a2>>3;
else
begin
a2=a2>>3;
a2[15:13]=7;
end
if(ib[11]==0)b1=ib;
else
begin
bl=ib;
bl[15:12]=15;
end
b2=ibp;
if(b2>0)b2=b2>>3;
else
begin
b2=b2>>3;
b2[15:13]=7;
end
if(ic[11]==0)cl=ic;
else
begin
cl=ic;
cl[15:12]=15;
end
c2=icp;
if(c2>0)c2=c2>>3;
else
begin
c2=c2>>3;
c2[15:13]=7;
end
a3=al-a2;
b3=bl-b2;
c3=cl-c2;
iahql=a3;
ibhql=b3;
ichql=c3;
end
endmodule