错误如下 9 y( d2 t& g. R5 Z" Z$ g U# XERRORack:679 - Unable to obey design constraints (LOC=CLB_R38C1.S0) which9 c5 P! ^! g& P ~
require the combination of the following symbols into a single SLICE* k5 z) l' R" [' j6 n
component: 8 |# i5 {; a. x" _+ C; L FLOP symbol "Chain[37].uChain/Node[0].uNode0/uFdce" (Output Signal =6 l" U9 ~# N/ [3 X; r
Chain[37].uChain/wOutA0<0>) + U6 l. ]$ T; g" H V FLOP symbol "Chain[37].uChain/Node[0].uNode1/uFdce" (Output Signal = ; ~$ e4 q# Q; H Chain[37].uChain/wOutA1<0>)3 q$ C7 m3 U Y4 r: _: U
The set/reset signal Reset_IBUF_1 of register0 Z: x; ~/ f1 |7 ?4 j) n$ K
Chain[37].uChain/Node[0].uNode1/uFdce doesn't match the existing usage of the/ S/ Z+ j3 Z' ^
SR MUX. The signal Reset_IBUF_2 already uses SR. Please correct the design 9 L6 X p6 a7 |" r( P) r7 M; a I constraints accordingly.; G; \9 |2 q: j: i# j. T: c
请大侠帮忙
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发表于 2012-6-8 17:35
ack:679 - Unable to obey design constraints (LOC=CLB_R38C1.S0) which9 c5 P! ^! g& P ~
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