EDA365电子工程师网

标题: 求助，此PADS转入ALLEGRO走线一根都没有了 [打印本页]
作者: 123456789lil.    时间: 2011-10-12 00:37
标题: 求助，此PADS转入ALLEGRO走线一根都没有了
Translating E:\WORK\TEST\1.asc.7 m& E: p( v' u5 d/ N/ L, q+ e. J
Reading PADS ASCII file header.! T2 k: O: I3 A+ a# @1 X
Version = PowerPCB5.05 W* Z; ]( Y. j2 K0 F) i6 Q) n
Route Layers = 4( Y2 l( h5 E$ v( }( K5 S; E
Units = METRIC
: B! ?2 C% X* d& {2 K4 e% a Hatch mode = Vertical / Horizontal
' z# ?# A5 _6 T) I* Z% y" ?# U4 ~ Hatch grid = 2.000000, angle = 0.000000, anti-pad spacing = 0.0003158 A5 u% d  H9 Y$ _" t( Y/ f
Initializing new database.4 l5 J" U: C3 E- [6 K+ A
Creating layers.
* u/ |- N9 P% R/ fReading PADS ASCII file body.
5 a) `, @+ ?+ y *PARTTYPE*/ D0 U. w* n0 I) P: A/ t
*MISC*4 {; E( V8 A4 ]
*MISC*0 o0 H9 b# o# N1 I* r+ d/ w
*MISC*
& L: X* j# ]6 j5 R) h' O *MISC*
( I2 g8 U; V, K2 }- g: v *MISC*
; `. T; f. X9 O5 {# P *REUSE*3 f* n% I: \" ~( u
*TEXT*, n' V: m9 @, k/ o9 G$ n, C
*LINES*
+ ^( Q) a0 j$ u& k! ~$ c *VIA*
! B- v; ]" `8 @9 f  T *PARTDECAL*6 E; R* b0 ]- T0 i
*PARTTYPE*
; L4 \- G+ ], [8 U *PART*- R. h* K5 M4 t2 `, c" M
*ROUTE*# d; n6 U9 M4 G( s( I
Writing routes.( R6 C  [( K+ Q; D
*END*/ r. a; N( J/ G1 e

; t% L' `9 d) i2 x' c===============================================================================
5 c6 ^# V$ p$ j9 S PADS layer usage summary:& ~3 E# D2 r2 l: [
  Layers 1 to 4 are route layers.
! q/ F1 J( _* Y+ b! L  H  LINES:
* X) v' a  E* B# l: g/ J5 Y     0 BOARD GEOMETRY - ALL
8 H" o: X, F/ R6 ~& M0 n' H' Z  H     1           ETCH - TOP
, H. B' c7 e/ y% V0 x2 ~     3           ETCH - INTERNAL2
) v' j6 V7 ?9 Z% q  R1 @9 K     4           ETCH - BOTTOM
* o; _9 R. j- I2 Y9 I' {     9  * Not mapped!
9 G6 A) M$ [6 M& U! x, R- N9 k    10  * Not mapped!( v, p  j6 T. Q: }% n1 q  I) T
  COPPER:
$ o/ o/ b/ M" s2 L  TEXT:8 Z9 g( f; }7 L  X1 k
     1           ETCH - TOP; O4 r( G% b4 X% Q) Y
    26  * Not mapped!" t% z! w1 I* ?9 Q
  DECALS:
- i# M" Z3 |: E& c8 Y, Z* E: e     0 PACKAGE GEOMETRY - SILKSCREEN_TOP- t9 f9 I2 x0 P
     1 PACKAGE GEOMETRY - SILKSCREEN_TOP
, r2 u3 x' I+ _: M/ X# Z# _    12  * Not mapped!
1 A7 f6 @) b; u& l6 R: v! K. Z    19  * Not mapped!+ p+ d" F. @5 U" {
    26  * Not mapped!% L  Y  @2 r" ^& H
  PADS:. l2 Z1 A. d3 X6 ^4 k6 b! V
     0           ETCH - internal_pad_def. {6 q, T) a+ o/ _/ `& g
     1           ETCH - TOP
; W* k- l8 @, R7 Z! a% v     2           ETCH - INTERNAL1. ~& r/ f, W4 Z! ?3 U9 g: R1 E( J& q9 j
     3           ETCH - INTERNAL2, E8 D5 |9 U. n9 A
     4           ETCH - BOTTOM" m$ x! T2 h0 B+ q
     6  * Not mapped!" L0 H& L% V% R- K) q0 ]8 ?7 P
    15  * Not mapped!
% B; ~4 v9 _1 [6 I3 z4 ?  ^$ Q( U    16  * Not mapped!4 m* ?: ~" [$ [5 N8 {. u. R4 E+ E
    23  * Not mapped!
* H. T- M2 ~( R; x1 `# u+ D  VIAS:
: ~' u# w) g! @3 R     0      VIA CLASS - internal_pad_def
5 I" z$ p7 f, F     1      VIA CLASS - TOP2 I; s, Q- g( T
     2      VIA CLASS - INTERNAL15 J% @- n4 M  i$ B% ^9 G2 O. T
     3      VIA CLASS - INTERNAL2
8 y8 S1 p+ n3 b& q3 h     4      VIA CLASS - BOTTOM. w, J) Y( r, @/ Y  G

6 P$ P4 P* F; \7 a# J9 ~ WARNING: 63 data objects mapped to the UNUSED class were ignored.
( t- R+ I; b; t6 M1 i: K===============================================================================# d: ~2 A/ P$ m/ B" k4 Q. B
" j/ l. i% x$ Z- K9 g" d
Creating E:\WORK\TEST\1.brd.7 ^% F3 h2 f4 ?3 E% L  {
Loading netlist:
* W: G) u' }: ^1 U5 LE:\WORK\TEST\1.TXT
& F( K- q  R( T; pWriting database.
; I, D. p5 A1 p, v! ^, b* {ERROR: Error while writing the Allegro database.
2 e" B+ Y3 A& g! e! }Closing database.
+ `2 h8 H4 U3 z  G1 ~! W( f9 ~Translation complete.* R* @, \$ [* V! l$ E8 O
Finished with errors!
5 B1 t) A$ z4 {/ U% l- m5 t, k/ ~
作者: mindray_ty    时间: 2011-10-12 09:06
这个问题说明你的在导出的时候选择有些问题，在导出的时候这是非常关键的一步骤！
作者: 123456789lil.    时间: 2011-10-13 13:07
兄弟别的板子我随便都导成功，只有这个板怪得很
作者: flyingc381    时间: 2011-10-13 13:23
这个接口做得一般，，
2 q# b! X. e8 m  b' {; \
- P7 {0 g$ `, @' C, \% ?4 l! V! W所以有问题很正常



欢迎光临 EDA365电子工程师网 (https://bbs.elecnest.cn/) Powered by Discuz! X3.2