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本帖最后由 stupid 于 2010-6-30 14:56 编辑
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) B* e f+ I- T- U4 `/ k/ e+ sChip-Level Design
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Strong Encryption and Correct Design Are Not Enough: Protecting Your Secure System from Side Channel Attacks
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5 ^) Z# X- z. w& }# S: `Board and System Design
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; s6 n/ h, v; j3 [ k+ pEffect of Conductor Profile on the Insertion Loss, Phase Constant, and Dispersion in Thin High Frequency Transmission Lines
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1 m% n3 L2 A& K. f0 ?! ]Introduction and Comparison of an Alternate Methodology for Measuring Loss Tangent of PCB Laminates9 b1 c" W" h) m2 P6 y, c
+ \, J: k9 _4 o- `0 t# E* S% oInterconnect Design
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3 Q: H; B2 r$ }2 |, p, i; BFrequency Dependent Material Properties: So What?
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Additional Trace Losses due to Glass-Weave Periodic Loading, M9 U. A/ m6 y) }! C" s$ W
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High-Speed Design and Test Category
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3 ?% [, D P6 i5 W% YA New Method for Receiver Tolerance Testing Using Crest Factor Emulation# e& n9 c7 i0 Y& p
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Accuracy Improvements of PDN Impedance Measurements in the Low to Middle Frequency Range8 l/ ]5 W/ Z+ @- f7 l, J! q
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Power and RF Design Category; l" z( }% T+ @* h+ b8 {
* ^* b) e9 b! W' POn-Chip PDN Noise Characterization and Modeling: n' |0 G3 ^3 |2 y/ }2 T0 M! r
1 h! |- g% e( O/ [* q8 bFast Physics-Based Via and Trace Models for Signal and Power Integrity Co-Analysis |
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发表于 2010-6-30 14:55
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发表于 2011-9-4 13:20
