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本来一直好好的,元器件都布局好了。然后去ORCAD里更改了一下原理图里几个电容的封装,再更新到PCB就出错了。有人有解决办法吗?不然白忙活了。) n; a' o) y4 s3 C5 f4 l
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Allegro里的出错报告如下:7 z8 N& m1 R( B% M; I
Cadence Design Systems, Inc. netrev 15.7 Wed May 12 21:32:04 2010
* D/ z9 W% ^( q% r I2 g% E* z(C) Copyright 2002 Cadence Design Systems, Inc.
$ N/ j6 s, C- h. }- p------ Directives ------
/ ^$ N& }' A6 C/ O* z( tRIPUP_ETCH TRUE;
6 J. q# v( U9 L+ ?+ f& e% v, U) ^- kRIPUP_SYMBOLS ALWAYS;
4 j+ |& X0 w" B0 @# A' fMISSING SYMBOL AS ERROR FALSE;
& Q6 Y; }9 ^' USCHEMATIC_DIRECTORY 'D:/CadenceWork/HongelDM642/PCB/allegro';0 ~' B* @3 C; V, H, i2 L0 _8 n
BOARD_DIRECTORY '';" ]# M: S. ~( `! c4 R
OLD_BOARD_NAME 'D:/CadenceWork/HongelDM642/PCB/DM642_Core_Board.brd';3 j9 Z) c2 N7 o5 e' b' _7 |
NEW_BOARD_NAME 'D:/CadenceWork/HongelDM642/PCB/DM642_Core_Board.brd';
- K9 v' L9 |, A1 c; l5 CCmdLine: netrev -$ -5 -i D:/CadenceWork/HongelDM642/PCB/allegro -x -y 1 -z D:/CadenceWork/HongelDM642/PCB/#Taaaaaa00436.tmp
4 P$ [+ J9 y$ M+ h8 j( a2 ~------ Preparing to read pst files ------
- Q) F! t+ z( |# s. HStarting to read D:/CadenceWork/HongelDM642/PCB/allegro/pstchip.dat
~5 y# j9 G# u- ^: e. J3 @ Finished reading D:/CadenceWork/HongelDM642/PCB/allegro/pstchip.dat (00:00:00.04)3 ?& h( Y# {3 y5 c/ d& @9 ~$ |' b2 [5 ]
Starting to read D:/CadenceWork/HongelDM642/PCB/allegro/pstxprt.dat , l' `4 P* @: x
Finished reading D:/CadenceWork/HongelDM642/PCB/allegro/pstxprt.dat (00:00:00.01)( d" J. F# h* X6 F0 d
Starting to read D:/CadenceWork/HongelDM642/PCB/allegro/pstxnet.dat 5 l/ V5 d3 \/ b# Y0 j* U6 L# j, H p/ }
Finished reading D:/CadenceWork/HongelDM642/PCB/allegro/pstxnet.dat (00:00:00.03)
. P8 V' i. @% ~# v5 z- E------ Oversights/Warnings/Errors ------% |/ Z& I z* H% @3 D
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#1 ERROR(102) Run stopped because errors were detected
* Y# Q( y1 a5 [netrev run on May 12 21:32:04 2010# s+ `- Y \9 ^( w+ R1 p
DESIGN NAME : 'DM642_PRJ'
9 _/ z/ |8 D" `1 Z+ b PACKAGING ON May 28 2006 22:05:314 S! f. X3 k& e" h9 c) D8 A' C
COMPILE 'logic'
( b+ Q4 x9 x4 w CHECK_PIN_NAMES OFF
$ l4 W8 U& u! W, a' w& w CROSS_REFERENCE OFF8 \) w* J8 c" f. {
FEEDBACK OFF
# |0 }; [* u5 @; }5 r# O! c& | INCREMENTAL OFF
1 Y& o/ g7 F, t INTERFACE_TYPE PHYSICAL E; V9 @% y2 J( M
MAX_ERRORS 500
; ]3 O6 P5 Z* B! J1 g0 ^ MERGE_MINIMUM 5' m3 b: Y3 D8 A Z
NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'8 n; c2 [4 j$ {2 ]5 S% }9 `" Q
NET_NAME_LENGTH 24+ w. R. [0 s& ~ u# m$ l( m& D
OVERSIGHTS ON& Q8 a. }9 T% f
REPLACE_CHECK OFF
; O7 b/ z8 `. N SINGLE_NODE_NETS ON
' l- E5 p/ W5 l SPLIT_MINIMUM 0
9 i8 W% ^! @; Q1 e0 y% J SUPPRESS 206 j g5 w8 r* _) m+ z( |8 Q5 G. [
WARNINGS ON
4 h8 d5 }6 j$ \7 u" E 1 errors detected
) F0 R! L, f( B No oversight detected0 _* ?2 s5 m6 U* q
No warning detected
' Y& j7 }& h. rcpu time 0:02:36
# V3 N: w& B5 E0 L+ x0 M+ n3 |9 ielapsed time 0:00:01 |
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