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DATE: 04-23-2010 HOTFIX VERSION: 007
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+ G2 e. i3 Q1 `2 Q- sCCRID PRODUCT PRODUCTLEVEL2 TITLE( r" w% v- e- P5 w' I
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721859 ALLEGRO_EDITOR OTHER update shape to smooth creates tmp file on remote file server working dir why?0 i' X7 E7 |0 V5 D5 h
740201 SPECCTRA_MENT_ IMPORT Wrong stackup order after translating from mbs2sp3 q: l+ g$ l- Y+ \
744797 SIP_LAYOUT OTHER Cannot Copy a connector (IO) symbol in APD and SiP tools: a4 J4 s* a+ l
747831 CIS CONFIGURATION There is a delay of 5 to 10 mins in opening SQL database in V16.2 and V16.3. It is fine in V16.0.
6 e: U% u% u, \3 G0 R& r/ M747848 CIS CONFIGURATION Unable to configure CIS with Oracle database due to Capture crash., h' Y, e7 L/ o4 ], j
751372 CAPTURE OTHER Copy / Paste Issue in capture 16.3
; M5 T; X) h& t, [; c$ Z: c757434 ALLEGRO_EDITOR MODULES Allegro hangs the board file after creating Placement Replicate circuit.
1 F* m7 u+ F+ V759906 CIS PART_MANAGER Property copy from one to several parts doesn't work2 J* I4 D' P5 F, Z" z
760154 PSPICE NETLISTER Model parameter (Tj) is not affecting Smoke Analysis result
( u1 C. b; q+ j# A+ T7 D+ M' E761177 CIS OTHER Error Message - Memory exhausted
1 x1 C$ @- t% i762602 CIS EXPLORE_DATABASE CIS doesn't open datasheet for parts if it is not stored at default Capture location.
( }; w( K: H! u& g8 s1 u763677 APD EDIT_ETCH The "Via to Via Line Fattening" tool is inconsistent in which clines are changed.
% E+ y8 b' ^. z! d763715 CAPTURE NETLIST_OTHER A long pin name gets truncated upto 31 characters when the wirelist is created.
7 j. G8 }7 g; N' l; o" l763878 CONSTRAINT_MGR DATABASE Why Pinpairs disappear after closing Constraint Manager?
7 v% D. t9 ]# l3 v% u# U764020 CAPTURE NETLISTS Usernetl.dll has changed between 16.2 and 16.3
6 E; |5 w9 }$ g2 w/ n5 G; n764101 APD EDIT_ETCH Perpendicular routing through a Region does not work when the region segment is drawn at an angle. h/ e# q- X" X6 J. ^) x* D
764200 ALLEGRO_EDITOR DRC_CONSTR Via at smd fit drc on a via that is placed fully inside the padstack having custom pad
( O0 U. {, H1 W, `- C' t764903 PSPICE ENVIRONMENT 'Run in Resume Mode' does not work in SPB 16.35 N( J1 R- L0 @& G
765206 F2B PACKAGERXL Unable to feedback subsequent pin swaps from Allegro
6 k( e Z$ X* @0 A0 E765319 APD DRC_CONSTRAINTS Identical Constraints in Performance Advisor question2 {; y4 p6 m. a4 [# @
765541 SIP_LAYOUT SHAPE Set via oversize value to 3 in dynamic shape instance parameters will make overlap shape.
/ B8 n! j: H+ y766147 APD EDIT_ETCH Resize/Respace Diff Pairs does not work on 45 and off angle
. C1 h* V# A# v8 }5 v L' u766337 SIG_INTEGRITY GEOMETRY_EXTRACT Geometry of Via model Extracted from board file is not identical to Original Via geometry design& y9 N* J) M% S6 H8 l
766443 ALLEGRO_EDITOR PADS_IN unable to translate PADS ascii to brd in 16.3
4 `, J e; M! {) n7 d! M' B* n$ G766581 CIS CONFIGURATION In 16.3 capture.exe remains memory-resident after exit: Y9 U2 }( f- M* G% P7 n' q
767161 ALLEGRO_EDITOR SHAPE The behavior of Add Fillet command is different by Hotfix version.
5 K! @6 f9 S, _) J2 d \767217 SIP_LAYOUT IMPORT_DATA The Die-Text In wizard and it is crashing on the "Finish" step.
6 e# U1 {% j4 m G T# J9 F767598 SIP_LAYOUT WIREBOND Can't wirebond SIP designs as it just hangs.6 w2 Q: l! J* M* ?8 a8 R
767832 ALLEGRO_EDITOR DRC_CONSTR Reducing Design Accuracy updates Physical Diffpair constraints wrongly
6 ?/ H( x. a/ _! ~ g b768822 ALLEGRO_EDITOR SKILL axlSetParam return value is divided by 10 to the power of the design accuracy.
; x% ?- o1 I# h, \+ P) p769150 CIS PART_MANAGER Update All part Status on a group changes 揇o Not Stuff?status to 揝tuffed?in V61.3_ISR_5.5 g r* H2 [; X6 Q- i- Z# W+ H
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发表于 2010-4-19 21:07
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