C@dence.SPB16.20.winnt.Hotfix.001和002所更新的内容

zlei

HOTFIX VERSION:  002
$ |: p/ C9 c+ C( n1 u/ ^" I========================================================================================================
CCRID      PRODUCT          PRODUCTLEVEL2        TITLE
========================================================================================================
  A2 G6 l9 Z+ D( v- N. ~! f9 G) x511865     SPECCTRA         REGIONS              Diff pairs should adhere to constraint area
& g8 j4 ?" I- ]9 U) Z( `564589     ALLEGRO_EDITOR   OTHER                The show measure command should show the actually measured po
570861     CONCEPT_HDL      CORE                 Unconnected mark does not be removed even after wire is conne
572188     APD              PAKSI_E              3-D model extract failed
; ?3 ^5 I# v! `6 M578164     CONCEPT_HDL      SKILL                Cnskill crash during Create Test Schematic step when large pi
578874     SIP_LAYOUT       DIE_STACK_EDITOR     Stackup editor in SiP fails to add layers above and below top
5 s9 l( m) c" j580315     APD              ETCH_BACK            Etchback trace fails with error "W- An etch-back trace cannot
582308     ALLEGRO_EDITOR   OTHER                Create Detail for bondpads rotated at (0,90,180 and 270) angl
594370     SIG_INTEGRITY    OTHER                Wrong description in case update form when changing preferenc
595755     CONCEPT_HDL      CORE                 Rumtime error happen when do Move Group in conceptHDL
5 y$ ]1 E' _) `1 I& e597922     SIG_INTEGRITY    TRANSLATOR           spc2spc doesn not handle inline RLGC DATAPOINTS
  J7 G9 d) _9 ]' Y, r606620     ASSURA           DRC                  Problem with density checks in Assura
  d' s$ ^4 N- s2 C! g609866     SCM              SCHGEN               Schgen replaces CTAP with COMMENT symbol which causes net sho
0 V5 S; ?& \8 w$ @611678     ALLEGRO_EDITOR   GRAPHICS             During Place > Manual Pins disapear if component is on bottom
615630     ALLEGRO_EDITOR   GRAPHICS             Pins are not visible when place manually is used for Bottom s
: m2 q) q( ~, c& u( ]6 Z8 X$ X615764     CONSTRAINT_MGR   TDD                  BOM report does not filter parts with BOM_IGNORE
7 L, f3 U' Q. _% T616529     CONCEPT_HDL      CORE                 15.7 Design Entry HDL fails with Out of Memory message
. m: E( _, S) C4 G! {3 |) f( z616928     CONCEPT_HDL      CONSTRAINT_MGR       Net_physical_type and net_spacing _type constraints not sync'
617441     SIG_INTEGRITY    FIELD_SOLVERS        Reflection simulation fails when using wideband vias
617679     ALLEGRO_EDITOR   COLOR                The color palette will not be saved with the design unless co
617805     CIS              PART_MANAGER         Capture_crash
618988     ALLEGRO_EDITOR   SCHEM_FTB            Long bus names being truncated
619588     APD              EDIT_ETCH            Poor routing performance. 5 second delay after each mouse cli
$ S% [* o. H. a+ K. F619691     SIG_INTEGRITY    FIELD_SOLVERS        Problem of EMS2D by using FreqDepFile
619867     ALLEGRO_EDITOR   DFA                  DFA_BOUND_TOP shape doesn't display DFA Audit conflicts
( y1 b1 E$ y4 k7 @# r1 y8 |6 y. Q620359     CONSTRAINT_MGR   CONCEPT_HDL          ECSet and Netclass definitions lost in the FTB process
7 [& E5 |' j% F5 P620424     CONCEPT_HDL      CONSTRAINT_MGR       CM restore from definition of subblock removes ECSets defined
/ ~4 T9 k( x* `; S' f620700     ALLEGRO_EDITOR   PAD_EDITOR           Shape has bigger void on Y direction for Oblong SMD Pads
620868     SIG_INTEGRITY    PAKSI_E              Wirebond material conductivity is not used by PakSI, only a d
620895     ALLEGRO_EDITOR   DRC_CONSTR           About error message of cns_design command.
620924     CONCEPT_HDL      OTHER                PDF Publisher 16.1/16.2 can not output some Japanese characte
621156     SIP_LAYOUT       ASSY_RULE_CHECK      ADRC Rule for 揟race Minimum Angle to Pad?not showing all th
621163     SIP_LAYOUT       ASSY_RULE_CHECK      Ambiguity about the how is the 搒tart of the wire" defined in
621298     CONSTRAINT_MGR   UI_FORMS             PCB SI crashes when importing a constraint file into Constrai
; E/ Y- L- t3 x$ G621315     ALLEGRO_EDITOR   PLACEMENT            Getting wrong component when using Place replicate unmatched
8 @* P+ T* V. a: d621848     CONSTRAINT_MGR   TECHFILE             techfile write fails with Failed writing object attributes
& z0 C7 W6 p2 S6 |621867     ALLEGRO_EDITOR   TESTPREP             Transcript window randomly locks up when running TestPrep
6 E, e- b' ]- d- @, I+ {" v0 Y621901     SIG_INTEGRITY    OTHER                Incorrect extracted via drill/pad diameters and missing inter
622010     ALLEGRO_EDITOR   DATABASE             Undesired openings in Negative shape
0 v8 y5 ]5 Z+ H8 V2 |- J622062     CONSTRAINT_MGR   DATABASE             Importing dcf file at system level crashing the Allegro PCB e
4 L1 N; {! o. \% l! \1 U9 M622156     ALLEGRO_EDITOR   SHAPE                Thermal/Anti value producing incorrect void sizes
622450     SIG_INTEGRITY    SIMULATION           Field solution failed
7 v3 ~7 P8 }2 Y. Q4 O622466     ALLEGRO_EDITOR   COLOR                layer priority in 16.2
622566     ALLEGRO_EDITOR   SCHEM_FTB            Replacing the components of same refdes on board after import
  E4 ]; t) y! {- h$ \& c/ ^622700     APD              PLATING_BAR          Plating Bar Check is highlighting Nets that appear to be conn
" f; X7 s4 h% S% D" @622862     ALLEGRO_EDITOR   ARTWORK              Allegro crashes when we enter a value in the field file size
622989     SIP_LAYOUT       IMPORT_DATA          Type of Wirebond die changed after die import
' i3 p( ]. {. y623182     SIG_INTEGRITY    FIELD_SOLVERS        Extract topology crashed
623300     SIP_LAYOUT       3D_VIEWER            Wrong placement of Solder Mask Bottom in 3D view file
623384     ALLEGRO_EDITOR   VALOR                Valor output showing padstacks on 45 degree angle wrong in 16
623489     ALLEGRO_EDITOR   EXTRACT              Allegro tools Report etch length by pin pair takes forever to
) B" U" D, R$ ^1 O0 m% e' z623529     ALLEGRO_EDITOR   EDIT_ETCH            Manual tandem diff pair routing has been lost in the 16.2 rel
1 q6 u5 d) D  A5 Y5 b623536     F2B              PACKAGERXL           packager fails with memory allocation error
623673     CAPTURE          OTHER                Unable to get capture window size to full-screen in dual disp
623701     ALLEGRO_EDITOR   OTHER                'Analyze' menu missing when opening Allegro PCB Editor L - Pe
623738     CAPTURE          PART_EDITOR          Create part from spreadsheet is not working correctly
623740     ALLEGRO_EDITOR   OTHER                Can we use variant.lst file as list file in find filter
623745     CAPTURE          OTHER                Capture crashes when the user tries to place markers
623813     SIP_LAYOUT       WIREBOND             Add wirerbond only is not working in this case with a bondfin
. L% A3 v) ?7 b/ e/ z623830     ALLEGRO_EDITOR   MANUFACT             backdrilling is drilling through component pads on the bottom
4 C& f/ L( H) E+ w+ P) R' o624048     ALLEGRO_EDITOR   OTHER                Viewlog for Export to 16.01 is not closing from any of the 'C
624223     ALLEGRO_EDITOR   GRAPHICS             disable_datatips variable is busted
624495     ALLEGRO_EDITOR   SHAPE                Static shape did not void to drill holes
: @$ Y! S* j; \  ~624599     SPECCTRA         ROUTE                PCB Router hangs on route of design
624653     APD              BGA_GENERATOR        BGA Generator fails at 400um pitch
624812     CONSTRAINT_MGR   ANALYSIS             Importing dcf at the system level causes RPD constraints not
% N1 W, J7 b: ~2 W5 `) J7 ?624888     ALLEGRO_EDITOR   DRC_CONSTR           Regions and RCI's Cset not working as expected
4 \& I5 R$ h5 L( I% `8 ~# p; {624958     ALLEGRO_EDITOR   EDIT_ETCH            Slide in region is changing etch to min line width
625251     ALLEGRO_EDITOR   COLOR                16.2 Linux allegro - new subclass created does not reflect in
625273     APD              IMPORT_DATA          Import a .mcm into SIP in order to edit the die pins. Edit ->
625279     APD              DIE_EDITOR           die text in fails when the function name is >31 characters wi
625304     SIG_INTEGRITY    IRDROP               Need a better understanding of absolute current values report
625367     ALLEGRO_EDITOR   DRC_CONSTR           drc_fillet_samenet does not work correctly
% n% D  ^3 q: D' g: W6 Q625551     ALLEGRO_EDITOR   SHAPE                Dynamic shape is not voiding to route keepout correctly
625852     ALLEGRO_EDITOR   DRC_CONSTR           Some buses in CM are disappeared after import CIS 3 .dat netl
625885     CAPTURE          DRC                  Report misleading Tap connections check for DRC reports error
625972     CONSTRAINT_MGR   TECHFILE             techfile import fails with Failed writing object attributes
626630     CAPTURE          NETLIST_ALLEGRO      Capture 16.20 hangs endlessly but Capture 16.0 prompts result
1 a( |$ F0 J" b& V626669     SIP_LAYOUT       OTHER                16.2 radial router find filter does not have option for bond
626671     SCM              OTHER                Adding signals in ASA is taking too long
627228     ALLEGRO_EDITOR   MANUFACT             Dynamic Fillet is disappered, when use slide command.
0 k) ]$ a( i/ C! a! t" o" B627289     SIP_LAYOUT       DIE_GENERATOR        Pins connect at the same net name after Die Text In
627864     CONCEPT_HDL      EDIF300              EDIF c2esch crashes
+ e" ^9 j" t, Y4 o) N$ q5 O: E: W' J628169     ALLEGRO_EDITOR   OTHER                write command changes design name in constraint manager
628220     SIG_INTEGRITY    SIMULATION           Reflection simulation failed with filed solver "EMS2D"
628261     APD              OTHER                no "Tangent Via Line Fattening" in APD products
2 h% Q! w9 t& n4 c628922     APD              REPORTS              Metal Area Report shows 0.00 on one layer
9 d( L! N5 o! j) l; x* JHOTFIX VERSION:  001
6 r, x" M6 b( t2 v+ B========================================================================================================
CCRID      PRODUCT          PRODUCTLEVEL2        TITLE
% q* s5 f$ v. x. A) X3 y========================================================================================================
191020     ALLEGRO_EDITOR   SHAPE                Shape edits results in same net DRC being reported.
% K; I2 j) u% }, n230469     ALLEGRO_EDITOR   SHAPE                Allegro improve performance of Dynamic Shapes
295039     ALLEGRO_EDITOR   DFA                  Allegro DFA to be enhanced to include height
3 Y2 b  E- U8 k" l9 ~$ |/ p/ q346863     CIS              DESIGN_VARIANT       Variant View mode is not working for multi-section parts
400036     CONCEPT_HDL      HPF                  nihongo_vector_font should be listed in the Plot Setup GUI
% _! o/ @+ X' p+ o3 T- Z6 m1 a410092     CONCEPT_HDL      OTHER                The Imported sheets loses the write permission for the group
) R2 ~' s& ]' F3 @) j415462     CONCEPT_HDL      MARKERS              The SPB157 Markers does not normally display the Japanese fon
501802     ALLEGRO_EDITOR   GRAPHICS             When hilighting parts or nets the system is inconsistent on z
9 `+ z. z$ F( e' g0 \' }' N. N8 l503526     SPIF             OTHER                SPIF is NOT defining class for class to class rules.
511175     CONCEPT_HDL      CORE                 Copy All causes - No object selected error
526774     LIBRARY          DEVELOPER            Pin抯 text size goes back to default size after change pin na
8 y& ?% ]) |/ D  b533536     CONCEPT_HDL      OTHER                The font used in published PDF is not identical.
; v) \6 k! P7 J9 ]537769     CONCEPT_HDL      CORE                 Sporadic behavior of DE HDL toolbars for adding components ge
" |- k# f+ q6 {( t1 q: y7 A544519     ALLEGRO_EDITOR   MENTOR               mbs2lib Generating extra "b" version of footprint during tran
. _7 g( I* A% A2 j& }1 T8 b551528     LAYOUT           OTHER                Layout2Allegro L2A translator not translating reference desig
; |' a' ]+ M. M' T1 }2 w* X, R" f551614     SIG_INTEGRITY    IRDROP               Import and export of IR-Drop setup
" M# u$ ^0 ^" F4 S, u552127     LIBRARY          LIBUTIL              When -lib is missing from con2con PTF files get re-written in
8 J' v. x& t1 x5 O' q4 O2 U* _560417     ALLEGRO_EDITOR   OTHER                Part Logic does not read part row from ptf file and assign in
3 m+ T6 W0 K/ l5 H564954     CONCEPT_HDL      CREFER               Crefer attaches $XR property to other $XR on RHEL.
" Z% r! H0 |; ^5 m: i565798     CIS              DESIGN_VARIANT       all the sections of mult part package are not coming as DNS i
, }. O- ~) E( D" E, B* V571627     CONCEPT_HDL      CONSTRAINT_MGR       cmuprev fails to synchronize constraints on low assertion vec
# f4 ]4 H5 P; t0 `; l0 d577915     CONCEPT_HDL      ARCHIVER             zero folder is not archived how the archiver is working ?
581446     LAYOUT           TRANSLATION          L2A fails with pin numbers do not match between symbols from
( q8 p3 {& w9 t8 w9 z' h1 N583891     ALLEGRO_EDITOR   MENTOR               Mbs2brd will not run with PA5630 license (Allegro PCB SI GXL)
5 P9 i$ V) I1 O586998     ALLEGRO_EDITOR   PLOTTING             Board shifts towards top left when plotting at higher resolut
0 @! l" I, X- W7 l$ x% O) b3 x587870     ALLEGRO_EDITOR   PCAD_IN              Import PCAD fails due to dupliate pad name.  Caused by a peri
( F! j6 c* ^! |1 X: o& V* p588949     CONCEPT_HDL      CORE                 Importing schematic pages from another project crashes Concep
592340     ALLEGRO_EDITOR   MENTOR               MBS2LIB not creating the correct shape in symbol
# s0 f# p; d6 c$ X. ^. W, f596530     ALLEGRO_EDITOR   PADS_IN              PADS to Allegro Translator removing/renaming reference design
8 Z" y/ c) y! _& W2 {0 Q596638     ALLEGRO_EDITOR   EDIT_ETCH            The timing meter indicates untruthful violation
% @+ p3 e, i  W596716     PSPICE           DEHDL                Flag error due to part pin mismatch while create netlist
9 O4 i5 K3 A1 p* F+ @597685     ALLEGRO_EDITOR   SCHEM_FTB            ratnest are out of date error in DBDoctor after import logic
597937     ALLEGRO_EDITOR   PADS_IN              Request PADs_in to translate keepout areas
598575     ALLEGRO_EDITOR   OTHER                During Split plane should it use settings regarding fill styl
' }& S! O7 f# H" |  ^) s4 o598814     APD              WIREBOND             bondfinger does not move relative to its origin using ipick
599823     CONCEPT_HDL      CONSTRAINT_MGR       Lost ref to dml-lib causes loss of cm data even if the refere
599886     APD              EXPORT_DATA          bodygen batch tool is failing to generate .css file
. Q( G& K2 W% f3 X/ n- A' t& E( N603425     SPECCTRA         PARSER               Do file fails Syntax error in command unexpected end-of-line
; i" ^3 ^/ h& U2 V! x! ~7 p$ e603987     APD              OTHER                Offset via generator should ensure pitch distance is met or e
7 d& P; i# R8 H7 V6 M0 y  ?4 s: X604377     SCM              PACKAGER             Output board name containing a dash causes scm crash
604614     CONSTRAINT_MGR   OTHER                netrev is unable to update the Canonical paths with the new d
604794     ALLEGRO_EDITOR   PAD_EDITOR           Replace Padstack reports error pad missing not true.
# @! `% i% n( A( u8 h605169     ALLEGRO_EDITOR   OTHER                Can design_compare handle swappable pins?
# y, e/ u$ h& M7 h606586     ALLEGRO_EDITOR   INTERFACES           Multiple drill in padstack cannot be shown in Pro/E IDF
607217     APD              IO_PLANNER           wirebond die replacement from IOP
5 y  b$ ^& h3 l( \607222     APD              WIREBOND             auto wirebonding creates wirebond with DRC
$ B5 _$ p0 m$ B2 w) [- s607644     ALLEGRO_EDITOR   MANUFACT             Enhancement to increase the IDF export ''default package heig
607718     CONCEPT_HDL      HDLDIRECT            HDL Direct Errors reported while generating simulation netlis
8 Y( Y# O. w8 f( H, x8 }! p608233     SIG_INTEGRITY    FIELD_SOLVERS        Convergence errors with analytical vias when drill size is 1
& ?7 w0 s1 `- c# r* z) F' T* h. z9 R609549     ALLEGRO_EDITOR   INTERACTIV           Mirror Geometry command to change BB Via's layer.
610028     SIP_LAYOUT       IMPORT_DATA          De assign NC nets during aif import
610134     CONSTRAINT_MGR   INTERACTIV           Cross-probing from CM to Allegro no longer works on system le
610276     ALLEGRO_EDITOR   PADS_IN              PADS to Allegro translation is failing with error.
610482     ALLEGRO_EDITOR   SCHEM_FTB            Netlist swapped net names on 2 pins causing shape to lose its
  e; ]! e! C- i3 C610681     CONSTRAINT_MGR   DATABASE             An exported constraint file can not be re-imported in V16.01
* s6 t5 L: C9 V" R% {& ?611260     ALLEGRO_EDITOR   DRC_CONSTR           Routing a diff pair it does not follow Physical line width se
611425     ALLEGRO_EDITOR   MENTOR               mbs2brd crashes when importing Mentor
611697     SIP_FLOW         SIP_LAYOUT           octagonal bumps have offset in SIP compared to the chip view
7 g! T7 p/ {  _6 M6 N611807     APD              WIREBOND             Duplicate paths created on wirebond import for some cases.
# x/ Q8 W2 B. N6 h7 z( p2 ^611856     CONCEPT_HDL      GLOBALCHANGE         Ref des deletions after runnning Global Change to change $LOC
611874     CONCEPT_HDL      OTHER                Crossprobing one symbol in Concept using Occurence edit mode
# X$ k7 t( f! A, A612088     PSPICE           DEHDL_NETLISTER      Fail to create the netlist for G value expression
612195     ALLEGRO_EDITOR   DATABASE             Adding layers to the default cross section causes phantom tex
. T3 T; y; g/ r9 Q( _612237     ALLEGRO_EDITOR   SKILL                axlFormColorize does not change the full background area of a
- R' {  e: X& |- H# _1 T% @$ Q612299     APD              DEGASSING            Degassing static shape creates voids inside of voided areas
, e5 M4 k! O/ w( Z. I5 C- @! |612560     CONSTRAINT_MGR   OTHER                Diffpairs don't show the CSet assigned through Net Class
1 R% _7 z' D. W: ~7 [612587     APD              WIREBOND             Unchecked Allow DRC option creating disconnected wire bond.
612884     SIG_INTEGRITY    SIMULATION           When using ViaModel
# o+ W1 p7 d3 c. m- Z612914     ALLEGRO_EDITOR   EDIT_ETCH            Centered via option in fanout command not available when swit
612939     SIP_LAYOUT       ASSY_RULE_CHECK      ADRC Continuous Solder Mask check problem
# }; z0 G1 A& E613553     CONCEPT_HDL      EDIF300              edif schematic writer crash on this design
613565     ALLEGRO_EDITOR   EDIT_ETCH            Allegro Editor Differential Pairs are routing incorrectly
# Y& W/ }; H% f' l! ~# y: y1 X613736     SPIF             OTHER                Spif fails to write class data
613990     POWER_INTEGRIT   INTERACTIV           PI is crashing during capacitor selection
8 E, O6 {1 P1 w3 d1 k: I614278     CONCEPT_HDL      EDIF300              pin text note and flag are not visible on reloaded edif file
& V9 V+ |7 i8 u) e. ~! a614371     SIP_LAYOUT       WIREBOND             Any wirebond command crashes the application
8 i3 r& {1 f9 `$ o4 t9 W614407     POWER_INTEGRIT   INTERACTIV           PI crashes when editing capacitors
614727     SPECCTRA         GUI                  Allegro PCB Router can not process the dsn and rules file for
, k: j. T" u$ q& w- E- K" |1 X' V& x614972     ALLEGRO_EDITOR   SKILL                axlCNSSetSpacing does not change the value of the "testvia to
615144     SIP_LAYOUT       3D_VIEWER            die placement does not change with changing in soldermask thi
, p6 L+ O: r. e5 C* t9 x( x3 V8 Q615431     LAYOUT           TRANSLATORS          padstack names are crippled or renamed if it has over 18 Char
- `7 v7 J+ s% V5 q+ `615506     APD              MANUFACTURING        Sort by die pin location for Manufacture Doc Bond finger brok
4 g$ I0 o$ K5 Q8 s2 X615745     SIP_LAYOUT       DATABASE             Move die symbol with stretch etch on is disconnecting wires f
) m( z: e: G, j- p6 ]# X% e1 g. W615816     SPIF             OTHER                Allegro match group members not translating to PCB Router; mi
616104     CONSTRAINT_MGR   OTHER                allegroTechnologyFile XML format issue
0 D; f& D  _6 w3 _- E* _8 @: ~3 F616122     LAYOUT           TRANSLATORS          Protel to MAX translator problem with package outlines and re
616404     ALLEGRO_EDITOR   OTHER                Design compare fails with message "Invalid input argument" wh
616713     CIS              PLACE_DATABASE_PAR   property name with "&" charecter in access database causing c
616818     SCM              PACKAGER             BOMHDL -type scm fails on schematic block
616907     SCM              VERILOG_IMPORT       scm crash during Get Module Name
617058     APD              WIREBOND             wirebond space evenly does not work for fingers on power ring
617083     ALLEGRO_EDITOR   INTERACTIV           Windows tabs hangs on Linux
& m# D( w6 F2 h: f617236     ALLEGRO_EDITOR   SHAPE                Editing a shape in a void causes the bigger shape to drop seg
617351     CIS              DBC_CFG_WIZARD       XML writer fails if DBC location doesnt have write permission
617515     SIP_LAYOUT       OTHER                Be able to invoke Velocity from cdnsip
617761     LAYOUT           TRANSLATORS          Value property for Library symbol of Orcad Layout is not tran
. ?! \/ E) f8 t- i# p$ K" k: M617890     SIP_LAYOUT       WIREBOND             Push and shove on Bond fingers with multiple bond wires cause
618184     APD              OTHER                database diary on unix/linux
618201     ALLEGRO_EDITOR   OTHER                Dynamic fillets take a long time to complete
6 n( {- M6 Z2 V8 x4 R618545     ALLEGRO_EDITOR   INTERACTIV           Allegro crashes when we place a package symbol for Jumper usi
, W( C2 J, D  R618610     ALLEGRO_EDITOR   MANUFACT             Delete a cline seg creates a fillet
618651     SIP_LAYOUT       IO_PLANNER           Bondfingers and die are shifted every time an update package
" F  \% _* l, b$ U1 U618712     ALLEGRO_EDITOR   EDIT_ETCH            Shove mode is not working on Diff pairs in PCB Design L
618836     ALLEGRO_EDITOR   SCRIPTS              Allegro does not interpret recorded macro script files proper
3 u$ H# Y$ m$ K618946     ALLEGRO_EDITOR   INTERACTIV           Allegro crashes while using Place Manual -H
6 y  \" j2 v4 m/ ?& b0 N2 }2 h618984     ALLEGRO_EDITOR   COLOR                Layers on Allegro Canvas does not match Color Dialog Box
619007     ALLEGRO_EDITOR   SKILL                Skill command does not accept spaces in file path/name
4 V: M  c& ]. B( n9 s( v# L9 s$ K7 G619033     F2B              PACKAGERXL           Pinswap lost on backannotation
4 F3 {( \! D, S. p619268     POWER_INTEGRIT   SIMULATION           IR-Drop can't sees via on pad as open
619356     CIS              FOOTPRINT_VIEW       Footprint preview only from 1 directory in Capture.INI
- a/ L( f% @) C" O  \, O# v0 l619712     ALLEGRO_EDITOR   EDIT_ETCH            Unable to route in the Bubble Mode for Partitioned board
$ v. M3 I% h* s# Q- k, S& b619773     ALLEGRO_EDITOR   DATABASE             Uprev for 13.6 and 14.0 files not working with SPB 16.2 on Wi
620064     CONCEPT_HDL      CONSTRAINT_MGR       Loosing Diff pair constraints from lower blocks when packagin
622132     CAPTURE          NETLIST_ALLEGRO      Incorrect ALG0078 error for complex hierarchical design