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高速数字信号设计和高速互连1 P# d8 ~, |% p+ B% P, |
CHAPTER 1 Transmission Line Fundamentals.......................................... 1
" G0 M1 t3 ]) J$ hBasic Electromagnetics.................................................................... 17 t8 l9 j0 i7 L0 f
Electromagnetics Field Theory................................................... 15 g3 z5 t' s% T' I9 U2 E
Propagation of Plane Waves....................................................... 6" A' K" [1 m, O. l) c
Transmission Line Theory............................................................. 10" T3 M, }' r8 ?: U! B; c
Wave Equations on Lossless Transmission Lines.................... 11
/ S% k- Y, H5 c# p7 Q4 G" N9 y7 h) SImpedance, Reflection Coefficient, and Power Flow
3 Q3 _! j! J0 m% {9 oon a Lossless Transmission Line......................................... 14
$ g' g3 @; i; T0 ]. A4 JTraveling and Standing Waves on a Transmission Line ......... 16
7 O" {# D1 Y" J: sTransmission Line Structures ........................................................ 18
. t. \2 n. i( S4 ^- BStripline ..................................................................................... 19
* Z @( O# N2 XMicrostrip.................................................................................. 20
* m* I0 z7 V& HCoplanar Waveguides ............................................................... 21( C! c: p# Y/ w4 d* i
Novel Transmission Lines ........................................................ 223 J$ M) p2 |) t. B. U( {3 }; i
References ...................................................................................... 26
. H# `0 C U: h6 U/ @CHAPTER 2 PCB design for Signal Integrity........................................... 27
) W8 l6 \6 ?$ [* j9 m6 H' CDifferential Signaling..................................................................... 27
9 H" C) O. ]4 \# a2 V; y1 xImpedance ................................................................................. 28
8 b8 W; T* X+ A% T+ d$ ]Time Domain Analysis .................................................................. 31% h( b( d( {. L* R/ z4 ]6 N4 p6 k
Eye Diagram ............................................................................. 310 z+ p9 Q8 q# y5 a: f/ Z+ ^4 L' k- `, q
Jitter........................................................................................... 33( J9 F$ }& W2 u3 Q8 F
Frequency Domain Analysis.......................................................... 42
& J" [; l+ n7 ^, u9 k2 OSpectral Content........................................................................ 425 L2 f' D8 J: A% o# G% c
Insertion Loss............................................................................ 442 D5 H: D3 p: F* s
Integrated Insertion Loss Noise................................................ 46
) s1 F/ g8 Q5 \+ d2 D, w+ Z6 ?Return Loss ............................................................................... 49
3 y% i @0 ~( |7 d; [+ s4 K, M% }Crosstalk.................................................................................... 51. K) T( b$ R( ?+ }6 Q
Integrated Crosstalk .................................................................. 54/ ?4 n, j3 V5 }9 K
Signal-to-Noise Ratio................................................................ 55
# |1 E3 j: C0 z0 T* N$ s' EStack-Up Design ............................................................................ 58
1 c, p/ w, }% u% IImpedance Target (Routing Impedance) .................................. 59
8 | I$ h# p7 |2 C5 HPCB Losses ............................................................................... 612 K3 {$ [* Q8 t9 k" z7 [; [
Dielectric Loss .......................................................................... 62& \2 F9 y5 {9 z) G& Y' W- }
Conductor Loss ......................................................................... 657 b9 s% p: H: p& B- X9 D
Crosstalk Mitigation through StackUp..................................... 68% A, Y) m m9 o. |
Dual Stripline ............................................................................ 73
5 W/ u4 R; |+ ?- }) p- y4 Cv
" Y6 M* u0 X6 |" |8 HDensely Broadside Coupled Dual Stripline.............................. 84- _4 [+ {' h8 K" p: W
Via Stub Mitigation .................................................................. 86" h7 c, W) E# x6 v0 Z
PCB Layout Optimization ............................................................. 95
* z5 A U" W1 X% m# iLength Matching....................................................................... 96
* ^6 M. T' |) b0 F! |Fiber Weave Effect ................................................................... 998 W" f# R2 ^4 [
Crosstalk Reduction ................................................................ 101$ H/ ~$ J9 A/ o& {
Non-Ideal Return Path ............................................................ 107# w' N, p( I/ ]4 P9 [
Power Integrity........................................................................ 110# z: w$ G; g' W. Q0 @% l& |" ^
Repeaters ................................................................................. 111
( R8 o3 D* N6 ^/ n# E3 {8 xReferences .................................................................................... 115
' M' l8 ]- J$ \4 E8 [7 i/ f" }- N9 VCHAPTER 3 Channel Modeling and Simulation.................................... 1176 B+ Z7 ]0 ^' S$ s' z0 T
Transmission Lines ...................................................................... 117; v2 |: @. k' p, F, v: i
Causality.................................................................................. 117 C% X8 [( g4 _
Checking for Model Causality................................................ 1183 S( }0 w+ ], W
Causal Frequency-Dependent Model...................................... 120
/ Q$ `* @$ R, J" h1 XCopper Surface Roughness..................................................... 121% i4 G$ h! e) m# s
Conductivity............................................................................ 126 B& d' z1 H' l4 q2 C; ?' R3 n" g
Environmental Impact............................................................. 127
, V* a9 N" X. p+ P# N6 X' J8 oModel Geometries................................................................... 130: f- r% \) w( F) |
Corner Models......................................................................... 133
2 o' s% ~& I' Q. e) F+ OIdeal Assumptions: Homogeneous Impedance....................... 137
3 w6 P. M8 b" jIdeal Assumptions: Crosstalk Aggressors .............................. 137
- M7 P, c# | i$ t8 ]3 V3 [Transmitters.................................................................................. 138
# G3 S7 Q# \- E1 ~ z/ ~IBIS Models ............................................................................ 138
5 v( k; P9 ?8 K f! `) mSpice Voltage Source Model .................................................. 139
+ y' a1 x7 u8 o3D Modeling ................................................................................ 141
+ l. {) f0 D( t$ ?2 K8 QPorts/Terminals ....................................................................... 142
( s1 v! e3 C/ A! bModel Analysis Settings ......................................................... 144
4 L6 R2 `' c+ yPlated-Through-Hole Via............................................................. 146
% _7 t9 w1 _# S E0 YModel Techniques................................................................... 147
$ K6 n( s, }" c. O" y+ y# s0 LPre-Layout Approximation ..................................................... 1482 w2 N' y8 _/ @. V: {9 C5 O9 B6 y
Pre-Layout Modeling .............................................................. 148
; |! N. m5 M0 H, f: r# V( yPost-Layout ............................................................................. 149
; o- i1 E: k1 x. XConnectors.................................................................................... 150
% n X" |5 E3 B5 J# s4 V( GConnector Variability.............................................................. 150
% p# S3 D! G9 a& ZSignal Selection....................................................................... 1501 k- ?% O) ] ]7 N
Separated Via Models............................................................. 152( n% B4 | h. t/ x
Unconnected Pins.................................................................... 153
0 L9 ~/ I e, z/ x, x9 PPhysical Features..................................................................... 1542 S" U% j0 @- O# N
Design Optimization ............................................................... 154
6 H8 C, y P7 Q# Y, E' PPackages....................................................................................... 156
1 A8 E/ V- N& z3 K/ mC4 Escape................................................................................ 158
9 Q3 S: g& l" o* e6 ]3 R& x. {vi Contents$ {# u4 v7 {+ K+ u9 N* L; g
Transmission Line................................................................... 158
6 G' B+ Z7 c C) p# {/ ^PTH Via .................................................................................. 1601 g, c; _$ L1 C9 ?' y: Y1 C
BGA Model............................................................................. 160
- Z k& V+ ~4 dSignal Selection for 3D Package Structures........................... 161* V! H% V5 l' S3 k
References ....................................................................................161) H) W7 T6 j) \, _6 h
CHAPTER 4 Link Circuits and Architecture .......................................... 163 D* y- |7 G' J9 ?2 i
Types of Link Circuit Architectures............................................163
7 |; o7 G( W( ]( G; ^Embedded Clock Architecture................................................ 163
) S/ W! _5 [& I2 `$ G7 g$ dForwarded Clock Architecture................................................ 164
0 \4 m; c; K! I; h+ K+ TTermination ..................................................................................165' B* ]( n' z# ]# x+ z
DC and AC Coupling.............................................................. 165
( O% l3 \7 ]2 M, Y1 j* W# pTermination Type.................................................................... 166+ E) K( o9 F$ Z' x% Y
Termination Circuits ............................................................... 167# j. s% b( p5 r p0 x) [
Termination Calibration Circuits............................................ 168
; a# L5 ]# c6 J8 ?/ ~$ GTermination Detection Circuits .............................................. 169
0 _0 Z1 a( E: I1 DTransmitter ...................................................................................170
3 A" b2 P0 g/ T% @Transmitter Equalization......................................................... 171
# A) H0 V w% ETransmitter Data Path ............................................................. 173
) _/ i" d6 B4 V' I* K0 P8 j9 ECurrent-Mode Driver .............................................................. 174
/ u1 L! n! s4 s; jVoltage-Mode Driver.............................................................. 177
$ c0 H, }6 `/ \) r wReceiver........................................................................................179
. t; D/ w+ q# N/ G# wReceiver Equalization ............................................................. 180
- j# H: s9 q* O- Z" r: r% Q% XReceiver Data Path.................................................................. 182
1 D, _; K) z6 JContinuous-Time Linear Equalizer ........................................ 184* M1 b* f0 w$ W7 p g" c0 }
Decision Feedback Equalizer.................................................. 184+ Q# X& f" A! P. z
Data Sampler........................................................................... 186
: d* a- h, H; |- k. V$ jError Sampler.......................................................................... 186
. a3 h+ _$ {; L2 s+ K! D1 P, s! s: Q; KReceiver Calibration ............................................................... 187
- M3 |8 }/ w/ z1 ?5 r' K1 zReceiver Adaptation................................................................ 1889 c; q' ^; t( u
Clock and Data Recovery............................................................190
1 L! o* W6 V3 m. k8 x) @0 ]Clock and Data Recovery Loop ............................................. 191% n; t' c$ H* x Q5 t; f
Phase Detectors....................................................................... 192
) G: H( Z' n4 D- r2 [! X4 UForwarded Clock Receiver ..........................................................1956 m2 R9 t+ o( G& u5 Q4 A/ u! d
Delay-Locked Loop ................................................................ 195
. A: t5 w8 u' G" FDesign for Test/Manufacture.......................................................195! l: d& {4 L6 E# p0 k
Analog DFx Features .............................................................. 196& e; e) a% e0 @+ J( h: t
Digital DFx Features............................................................... 196
. K J" l) d' G! c; R* sReferences ....................................................................................198
3 C, l2 a' P' uCHAPTER 5 Measurement and Data Acquisition Techniques............... 199
! t5 M4 G" S; _3 KDigital Oscilloscope Measurement..............................................199& C& q& J3 X/ f! }" e
Real-Time and Equivalent-Time Sampling Scopes ............... 1997 w) f7 M# Q/ q1 v. l- Y; j* T6 ^
Contents vii" Z( c$ q9 o; s
Bandwidth ............................................................................... 200
" H7 Z& @, D' h1 l: } i3 \* {Scope Digital Filter Applications ........................................... 2026 R) N0 s4 s4 ~
TDR Measurements ..................................................................... 204( G* y& Y. B; e1 U, b4 `
De-skew Differential Pairs with TDR .................................... 205
0 Y) U: Q9 M) uChannel Characterization with TDR ...................................... 207
) r* L1 r: H5 j$ j# \7 |0 b$ L6 EReturn Loss Measurement with TDR..................................... 209
/ N4 M: i; r$ H% z1 kVector Network Analyzer Measurement..................................... 211! E% l$ j, t7 g* h; ~. A
What is VNA?......................................................................... 211
9 t" C* d! s! F) i5 W% BVNA Error Sources and Calibration....................................... 213
7 N+ ?0 m2 |" R: TFull Two-Port SOLT Calibration Procedure .......................... 217
9 H* R- F T; DExample of Measurement Using VNA................................... 217. T$ G1 E2 \% j0 s
VNA Measurement Procedure................................................ 218
" B1 A9 f& G* i! n4 OReferences .................................................................................... 2196 P5 Q8 B; |: U% d
CHAPTER 6 Designing and Validating with Intel Processors............... 221
T7 n0 U* o! sDesigning Systems with Intel Devices........................................ 221
* T1 H9 b6 p* z: \+ d% F! zInterconnect Model ................................................................. 221( b B+ S( e/ L& x
Equalization Models ............................................................... 2230 ~1 G2 M" e3 e7 n2 T0 c
Automatic Equalization Adaptation ....................................... 225- N- Z& ~ T n* g- Q2 a
Performance Analysis ............................................................. 227
! `; p" ?; O: L. SSolution from Design of Experiments.................................... 2325 u$ _7 g; r0 Z+ h) L3 n6 v
Solution from Typical Models................................................ 234
, w3 o1 a1 O/ e8 x3 xSystem Validation with Intel Devices ......................................... 237) V+ J5 I4 p/ e7 {# J8 Z
Power-on Preparations ............................................................ 237
" D, K* r* [4 ? ?& @1 E, u1 f4 I VTypes of I/O Design Validation ............................................. 238" o; c" Z! F1 |4 V9 A
System Margining Validation Overview................................ 239- L3 y D; q D
DDR System Margining Validation ....................................... 244
+ O! x! D+ i- ^" I- [% ]High-Speed Serial I/O Margining Validation ........................ 246
+ n9 u( j1 p) o" Z9 ?Low-Margin Debug Guidance ................................................ 249( C# N7 D7 j I* `" t
Summary ...................................................................................... 250
3 a) v9 J, v+ V6 FReferences .................................................................................... 250
( ?6 x: v n. ]% F$ KIndex .............................................................................................................+ @; C4 t& Z# N+ M( E: f
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发表于 2017-7-6 14:49
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