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高速数字信号设计和高速互连
# i. G" t# i! n, ^* b9 t; o9 BCHAPTER 1 Transmission Line Fundamentals.......................................... 1
8 p" K; u7 E5 X4 w; n) ]Basic Electromagnetics.................................................................... 1
) h: D! g. e& i1 K, P8 ]( y' nElectromagnetics Field Theory................................................... 1: ^! C1 ^8 ]. _9 T
Propagation of Plane Waves....................................................... 61 l; V( F! t% D% `! V# q9 T4 a
Transmission Line Theory............................................................. 10* ~: a+ g* R9 G/ ?$ j1 \) }
Wave Equations on Lossless Transmission Lines.................... 11
& V* i; e- ]1 Y" b T" l! a3 IImpedance, Reflection Coefficient, and Power Flow: j! R% Q: Y$ D' X
on a Lossless Transmission Line......................................... 14
( C# M+ C" `7 l) t1 U# y8 g- CTraveling and Standing Waves on a Transmission Line ......... 16. N8 u1 `7 A" h! ~" |# Q
Transmission Line Structures ........................................................ 18
. [: ]& |1 }0 aStripline ..................................................................................... 195 q3 ?/ Y ]- c( d6 W0 z
Microstrip.................................................................................. 20/ X9 O. U7 b; C
Coplanar Waveguides ............................................................... 210 A$ C) l* J" R, w
Novel Transmission Lines ........................................................ 22
2 x- A. z, y2 f6 u+ u: _References ...................................................................................... 26
$ ?/ H% h) C' |, c- `" `CHAPTER 2 PCB design for Signal Integrity........................................... 27, _/ B5 C- Y i# r4 o9 G/ U6 r+ [
Differential Signaling..................................................................... 27/ {4 E2 A# I% E( R: z- i$ S) Z
Impedance ................................................................................. 283 J3 Z+ Q! K! [: e; `# C9 o
Time Domain Analysis .................................................................. 31
* |5 u- B5 E9 ^7 s. P. F0 DEye Diagram ............................................................................. 31# l( {9 M/ @! `; F0 m
Jitter........................................................................................... 33
) }) o* I% m2 dFrequency Domain Analysis.......................................................... 42
- h9 S0 S5 I; j0 x0 ]( J; GSpectral Content........................................................................ 42
H% U/ t2 B( Y- m7 i* g) JInsertion Loss............................................................................ 44( p+ W* z6 i% }' R% x
Integrated Insertion Loss Noise................................................ 467 ^' P* x2 I+ {" H3 M) l) C8 ], Y8 J
Return Loss ............................................................................... 49
) A! Y; Z- W7 }! V) |; b8 x; |Crosstalk.................................................................................... 51* @& u) R; X& \. I1 C0 h ^. _
Integrated Crosstalk .................................................................. 54
9 _) E1 \# f3 o5 P% Q* kSignal-to-Noise Ratio................................................................ 55+ Q0 r2 n- ]5 ?+ E/ e; a
Stack-Up Design ............................................................................ 58
. c$ n3 H( f9 m+ l5 H* B" cImpedance Target (Routing Impedance) .................................. 59$ K# g& O2 [4 F! a L
PCB Losses ............................................................................... 613 N }1 m+ V* k
Dielectric Loss .......................................................................... 62! T6 M8 C x" T" \' u# F' ?
Conductor Loss ......................................................................... 65
( y3 P; k1 M$ l# z" j5 X$ cCrosstalk Mitigation through StackUp..................................... 68
+ S/ a/ N6 i, ~Dual Stripline ............................................................................ 73
7 k- @) t* c/ V4 g& Qv
0 [0 W3 E$ Q$ @- \* L6 CDensely Broadside Coupled Dual Stripline.............................. 84
6 w1 O( Y1 a1 q# EVia Stub Mitigation .................................................................. 86
- v6 k# [( p1 T4 l! N$ Y4 fPCB Layout Optimization ............................................................. 95
4 O9 k9 p. ]/ l! m9 Y$ a- QLength Matching....................................................................... 962 g/ d/ ]0 M3 @, Y" J
Fiber Weave Effect ................................................................... 99
{, H$ {2 ^: Z' GCrosstalk Reduction ................................................................ 101" p& j; w7 p( H% T0 ~8 ?$ D
Non-Ideal Return Path ............................................................ 107
/ l( O' w" B, \# G/ y8 B6 lPower Integrity........................................................................ 110/ B+ l( N0 P# j1 j, i% I+ h ?
Repeaters ................................................................................. 111+ s5 t9 i8 R! m, z
References .................................................................................... 115
1 y7 D0 O7 e9 F5 b( \8 s" e' HCHAPTER 3 Channel Modeling and Simulation.................................... 1175 ~. z w# U' p6 U7 A
Transmission Lines ...................................................................... 117
5 o+ i( u. t) X& b! ^7 tCausality.................................................................................. 117& C* |- Y9 x* Z) c- k! ?
Checking for Model Causality................................................ 118
8 r, \, ^+ z( s3 RCausal Frequency-Dependent Model...................................... 120& Y" P: r$ ~% P
Copper Surface Roughness..................................................... 1219 }+ T& c3 {; K" ~
Conductivity............................................................................ 126
6 M l6 ]- ~* T0 UEnvironmental Impact............................................................. 127
* A9 X ^6 J0 F6 [Model Geometries................................................................... 130
+ N- q8 q) Z% S& qCorner Models......................................................................... 133
/ {+ j+ j' _6 K; V( P$ z* ^Ideal Assumptions: Homogeneous Impedance....................... 137
4 L/ D5 D1 c/ u: f# A- ]Ideal Assumptions: Crosstalk Aggressors .............................. 1377 l7 V/ N. N+ z( d
Transmitters.................................................................................. 138
0 X4 E) M) @7 H# j: R( cIBIS Models ............................................................................ 138
* z8 c h, Z" }3 I/ @, BSpice Voltage Source Model .................................................. 1394 c, w" @% c" c
3D Modeling ................................................................................ 141
1 V; e% d3 H! ^Ports/Terminals ....................................................................... 1428 m7 Z/ f$ o. [3 e4 T6 e
Model Analysis Settings ......................................................... 144
4 {% |- r0 T8 ^0 LPlated-Through-Hole Via............................................................. 146
" \& w, I3 x, HModel Techniques................................................................... 147
: d9 @& X4 K5 p. m% y* f1 KPre-Layout Approximation ..................................................... 148
4 l, U1 A4 z# wPre-Layout Modeling .............................................................. 148* O9 V, y4 N+ C5 U
Post-Layout ............................................................................. 1491 i+ t" k5 \6 W4 T* E0 @
Connectors.................................................................................... 150$ t: S9 Z$ |6 k5 V0 ~
Connector Variability.............................................................. 150" P8 s& s* E' M, V$ M+ k3 o
Signal Selection....................................................................... 1506 a! r6 a' n5 ] W! V+ ?
Separated Via Models............................................................. 152
3 B3 O- r3 K" g% C0 w& yUnconnected Pins.................................................................... 153
) Y( K" W& p1 ~8 S, l6 HPhysical Features..................................................................... 154: W3 k7 o o! r
Design Optimization ............................................................... 154" B3 L, q5 z; m$ M0 N; \# o7 r
Packages....................................................................................... 156
6 [ N: p4 j9 \8 d- GC4 Escape................................................................................ 158% h# m* D: J3 C& v
vi Contents
. w2 g0 a3 b/ c6 l: CTransmission Line................................................................... 158' o" T, C* n. L, X
PTH Via .................................................................................. 160: A7 Y/ c% _% h, j8 H% t
BGA Model............................................................................. 160% Y: d7 N) |; v! t
Signal Selection for 3D Package Structures........................... 161* }4 X/ x" M- F
References ....................................................................................1615 s, Z' L: z; ?8 w
CHAPTER 4 Link Circuits and Architecture .......................................... 163) M. r/ @# P B$ ` T; M& i
Types of Link Circuit Architectures............................................163
# l( P# _) \9 V2 YEmbedded Clock Architecture................................................ 1631 m4 ?! n) s6 ]! q
Forwarded Clock Architecture................................................ 164: B7 m$ ?) `3 v6 N) L: A u8 k+ a4 J
Termination ..................................................................................165
* p2 u9 ^5 I8 j9 m% U7 v5 HDC and AC Coupling.............................................................. 165" k9 ~$ M8 I7 o7 H1 X6 ]
Termination Type.................................................................... 166
- J5 S4 j; B; E* g, F* cTermination Circuits ............................................................... 167" x) ^# K0 s' U3 ?2 I0 |
Termination Calibration Circuits............................................ 168
' L7 S# S$ ]& X8 ATermination Detection Circuits .............................................. 169* r+ X! j) X5 e
Transmitter ...................................................................................170
" n: {6 g5 |0 K% d4 B6 r+ {; pTransmitter Equalization......................................................... 171
6 H( a0 n* w0 G; u& C4 H KTransmitter Data Path ............................................................. 173' a& w( g* Y7 L% n2 u; Q6 D
Current-Mode Driver .............................................................. 1741 w3 n, B+ D6 o( u* a" s& _
Voltage-Mode Driver.............................................................. 177$ d3 `# s% V- S7 e) s
Receiver........................................................................................1794 n; d9 R7 K4 o# T2 Z7 f
Receiver Equalization ............................................................. 180
) |& P! ~! d5 G# I$ @, m: {: S6 IReceiver Data Path.................................................................. 182# Y4 d' K c7 \# C' t! V
Continuous-Time Linear Equalizer ........................................ 184
) [) z( D' `0 T+ F) C) g: P4 K4 g1 LDecision Feedback Equalizer.................................................. 184
5 Y3 S1 r* g# S- i% [7 j/ i4 u) x4 pData Sampler........................................................................... 186
4 L. c$ ?7 V' H1 @2 aError Sampler.......................................................................... 186
- w5 f% G8 ^9 O5 i" ^. y, `Receiver Calibration ............................................................... 187
, Z8 i% i" m0 `" VReceiver Adaptation................................................................ 188( _$ t' |/ R# U4 d& @( K
Clock and Data Recovery............................................................190/ l- F/ o4 ~$ r+ {2 o, o
Clock and Data Recovery Loop ............................................. 191
7 X6 @% f+ d7 {3 EPhase Detectors....................................................................... 192. \2 d& g6 B+ o; W
Forwarded Clock Receiver ..........................................................195
+ G- ?, ^% B' T* p, P2 M/ a) ^, A# h2 p" }Delay-Locked Loop ................................................................ 195
6 q s6 g+ p( ]2 i0 ZDesign for Test/Manufacture.......................................................195) ^! p, V6 \$ j, u4 o
Analog DFx Features .............................................................. 196
# Y3 ~) Z3 g! W$ E7 D; ]Digital DFx Features............................................................... 196' ^5 |$ a# q+ P4 v. O6 A# Y9 g
References ....................................................................................1985 @/ M" f8 H' D. J
CHAPTER 5 Measurement and Data Acquisition Techniques............... 199
, D, J) B0 a6 x& ~- j& n! }Digital Oscilloscope Measurement..............................................199
6 y% N' w7 N% {, t9 B) s6 f/ T5 i4 sReal-Time and Equivalent-Time Sampling Scopes ............... 1991 c7 g# `) q3 i& L9 P" E
Contents vii
! `$ } m, c. m1 g7 YBandwidth ............................................................................... 200
9 g2 ?9 n7 S% a f% J+ ]7 s& g4 S# UScope Digital Filter Applications ........................................... 202
3 L ?2 F$ h! Y O: F/ B2 @, W6 ~TDR Measurements ..................................................................... 204
]! H7 c( U2 i5 H6 jDe-skew Differential Pairs with TDR .................................... 205
* y& Q1 B* f& OChannel Characterization with TDR ...................................... 207" @7 t# V4 V; S$ d
Return Loss Measurement with TDR..................................... 209: F) ^+ n k3 c% c+ t. P( R
Vector Network Analyzer Measurement..................................... 211
/ i& |# A. k% NWhat is VNA?......................................................................... 211
- r7 ]- m. u# _ |7 g3 kVNA Error Sources and Calibration....................................... 213. M: W' a0 T1 p4 g
Full Two-Port SOLT Calibration Procedure .......................... 217" |6 q* M# {) k
Example of Measurement Using VNA................................... 217
+ Q1 E/ g* {9 v- W0 @VNA Measurement Procedure................................................ 218
; @9 J6 ~- v {References .................................................................................... 219
5 c% T. d2 `: P- Y3 }0 fCHAPTER 6 Designing and Validating with Intel Processors............... 221
- G K6 }! g! E! I% D/ TDesigning Systems with Intel Devices........................................ 221
8 b$ c# I9 d* Y8 WInterconnect Model ................................................................. 221+ b4 V0 f8 y) O) S" ?1 B: @, U* v
Equalization Models ............................................................... 223& n7 Y, S5 u# @
Automatic Equalization Adaptation ....................................... 225
9 r* T' C2 J4 W* S7 V1 X$ aPerformance Analysis ............................................................. 227& q( [. M& i* A, g/ G. J' H! A4 Q
Solution from Design of Experiments.................................... 232
3 ~, w. k; z1 _2 k7 HSolution from Typical Models................................................ 234
% p, H+ u! q1 J Y8 W8 a% x! SSystem Validation with Intel Devices ......................................... 2377 O* Y% S6 c. t8 T% x
Power-on Preparations ............................................................ 2372 y0 Z ~: ?" Y5 y$ `6 z% A
Types of I/O Design Validation ............................................. 238
j8 d% v/ V# r" C7 h9 FSystem Margining Validation Overview................................ 2391 k6 _6 V w1 y+ z ]7 H" h/ A
DDR System Margining Validation ....................................... 2448 Y% Q* Q0 S, v( s1 a4 o! Z) s
High-Speed Serial I/O Margining Validation ........................ 246
! G" k6 Y" o9 z+ b$ m3 W/ K4 nLow-Margin Debug Guidance ................................................ 249
$ s4 j1 }- @" g j! Z8 FSummary ...................................................................................... 250# X- Y# k, \. g. m$ d$ Z
References .................................................................................... 250/ E7 J9 K4 X' N; X* I% [. z
Index .............................................................................................................
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