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Since the earliest days of microprocessors, system designers have been plagued by a problem in which the
% l5 a5 g# |7 w- f. t2 C }2 cspeed of the CPU's operation exceeded the bandwidth of the memory subsystem to which it was connected.
( O h2 I# g$ i# h3 f qTo avoid wasting CPU cycles while waiting for the memory to fetch the requested data, the universally+ G9 h- B+ v$ }( C
adopted solution was to use an area of faster (and thus more expensive) memory to cache main memory data.+ Z$ l7 I8 o1 b! [
This solution allowed the CPU to operate at its natural speed as long as the data it required was available in
- x3 }8 s \# b. O, Ethe cache. |
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